CN102547281A - Joint photographic experts group (JPEG) image compression concurrency control method based on digital signal processor (DSP) - Google Patents
Joint photographic experts group (JPEG) image compression concurrency control method based on digital signal processor (DSP) Download PDFInfo
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Abstract
The invention relates to a joint photographic experts group (JPEG) image compression concurrency control method based on a digital signal processor (DSP), which comprises the following steps: adjusting a JPEG algorithm structure, adopting a step-by-step completed strategy for image data partitioning operation, namely encoding while partitioning, and simultaneously transferring partitioned data block units into an internal memory to be processed; opening up two memory areas in the internal memory; dividing JPEG algorithm by combination with encoding structure characteristics and a hardware structure of the DSP, achieving concurrency completion in the two memory areas in the internal memory through the DSP and a peripheral device enhanced direct memory access (EDMA), and achieving concurrent execution of the JPEG algorithm on the DSP based on the concurrency completion. The JPEG image compression concurrency control method prevents a processor from reading and writing an external memory, greatly prolongs JPEG encoding time, provides conditions for JPEG real-time processing, and improves utilization rate and algorithm execution efficiency of the DSP.
Description
Technical field
The present invention relates to the Image Compression in a kind of digital information technology, a kind of specifically jpeg image compression concurrency control method based on DSP.
Background technology
JPEG (Joint Photographic Experts Group) is the committee that under the International Organization for Standardization leader, formulates the still image compression standard, and the first international still image compression standard ISO 10918-1 of cover (JPEG) is exactly that this committee formulates.Because the good quality of JPEG makes
ItsObtain great success in recent years, be widely used in the Internet and digital camera field.Jpeg format is a most popular picture format on the present network, is can be File Compress to minimum form, and 80% image has all adopted the JPEG compression standard on the website.Yet JPEG compression algorithm complexity is high, coding rate is slow, and is higher to the hardware handles Capability Requirement that algorithm is realized.
DSP (digital signal processor) is a kind of microprocessor of uniqueness; It is the device of handling bulk information with digital signal; Having data-handling capacity and programmability at a high speed, is the embedded processing chip that becomes more and more important in the digitalized electron world.The powerful data-handling capacity of DSP and the high speed of service not only are embodied on the kernel processes ability, more are embodied in its peripheral hardware interface with high integration and coprocessor EDMA etc., have guaranteed the concurrency of DSP data processing and peripheral unit control.
DSP at first will handle each piece the view data piecemeal carrying out jpeg image when compression afterwards, is discrete cosine transform, quantification, Z-transformation successively, encodes, is combined into code stream, jpeg coder as shown in Figure 1.After deblocking was accomplished, except cataloged procedure has the continuity requirement to data block, all the other operations all were independently to the processing of each piece.So when carrying out the JPEG compression:
1. externally create in the memory one with the onesize storage area preservation image block of image after data;
2. each blocks of data unit is carried out discrete cosine transform, quantification, Z-transformation, encodes, is combined into code stream.
Because image data amount is big, when carrying out deblocking, has destroyed the continuity of view data, so need externally to open a memory block in the memory again the view data behind the preservation piecemeal.Carrying out the moving in the process of view data, be simultaneously external memory storage to be carried out read-write operation, must influence the execution efficient of DSP.
When carrying out subsequent operation, action needs such as discrete cosine transform, quantification, coding carry out lot of data to be handled, and can data block be moved in the internal memory and operate.After accomplishing the moving of data block, it is carried out subsequent operation such as discrete cosine transform after, the data code flow that generates is write in the external memory storage, carry out moving of next data block afterwards, accomplish the encoding operation of each data block successively.Will visit in a large number external memory storage like this, and the sequential processes of data, have a strong impact on the concurrency that program is carried out, processor and peripheral hardware thereof are not effectively utilized, influenced the operating efficiency of DSP.
Summary of the invention
The sequential processes of data has a strong impact on the concurrency that program is carried out when in the prior art data being compressed; Influence the weak points such as operating efficiency of DSP, but the technical problem that the present invention will solve provides a kind of JPEG code optimization method based on DSP of practicality and high efficiency parallel control.
For solving the problems of the technologies described above, the technical scheme that the present invention adopts is:
The present invention is based on the jpeg image compression concurrency control method of DSP, it is characterized in that may further comprise the steps:
Adjustment jpeg algorithm structure, view data divides block operations to adopt the strategy of progressively accomplishing, and promptly limit piecemeal limit coding is moved the data block unit behind the piecemeal in the internal memory simultaneously and is handled;
In internal memory, open up two memory blocks;
In conjunction with the coding structure characteristics of JPEG and the hardware configuration of DSP, jpeg algorithm is divided, walk abreast by DSP and ancillary equipment EDMA thereof in two memory blocks of internal memory and accomplish, realize the executed in parallel of jpeg algorithm on DSP on this basis.
In internal memory, opening up two memory blocks is: two memory blocks are set in internal memory, i.e. and first memory block and second memory block, and utilize EDMA to set up ping-pong structure.
Jpeg algorithm in the executed in parallel on the DSP is: when DSP accomplishes the data processing to first memory block; EDMA has accomplished the data-moving of second video data block in second memory block; DSP is provided with EDMA another area data of image is moved in first memory block; DSP changes the view data of handling in second memory block simultaneously, and so circulation is all finished dealing with until the image block partial data.
The JPEG coding generates the JPEG compressed bit stream through deblocking, discrete cosine transform, quantification, Z-transformation, Huffman encoding and code stream combination.
The present invention has following beneficial effect and advantage:
1. the present invention utilizes the EDMA hardware of DSP, and with the jpeg algorithm separated into two parts, a part is accomplished by EDMA; A part is accomplished by the CPU of DSP; And make two parts executed in parallel, avoided processor read-write external memory storage, improved the JPEG scramble time greatly; For JPEG handles the condition that provides in real time, improve utilance and the algorithm of DSP and carry out efficient.
Description of drawings
Fig. 1 is the algorithm flow of jpeg coder;
Fig. 2 is the ping-pong structure figure of EDMA;
Fig. 3 realizes the flow chart of JPEG method for the present invention.
Embodiment
Below in conjunction with Figure of description the present invention is done further elaboration.
The jpeg image compression concurrency control method that the present invention is based on DSP may further comprise the steps:
Adjustment jpeg algorithm structure, view data divides block operations to adopt the strategy of progressively accomplishing, and promptly limit piecemeal limit coding is moved the data block unit behind the piecemeal in the internal memory simultaneously and is handled;
In internal memory, open up two memory blocks;
In conjunction with the coding structure characteristics of JPEG and the hardware configuration of DSP, jpeg algorithm is divided, walk abreast by DSP and ancillary equipment EDMA thereof in two memory blocks of internal memory and accomplish, realize the executed in parallel of jpeg algorithm on DSP on this basis.
In internal memory, opening up two memory blocks is: two memory blocks are set in internal memory, i.e. and first memory block and second memory block, and utilize EDMA to set up ping-pong structure.
Jpeg algorithm in the executed in parallel on the DSP is: when DSP accomplishes the data processing to first memory block; EDMA has accomplished the data-moving of second video data block in second memory block; DSP is provided with EDMA another area data (being equivalent to the 3rd video data block) of image-region is moved in first memory block; DSP changes the view data of handling in second memory block simultaneously, and so circulation is all finished dealing with until the image block partial data.
The present invention partly divides jpeg algorithm out with image block, is accomplished by EDMA, and utilizes EDMA to set up a ping-pong structure, and is as shown in Figure 2.
To internal memory, let processor do subsequent treatment the data-moving of piecemeal.At first in internal memory, define two 8 * 8 internal storage location A and B (i.e. first memory block and second memory block), be used to store 8 * 8 data cells of JPEG processed compressed, build ping-pong structure with EDMA.Initialization EDMA, with the original position of the raw address pointed image memory block of EDMA, destination address is set to the initial address of internal storage location A; Each unit of EDMA is set to a byte; Every frame is set to 8 unit, just in time is 8 pixels of delegation, and every is set to 8 frames; Generated 8 * 8 data blocks of 8 row, 8 row, EDMA just can extract from the image memory block and meet 8 * 8 required data blocks of JPEG coding like this.
After system obtains piece image, start EDMA, with 8 row, 8 row in the image upper left corner totally 64 data move among the internal storage location A.After EDMA accomplishes data-moving; Also accomplished the extraction operation of a data block; Processor is provided with EDMA with view data moving in internal storage location B afterwards; Processor carries out discrete cosine transform (being dct transform), quantification, Z-transformation, Huffman encoding, code stream combination operation to the data among the internal storage location A simultaneously, and after processor was accomplished the data processing to internal storage location A, EDMA can accomplish the data-moving of second video data block in internal storage location B fully; Processor is provided with EDMA view data is moved in internal storage location A, the view data among the processor processes internal storage location B.The realization flow of jpeg algorithm in DSP is as shown in Figure 3.The deblocking of jpeg algorithm and next code separated into two parts executed in parallel have avoided processor to visit external memory repeatedly, have improved the utilance of processor.
More than the jpeg image compression concurrency control method based on DSP provided by the present invention has been carried out detailed introduction; Principle of the present invention and embodiment are set forth; The principle of whole algorithm design has been explained in above execution mode explanation on the whole, helps to help to understand method of the present invention and core concept; Simultaneously, the those skilled in the art for the DSP exploitation can on execution mode and range of application, all have certain change part to its algorithm design and hardware arrangement according to thought of the present invention.
Claims (4)
1. the jpeg image based on DSP compresses concurrency control method, it is characterized in that may further comprise the steps:
Adjustment jpeg algorithm structure, view data divides block operations to adopt the strategy of progressively accomplishing, and promptly limit piecemeal limit coding is moved the data block unit behind the piecemeal in the internal memory simultaneously and is handled;
In internal memory, open up two memory blocks;
In conjunction with the coding structure characteristics of JPEG and the hardware configuration of DSP, jpeg algorithm is divided, walk abreast by DSP and ancillary equipment EDMA thereof in two memory blocks of internal memory and accomplish, realize the executed in parallel of jpeg algorithm on DSP on this basis.
2. by the described jpeg image compression concurrency control method of claim 1 based on DSP; It is characterized in that: in internal memory, opening up two memory blocks is: two memory blocks are set in internal memory; I.e. first memory block and second memory block, and utilize EDMA to set up ping-pong structure.
3. by the described jpeg image compression concurrency control method of claim 1 based on DSP; It is characterized in that: jpeg algorithm in the executed in parallel on the DSP is: when DSP accomplishes the data processing to first memory block; EDMA has accomplished the data-moving of second video data block in second memory block; DSP is provided with EDMA another area data of image is moved in first memory block; DSP changes the view data of handling in second memory block simultaneously, and so circulation is all finished dealing with until the image block partial data.
4. by the described jpeg image compression concurrency control method based on DSP of claim 1, it is characterized in that: the JPEG coding generates the JPEG compressed bit stream through deblocking, discrete cosine transform, quantification, Z-transformation, Huffman encoding and code stream combination.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102801981A (en) * | 2012-08-30 | 2012-11-28 | 西安空间无线电技术研究所 | Multipath compressed kernel parallel encoding control method on basis of JPEG-LS (Joint Pho-tographic Experts Group-Lossless Standard) algorithm |
| CN103678204A (en) * | 2013-12-30 | 2014-03-26 | 龙芯中科技术有限公司 | Processor and data processing method |
| CN111274996A (en) * | 2020-02-14 | 2020-06-12 | 深圳英飞拓智能技术有限公司 | Face picture feature comparison method and device, computer equipment and storage medium |
| CN114428595A (en) * | 2022-01-28 | 2022-05-03 | 深圳市爱协生科技有限公司 | Image processing method, image processing device, computer equipment and storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102801981A (en) * | 2012-08-30 | 2012-11-28 | 西安空间无线电技术研究所 | Multipath compressed kernel parallel encoding control method on basis of JPEG-LS (Joint Pho-tographic Experts Group-Lossless Standard) algorithm |
| CN102801981B (en) * | 2012-08-30 | 2015-04-22 | 西安空间无线电技术研究所 | Multipath compressed kernel parallel encoding control method on basis of JPEG-LS (Joint Pho-tographic Experts Group-Lossless Standard) algorithm |
| CN103678204A (en) * | 2013-12-30 | 2014-03-26 | 龙芯中科技术有限公司 | Processor and data processing method |
| CN103678204B (en) * | 2013-12-30 | 2017-02-15 | 龙芯中科技术有限公司 | Processor and data processing method |
| CN111274996A (en) * | 2020-02-14 | 2020-06-12 | 深圳英飞拓智能技术有限公司 | Face picture feature comparison method and device, computer equipment and storage medium |
| CN111274996B (en) * | 2020-02-14 | 2023-06-09 | 深圳英飞拓仁用信息有限公司 | Face picture feature comparison method, device, computer equipment and storage medium |
| CN114428595A (en) * | 2022-01-28 | 2022-05-03 | 深圳市爱协生科技有限公司 | Image processing method, image processing device, computer equipment and storage medium |
| CN114428595B (en) * | 2022-01-28 | 2024-05-31 | 深圳市爱协生科技股份有限公司 | Image processing method, device, computer equipment and storage medium |
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Application publication date: 20120704 |