CN106328044A - Led display screen control card and led display screen control system - Google Patents

Abstract

The present invention relates to an LED display screen control card and an LED display screen control system. The LED display screen control card comprises a microcontroller circuit or a microprocessor circuit, a dynamic random access memory, and a programmable logic device. The dynamic random access memory is externally connected with the programmable logic device. The microcontroller circuit or the microprocessor circuit can be adopted as a co-processor of the programmable logic device. The programmable logic device is provided with a resolution identification module, an input buffer, an RAM control module, an anti-color error processing module, a sub-pixel encoding module, and an output buffer. Therefore, the anti-color error processing function and the sub-pixel sampling function are realized. In this way, high-definition images are displayed at a limited cost or on an LED display screen relatively low in physical resolution.

Description

LED display controls card and LED display control system

Technical field

The present invention relates to image procossing and Display Technique field, particularly to a kind of LED display control Fabrication and a kind of LED display control system.

Background technology

Modern flat-panel display uses space law to synthesize color, each pixel bag on display mostly Containing the sub-pix that can produce three primary colours.When sub-pix spacing is sufficiently small, color will be occurred to mix Close phenomenon and present various different colours.The sub-pix of LED full-color display screen correspond to different base colors The light emitting diode of (such as red, green, blue three primary colours), under the control driving signal, three primary colours Present various different color by color mixture and constitute a LED pixel.Show at LED During screen display diagram picture, the pixel data of video source can the most intactly be mapped to LED and show In display screen.

The advantages such as LED full-color display screen is high with its luminosity, imaging area is big, almost occupy Whole indoor and outdoor large-scale display field.But by many-sides such as technical merit, manufacturing process and costs Restriction make that pel spacing is big, the low major obstacle becoming its development of restriction of resolution, also cause LED display is difficult to reach high-resolution and the definition of similar LCD, PDP flat faced display.Cause This, how to demonstrate on the LED display of limited cost or low resolution high-resolution, One of Main way of LED display area research during high resolution pictures.

Showing for realizing high-resolution LED, prior art has proposition LED sub-pix multiplex technique； But sub-pix multiplex technique only increases the addressability of system, improves displayable image Scale, but image can be caused to produce blurring effect, thus image definition can not be effectively improved.

Prior art also has the direct sub-pix down-sampling technology of proposition, and its single primary colours sub-pix is regarded as It is the full color pixel elementary cell as addressing, in the case of only considering brightness, can be notable The sample rate of raising system, demonstrates finer and smoother, picture clearly, and the perception increasing system divides Resolution；But, due to the spacing color mixed effect of human visual system, although after sub-pix down-sampling The image of display can produce the display effect basically identical with original image, but in actual applications, Along with being gradually increased of picture frequency, the color offset that sub-pix down-sampling produces causes original figure Part aliasing in image is the most clearly, it is seen that sub-pix down-sampling is with color Mistake is the perceived resolution that cost improves display system；Therefore, how to eliminate or weaken color mistake It it is the key of sub-pix down-sampling technological direction broader applications by mistake.

Summary of the invention

For deficiency of the prior art, the present invention proposes a kind of LED display and controls card, is suitable to electricity Connect LED display.Specifically, described LED display control card includes: microcontroller electricity Road or microcontroller circuit, dynamic RAM and PLD；Described dynamically Random access memory is external in described PLD, and described PLD includes: point Resolution identification module, input-buffer, RAM control module, anti-color error handling module, Asia Pixel coder module and output caching.Wherein, resolution identification module is for identifying input The resolution of raw image data；Input-buffer is used for after identifying described resolution described input Raw image data cache；RAM control module is used for controlling caching to described input The raw image data of caching writes described dynamic RAM；Anti-color error handling module is used Described in receiving and reading from described dynamic RAM under described RAM control module controls Raw image data also carries out convolution fortune according to the default size template raw image data to being received Calculate, to obtain the view data of anti-color fault processing and under described RAM control module controls The view data of described anti-color fault processing is stored to described dynamic RAM；Sub-pix Coding module is for receiving under described RAM control module controls from described dynamic RAM Read anti-color fault processing view data and described microcontroller circuit or microprocessor electricity Under the synergism on road, the view data to the anti-color fault processing received carries out adopting under sub-pix Sample is to obtain down-sampled images data；And output caching is for entering described down-sampled images data Row cache is for output.

Additionally, a kind of LED display control system that the embodiment of the present invention provides, be suitable to drive control LED display processed carries out image and shows, described LED display control system include sending card and Receiving card, described sending card be suitable to electrically connect host computer to obtain view data to be shown, described in connect Receiving card to be suitable to be connected electrically between described sending card and described LED display, described sending card includes Video decoding circuit, network code circuit, microcontroller circuit or microcontroller circuit, able to programme Logical device and be external in the dynamic RAM of described PLD, described can Programmed logic device is connected electrically between described video decoding circuit and described network code circuit.Institute State PLD to include: resolution identification module, input-buffer, RAM control module, Anti-color error handling module, sub-pix coding module and output caching.Wherein, resolution Identification module is for identifying the resolution of described view data to be shown；Input-buffer is for identifying After described resolution, described view data to be shown is cached；RAM control module is used for controlling Make and the view data to be shown of caching to described input-buffer is write described dynamic RAM； Anti-color error handling module for receive described RAM control module control under from described dynamically View data described to be shown that random access memory reads and according to default size template to being received View data to be shown carries out convolution algorithm, with obtain anti-color fault processing view data and The view data of described anti-color fault processing is stored to institute under controlling by described RAM control module State dynamic RAM；Sub-pix coding module is for obtaining described anti-color fault processing View data is followed by being received under described RAM control module controls to be read from described dynamic RAM The view data that takes and under the synergism of described microcontroller circuit or microcontroller circuit to institute The view data received carries out sub-pix down-sampling to obtain down-sampled images data；And output is slow Deposit for described down-sampled images data are cached for output.

Therefore, the above embodiment of the present invention can reach following one or more beneficial effect: (1) The system senses resolution of flat faced display can be improved, may apply on multiple flat faced display, And on same display, realize clearly showing of higher resolution picture, reduce display effect pair The rigors of hardware system physical resolution；(2) LED display display capabilities can be promoted, Sub-pix down-sampling technology is achieved under conditions of not changing original LED display control system And add anti-color fault processing, reduce owing to directly carrying out the color mistake that sub-pix down-sampling brings Problem by mistake, is effectively guaranteed the definition of picture while providing display resolution；(3) improve The compatibility of encoder, can select the most sub-according to the arrangement feature of LED display lamp point Pixel sampling mode encodes, and can realize different template Processing Algorithm simultaneously, and output is optimal Video source give LED display control system such that it is able to promote different lamp points arrangement LED The compatibility of display screen, also improves display effect simultaneously.

By the detailed description below with reference to accompanying drawing, the other side of the present invention and feature become obvious. It is understood that this accompanying drawing is only the purpose design rather than the model as the present invention explained The restriction enclosed, this is because it should refer to appended claims.It should also be noted that it is unless another Pointing out outward, it is not necessary to scale accompanying drawing, they only try hard to illustrate conceptually described herein Structure and flow process.

Accompanying drawing explanation

Below in conjunction with accompanying drawing, the detailed description of the invention of the present invention is described in detail.

A kind of based on sub-pix down-sampling the data encoding circuit that Fig. 1 provides for the embodiment of the present invention Structural representation.

Fig. 2 is the inside main functional modules schematic diagram of PLD shown in Fig. 1.

Fig. 3 be input-buffer shown in Fig. 2 realize block diagram.

Fig. 4 be anti-color error handling module shown in Fig. 2 realize block diagram.

Fig. 5 is that the anti-color fault processing traversal of the embodiment of the present invention realizes explanatory diagram.

Fig. 6 is 3 × 3 templates realization explanations that the present invention implements that the anti-color fault processing of end uses Figure.

Fig. 7 be sub-pix coding module shown in Fig. 2 and output caching realize block diagram.

Fig. 8 a and Fig. 8 b is that embodiment of the present invention PLD carries out 3 sub-pix down-samplings Corresponding physics sub-pix arrangement mode and sub-pix down-sampling principle schematic.

Fig. 9 a and Fig. 9 b is that embodiment of the present invention PLD carries out 4 sub-pix down-samplings Corresponding physics sub-pix arrangement mode and sub-pix down-sampling principle schematic.

Figure 10 be the embodiment of the present invention 4 sub-pix down-samplings after 4 sub-pictures in each pixel data Element color data restructuring output procedure schematic diagram.

Figure 11 is to use the structural representation of the LED display system of data encoding circuit shown in Fig. 1.

Figure 12 is that the sub-pix down sampling function of data encoding circuit shown in Fig. 1 is integrated into sending card The structural representation of LED display system.

Detailed description of the invention

Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with The detailed description of the invention of the present invention is described in detail by accompanying drawing.

Refer to Fig. 1, its a kind of based on sub-pix down-sampling number provided for the embodiment of the present invention Structural representation according to coding circuit.The data encoding circuit 10 of the present embodiment can be to video source figure As data (such as host computer video card output data) process, it utilizes PLD also Row processes the advantage of data, to defeated based on sub-pix down-sampling technology and anti-color error algorithms The high resolution original image data entered processes, and the down-sampled images data of its output can be made For the video source view data that flat faced display is new；Such that it is able to do not changing original display physics Improve the perceived resolution of system in the case of pixel scale and arrangement, show the finest and the smoothest clearly Picture.The present embodiment such as can solving practical problems: (1) solve fixed physical resolution display without The problem that Faxian shows higher resolution picture: after traditional display is produced, its maximum display divides Resolution just secures, if needing the picture showing higher resolution can only change higher resolution Display or carry out picture scaling, the display changing higher resolution can bring cost accordingly Increase, and picture zoom technology will certainly cause the loss of data, display effect to be deteriorated；(2) solve What the display effect that display system is brought due to the direct sub-pix down-sampling technology of employing was deteriorated asks Topic: current video data encoding circuit realizes based on direct sub-pix down-sampling Technology design, But directly sub-pix down-sampling can lose the high-frequency information of original image, produce color Problem-Error, Reduce the display effect of image.

Specifically, as it is shown in figure 1, the data encoding circuit 10 of the present embodiment includes: DVI decodes Circuit 11, PLD 13, dynamic RAM SDRAM1, SDRAM2, DVI Coding circuit 15 and MCU (Microcontroller, microcontroller) circuit 17.For ease of reason Solve, below with FPGA (Field Programmable Gate Array, field programmable gate array) Device is as the citing of PLD 13, but the present invention is not limited thereto, and it can also It it is the programming device of other similar FPGA.

Holding above-mentioned, the data encoding circuit 10 of this enforcement selects FPGA device as core processing portion Part, its peripheral interface circuit includes DVI decoding circuit 11, dynamic RAM SDRAM1, SDRAM2, DVI coding circuit 15, MCU circuit 17 and other necessary circuitry are such as FPGA configuration circuit (not shown in figure 1) etc..In the present embodiment, in order to realize high-definition picture Process real-time, select FPGA device as core processor, in design MCU circuit 17 MCU as the coprocessor of FPGA device FPGA device is carried out basic control, obtains Take the operation such as its duty, exchange data.Dynamic RAM SDRAM1, SDRAM2 are complete Become the storage of video signal Large Volume Data, anti-color fault processing and sub-pix down-sampling.DVI Decoding circuit 11 is used for realizing DVI signal format as a kind of video decoding circuit and turns rgb format, DVI coding circuit 15 is used for realizing rgb format as a kind of video coding circuit and turns DVI signal lattice Formula；In the present embodiment, the kind according to the signal format of input is different, it would however also be possible to employ other regard Frequently decoding circuit and video coding circuit, such as HDMI decoding circuit and HDMI coding circuit, very To being that the video signal format that video decoding circuit is used with video coding circuit is different, the present invention This is not restricted.

More specifically, when design requirement can the highest supports 1080P high clear video image process, The data volume that need to process is big, algorithm complexity is higher, data processing speed is fast, connection system Peripheral circuit pin is many, can select that processing speed is fast, there are 24624 logical blocks (LE), 66 M9K embedded memory modules, 4 phaselocked loops, maximum user's I/O pin numbers are The EP3C25F324C8 chip of 216 is as PLD 13.At DVI decoding circuit In 11 and DVI coding circuits 15, (DVI decodes core can to select the TFP401 chip of TI company Sheet) as TMDS (Transmission Minimized Differential Signaling, Littleization differential signal transmission) receptor, simultaneously select TFP410 as DVI coding chip；This The feature of two kinds of chips is low-power consumption and low noise, and supports that resolution is 1920 × 1080 simultaneously DVI signal processing.The bit wide of each pixel data of full color image of 1920 × 1080 is 24bits, committed memory size are about 48Mbits, it is desirable to when data transmission bauds is fast, Ke Yixuan With two panels K4S283233F-FC60 of Samsung as dynamic RAM SDRAM1, SDRAM2 carries out ping-pong buffer operation, and this chip high workload clock is 166MHz, memory space Size is 128Mbits, can meet the requirement of system transfers speed and memory space.

Referring to Fig. 2, it is the inside main functional modules schematic diagram of PLD 13. In the present embodiment, the whole flow chart of data processing of PLD 13 takes into full account " goes here and there and turns Change ", " ping-pong operation " and " streamline " these high speed design thoughts, with improve treatment effeciency, Realize the real-time process of system.The row of different resolution video signal, field sync signal, time clock frequency Rate, data transmission format etc. is different.The DVI decoding circuit 11 raw image data to input After the decoded image data being decoded obtaining enters PLD 13, resolution know Other module 131 is according to extending display identification data (Extended Display Identification Data, is called for short EDID) standard carries out image resolution ratio identification, according to the resolution configuration system identified The parameter of system correlation module.After resolution identification, view data enters input-buffer 133 Cache.The function of input-buffer 133 is to cache and raw image data at RAM in real time Be stored in order under the control of control module 135 external dynamic RAM such as SDRAM1, SDRAM2.Two dynamic RAMs SDRAM1, SDRAM are according to picture frame alternately storage herein From the view data of input-buffer 133, in the two field picture time, one of them dynamic random Memorizer is for storing raw image data that input-buffer 133 transmits and doing anti-color mistake Process, another dynamic RAM picture number after output one frame anti-color fault processing Carry out sub-pix down-sampling according to sub-pix coding module 137, thus realize the high-speed transfer of data. The function of sub-pix coding module 137 is to receive under the control of RAM control module 135 from dynamically View data after the anti-color fault processing that random access memory SDRAM1, SDRAM2 read, Under the control of MCU circuit 17, view data is carried out sub-pix down-sampling, produces down-sampled images number Output caching 139 is given according to (namely having changed the view data of resolution).The merit of output caching 139 Can be down-sampled images data to be exported to DVI coding circuit 15 according to standard display format, afterwards The down-sampled images data of DVI signal format are exported as new video source by DVI coding circuit 15 View data.

Referring to Fig. 3, it realizes block diagram for input-buffer 133 shown in Fig. 2.Due to existing SDRAM chip the most at most can only read and write 256 data, it is impossible to directly by a line image pixel number According to being stored in dynamic RAM SDRAM1, SDRAM2, so system needs to arrange input-buffer 133.Input-buffer 133 realizes the most slow of view data decoded to DVI decoding circuit 11 Deposit, and under the control of RAM control module 135, view data is write dynamic RAM In SDRAM1, SDRAM2.When peak demand processes the original image number that resolution is 1920 × 1080 According to, it is contemplated that system needs to arrange 12 dual port RAMs, and the storage resource of needs is more, therefore needs Resources on Chip is carried out reasonable disposition.Shown in Fig. 3 two dual port RAM, namely RAM1, RAM2 Bit wide can be set to 32bits, capacity is set to 1024.When one-row pixels quantity is more than 1024, One RAM cannot cache entire row of pixels data, needs two reasonably combined realizations of dual port RAM to scheme The real-time storage of picture；Concrete implementation mode combines the resolution of input picture and may determine that.

Referring to Fig. 4, it realizes block diagram for color error handling module 136 anti-shown in Fig. 2. The function of anti-color error handling module 136 is to realize DVI signal format input image data Anti-color fault processing, this process substantially a mask convolution process, template in the present embodiment The selection of size needs to consider from many-sides such as realizing precision, spent time, complexity. Using size in the present embodiment is the module of 3 × 3.Need after a two field picture has been cached part data The data of caching are carried out anti-color fault processing and are newly stored in SDRAM1, SDRAM2.? In anti-color fault processing, the pixel data of each position will repeatedly be revised, it is advantageous to be The dual port RAM being easy to addressing data and rewriting is selected to carry out data process.Divide when peak demand processes Resolution is the image of 1920 × 1080, four dual port RAMs in Fig. 4, namely RAM3, RAM4, RAM5 and RAM6, respectively access one-row pixels data, so dual port RAM 3, RAM4, RAM5 and The bit wide of RAM6 is set to 32bits, and the degree of depth is set to 2048.12 depositors, namely depositor 1 The data of 12 positions, wherein three dual port RAMs in four row pixels is stored respectively to depositor 12 9 pixel datas below cooperate and realize 3 × 3 quick processing template, another one RAM Caching next line image pixel data, each clock all can get the data of 3 × 3 templates, as Shown in Fig. 4 dot-dash wire frame, it achieves the pile line operation to data, has saved time, raising Data-handling efficiency.

Referring to Fig. 5, it realizes explanatory diagram for the present embodiment anti-color fault processing row traversal.? In Fig. 5, (n is m) pixel coordinate position in a sub-picture, represents that it is in line n M arranges.In Figure 5, be first in RAM3, RAM4 and RAM5 storage n-th, n+1 and N+2 row raw pixel data participates in 3 × 3 mask convolution computings, meanwhile starts in RAM6 to delay Deposit the n-th+3 row raw pixel data.Pixel data n-th, n+1 and n+2 row finishes template volume After long-pending computing, RAM6 is stored in the n-th+3 row raw pixel data.Now start to RAM4, In RAM5 and RAM6 storage (n+1)th, n+2 and n+3 row pixel data carry out module convolution algorithm, Simultaneously line n pixel data through module convolution algorithm in RAM3 is newly stored into former SDRAM In, and the n-th+4 untreated raw pixel data of row is stored in RAM3.As can be seen here, with for the moment Carve, four RAM have three carry out mask convolution computing, remaining one in RAM control module The data processed are re-write in SDRAM and by next line original image prime number under the control of 135 According to writing this RAM；By that analogy, move in circles, until by all pixel columns time of whole two field picture Go through.

Referring to Fig. 6, it realizes explanatory diagram for the present embodiment 3 × 3 template.Doing mask convolution fortune During calculation, it is assumed that first clock template is in Fig. 6 dotted line frame position, now depositor 3,6 And in 9 storage pixel be (n, m), (n+1, m) and (n+2, m).Finishing mask convolution fortune Need after calculation to be stored in corresponding RAM the first row pixel data in 3 × 3 templates, i.e. distinguish By in depositor 3,6 and 9 pixel (n, m), (n+1, m) and (n+2, m) be stored in RAM3, In RAM4 and RAM5.Through a clock template movement to the solid box position shown in Fig. 6, Now in depositor 3,6 and 9, the pixel of storage is (n, m+1), (n+1, m+1) and (n+2, m+1), After mask convolution computing equally by the pixel of storage in depositor 3,6 and 9 be (n, m+1), (n+1, And (n+2, m+1) is stored in RAM3, RAM4 and RAM5 respectively m+1).Again through a clock mould Plate continues one position of translation, the like, until template movement is to the end of one-row pixels, from And the mask convolution realizing each pixel data of full line processes.Like this, template is the most orderly The process shifting and doing corresponding computing is i.e. convolution algorithm, and the algorithm used during convolution algorithm can See Application No. filed in Xi'an Novastar Electronic Technology Co., Ltd. on 02 12nd, 2015 CN201510075267.1, invention entitled " image processing method and image processing apparatus " send out Bright patent application, its disclosed content quotation in this as reference, and dotted line frame pair in Fig. 6 Should 3 × 3 block of pixels in application for a patent for invention.It should be noted that needed for convolution algorithm time Between relevant with the complexity of algorithm.Before and after doing mask convolution computing, pixel value is possible to become Change, will be by the first row pixel in 3 × 3 templates so often having carried out a mask convolution process Data (final result) are newly stored into RAM.In module, other two row pixel datas are owing to continue ginseng With following mask convolution computing, its value is not final result, so temporarily need not storage.

Referring to Fig. 7, it caches 139 for sub-pix coding module shown in Fig. 2 137 and output Realize block diagram.The function of the combination of sub-pix coding module 137 and output caching 139 is to receive warp Cross the view data after anti-color fault processing and it is carried out sub-pix addressing and down-sampling, generating New video source view data exports to DVI coding circuit 15.Such as, sub-pix coding module 137 Being 32bits including four bit wides, capacity is the dual port RAM of 1024, namely RAM7, RAM8, RAM9 and RAM10, four RAM cooperatings realize the picture number through anti-color fault processing According to sub-pix down-sampling.Synchronization, two dual port RAMs are to adjacent two pixel column picture number According to carrying out sub-pix down-sampling (or claim sub-pix data encoding), output data give output caching 139 as the data source of new video, two other RAM caching two pixel column view data below, Thus realize generating date.Output caching 139 function be by new video data according to EDID standard also exports to DVI coding circuit 15 under the control of MCU circuit 17.The present embodiment In, output buffer setting has two bit wides to be 32bits, and capacity is the dual port RAM of 1024, namely RAM11 and RAM12.

Referring to Fig. 8 a and Fig. 8 b, it is sub-that it carries out 3 for embodiment of the present invention PLD Physics sub-pix arrangement mode corresponding to pixel down-sampling and sub-pix down-sampling principle schematic.

In Fig. 8 a, 3 physics sub-pixs of each physical picture element (as broken circle indicates) in Triangle-Profile, all physics sub-pixs equidistantly arrange so that between each physics sub-pix in Existing maximum discrete state；The advantage of this arrangement is that light-emitting area is big, can by addressing flexibly with Restructing algorithm makes existing device have bigger room for promotion in perceived resolution.For Fig. 8 a The triangular pitch mode of shown physics sub-pix, the PLD 13 of the present embodiment Such as view data after FPGA device antagonism color fault processing carries out Asia picture as shown in Figure 8 b Element addressing and down-sampling.High-resolution after dotted line upper area is anti-color fault processing in Fig. 8 b Both full-pixel view data, is through sub-pix addressing and the down-sampling figure of down-sampling output below dotted line As data (or claiming sub-pix color data).Assume dividing of the view data after anti-color fault processing Resolution is 6M × 6N (row × OK), coding gained down-sampling after 3 sub-pixs addressing with down-sampling The data volume of image drops to 4M × 3N.As can be seen here, 3 sub-pix down-samplings can be largely Reducing video data amount, do not affect display resolution simultaneously, this largely can reduce high score Distinguish the image requirement to display device physical resolution.At this it is understood that sub-pix is sampled It is the constraint casting aside original physical picture element in technical spirit, using sub-pix as display, the base of addressing Our unit, is equivalent to add reticular density in the condition not changing original display device, improves The sample rate of display system.

Referring to Fig. 9 a and Fig. 9 b, it is sub-that it carries out 4 for embodiment of the present invention PLD Physics sub-pix arrangement mode corresponding to pixel down-sampling and sub-pix down-sampling principle schematic.

In fig. 9 a, 4 physics sub-pixs of each physical picture element (as broken circle indicates) in Distributed rectangular, all physics sub-pixs equidistantly arrange so that present between each physics sub-pix Maximum discrete state；The advantage of this arrangement is that light-emitting area is big, can be by addressing flexibly and weight Structure algorithm makes existing device have bigger room for promotion in perceived resolution.For Fig. 9 a The rectanglar arrangement mode of shown physics sub-pix, the PLD 13 of the present embodiment is such as The sub-pix that view data after FPGA device antagonism color fault processing is carried out as shown in figure 9b is sought Location and down-sampling.High-resolution full figure after dotted line upper area is anti-color fault processing in Fig. 9 b Element view data, is through sub-pix addressing and the down-sampled images number of down-sampling output below dotted line According to (or claiming sub-pix color data).Assume the resolution of the view data after anti-color fault processing For 6M × 6N, after 4 sub-pix addressing with down-sampling, encode the data of gained down-sampled images Amount drops to 3M × 3N.As can be seen here, 4 sub-pix down-samplings can reduce display number largely According to amount, not affecting display resolution, this largely can reduce full resolution pricture to aobvious simultaneously Show the requirement of equipment physical resolution.

It addition, it is noted that transmit in major part DVI coding-decoding circuit is 24 very coloured silks Color (each 8 of R, G, B) data, and obtain in 4 sub-pix down-samplings shown in Fig. 9 b every One new pixel of 4 sub-pix 32 bit data compositions, cannot complete one newly by a clock The transmission of pixel.Although the data transfer mode of reality can have multiple, it is recommended here that use Figure 10 Shown mode, sub-pix data when the dotted line of band arrow reflects data actual transmissions in Figure 10 Reconfigure in process, namely down-sampled images data in each pixel data of same pixel column 4 sub-pix color data be split to two transmission pixel data (3 sub-pixs in Figure 10 Data combine) in export, correspondingly the PLD 13 in Fig. 2 can enter one Step configuration output control module realizes 4 sub-pix color data partition to control output caching 139 The function of output.Further, it is to be appreciated that the display at 4 sub-pix rectanglar arrangements terminates Figure 10 Yu Fig. 9 b can be contrasted again after receiving pixel data and carry out the reduction of pixel data.

Referring to Figure 11, it is for using the knot of the LED display system of data encoding circuit shown in Fig. 1 Structure schematic diagram.As shown in figure 11, data encoding circuit 10 receives the high score of host computer video card output Resolution raw image data that it is carried out output after anti-color fault processing and sub-pix down-sampling is anti- Color fault processing and down-sampled images data, the most anti-color fault processing and down-sampled images number Corresponding place is done according to the sequentially sending card 81 in LED display control system 80 and receiving card 83 Reason rear drive control LED display 100 carries out corresponding picture and shows.LED in Figure 11 shows Screen control system 80 is the LED display control system of prior art, and no further details to be given herein.

Referring to Figure 12, it is for by the anti-color fault processing of data encoding circuit shown in Fig. 1 and Asia Pixel down sampling function is integrated into the structural representation of the LED display system of sending card.Such as Figure 12 Shown in, LED display control system 90 receives the original high-resolution image of host computer video card output Data also carry out respective handling rear drive and control LED display 100 and carry out picture and show.Wherein, LED display control system 90 includes sending card 91 and receiving card 93, and the structure of receiving card 93 is adopted By prior art thus do not elaborate at this.As for sending card 91, it shows as a kind of LED Display screen controls card, including: DVI decoding circuit 11, PLD 913, dynamic random Memory storage SDRAM 1, SDRAM2, MCU circuit 17 and network code circuit 915；Wherein, DVI Decoding circuit 11, the structure of dynamic RAM SDRAM1, SDRAM2 and MCU circuit 17 and Function is identical with Fig. 1, does not repeats them here；Network code circuit 915 uses of the prior art Network encoder thus do not elaborate at this；For PLD 913, its except Having outside the functional module shown in Fig. 2, for realizing sending card function, it is the most also configured with Parallel serial conversion module (such as 24bit turns 8bit module), network output module, partitioning video data The functional module well-known to those skilled in the art such as module.

It addition, in other embodiments of the present invention, it is also possible to the programmable logic device shown in Fig. 2 The main functional modules (corresponding anti-color fault processing and sub-pix down sampling function) of part is integrated into it He controls card by LED display, such as, be integrated into asynchronous control-card.Additionally, above-mentioned LED display Control to block the MCU circuit 17 in such as sending card 91 can also replace to comprise the processors such as ARM Microcontroller circuit；As a example by asynchronous control-card, because generally itself is just provided with at ARM Reason device, so without the most additionally arranging MCU.

In sum, the above embodiment of the present invention can reach one or several beneficial effect following: (1) The system senses resolution of flat faced display can be improved, may apply on multiple flat faced display, And on same display, realize clearly showing of higher resolution picture, reduce display effect pair The rigors of hardware system physical resolution；(2) LED display display capabilities can be promoted, Sub-pix down-sampling technology is achieved under conditions of not changing original LED display control system And add anti-color fault processing, reduce owing to directly carrying out the color mistake that sub-pix down-sampling brings Problem by mistake, is effectively guaranteed the definition of picture while providing display resolution；(3) improve The compatibility of encoder, can select the most sub-according to the arrangement feature of LED display lamp point Pixel sampling mode encodes, and can realize different template Processing Algorithm simultaneously, and output is optimal Video source give LED display control system such that it is able to promote different lamp points arrangement LED The compatibility of display screen, also improves display effect simultaneously.

Additionally it is noted that the template that used of the convolution algorithm of the above embodiment of the present invention is big Little is 3 × 3, but the present invention is not limited thereto, and it can also use the template of other sizes, example Such as 2 × 2 templates, triangle template, correspondingly, the RAM in anti-color error handling module 136 Quantity and register number can do accommodation；Such as, as a example by 2 × 2 templates, now Anti-color error handling module 136 is such as provided with 3 internal dual port RAM and is each inside Dual port RAM 2 depositors of configuration.

So far, specific case Asia based on PLD to present invention picture used herein Element Downsapling method, PLD, data encoding circuit based on sub-pix down-sampling, LED display controls card and the principle of LED display control system and embodiment is explained Stating, the explanation of above example is only intended to help to understand method and the core concept thereof of the present invention； Simultaneously for one of ordinary skill in the art, according to the thought of the present invention, in specific embodiment party All will change in formula and range of application, in sum, this specification content should not be construed as Limitation of the present invention, protection scope of the present invention should be as the criterion with appended claim.

Claims (10)

1. a LED display controls card, is suitable to electrically connect LED display；It is characterized in that, Described LED display controls card and includes:

Microcontroller circuit or microcontroller circuit；

Dynamic RAM；And

PLD, described dynamic RAM is external in described PLD, Described PLD includes:

Resolution identification module, for identifying the resolution of the raw image data of input；

Input-buffer, is used for the original image number to described input after identifying described resolution According to caching；

RAM control module, for controlling the original image number of caching to described input-buffer According to writing described dynamic RAM；

Anti-color error handling module, for receiving under described RAM control module controls The described raw image data that reads from described dynamic RAM according to default size template pair The raw image data received carries out convolution algorithm, to obtain the picture number of anti-color fault processing According to and described RAM control module control under the view data of described anti-color fault processing is deposited Storage is to described dynamic RAM；

Sub-pix coding module, for receiving under described RAM control module controls from institute State the view data of the anti-color fault processing that dynamic RAM reads and at described microcontroller Picture number to the anti-color fault processing received under the synergism of circuit or microcontroller circuit According to carrying out sub-pix down-sampling to obtain down-sampled images data；And

Output caching, for caching for output described down-sampled images data.

2. LED display as claimed in claim 1 controls card, it is characterised in that when described dynamic When state random access memory includes the first dynamic RAM and the second dynamic RAM, one In the two field picture time, described first dynamic RAM is used for storing described input-buffer and is transmitted across Next raw image data also coordinates described anti-color error handling module to do anti-color fault processing, Described second dynamic RAM is for output one frame image data extremely described sub-pix coding module Carry out sub-pix down-sampling.

3. LED display as claimed in claim 1 controls card, it is characterised in that described anti-face Color error handling module includes in four internal dual port RAM and described four internal dual port RAM Each internal dual port RAM be configured with three depositors.

4. LED display as claimed in claim 1 controls card, it is characterised in that described default Big little module is 3 × 3 templates, 2 × 2 templates or triangle template.

5. LED display as claimed in claim 1 controls card, it is characterised in that described sub-picture Element data coding module includes four internal dual port RAM；To described four internal dual port RAM In the figure of adjacent two pixel column anti-color fault processing that stores respectively of two internal dual port RAM During carrying out described sub-pix down-sampling as data, in described four internal dual port RAM Another two internal dual port RAM be received and stored on respectively described RAM control module control under from The picture number of next adjacent two pixel column anti-color fault processing that described dynamic RAM reads According to.

6. a LED display control system, is suitable to drive control LED display to carry out image Display, described LED display control system includes that sending card and receiving card, described sending card are suitable to Electrical connection host computer is to obtain view data to be shown, described receiving card is suitable to be connected electrically in described sending out Between card feed and described LED display, described sending card includes video decoding circuit and network code Circuit；It is characterized in that, described sending card also includes:

Microcontroller circuit or microcontroller circuit, PLD and be external in described The dynamic RAM of PLD, described PLD is connected electrically in described Between video decoding circuit and described network code circuit；Wherein, described PLD bag Include:

Resolution identification module, for identifying the resolution of described view data to be shown；

Input-buffer, for entering described view data to be shown after identifying described resolution Row cache；

RAM control module, for controlling the figure to be shown of caching to described input-buffer As data write described dynamic RAM；

Anti-color error handling module, for receiving under described RAM control module controls The view data described to be shown that reads from described dynamic RAM according to default size template The view data to be shown received is carried out convolution algorithm, to obtain the figure of anti-color fault processing As data and described RAM control module control under by the picture number of described anti-color fault processing According to storing to described dynamic RAM；

Sub-pix coding module, in the view data obtaining described anti-color fault processing It is followed by being received under described RAM control module controls the image read from described dynamic RAM Data and under the synergism of described microcontroller circuit or microcontroller circuit to the figure received As data carry out sub-pix down-sampling to obtain down-sampled images data；And

Output caching, for caching for output described down-sampled images data.

7. LED display control system as claimed in claim 6, it is characterised in that when described When dynamic RAM includes the first dynamic RAM and the second dynamic RAM, In one two field picture time, described first dynamic RAM is used for storing the transmission of described input-buffer The raw image data that comes over also coordinates described anti-color error handling module to do at anti-color mistake Reason, described second dynamic RAM encodes to described sub-pix for output one frame image data Module carries out sub-pix down-sampling.

8. LED display control system as claimed in claim 6, it is characterised in that described anti- Color error handling module includes four internal dual port RAM and described four internal dual port RAM In each internal dual port RAM be configured with three depositors.

9. LED display control system as claimed in claim 6, it is characterised in that described pre- If big little module is 3 × 3 templates, 2 × 2 templates or triangle template.

10. LED display control system as claimed in claim 6, it is characterised in that described Sub-pix data coding module includes four internal dual port RAM；To described four internal dual port The adjacent two pixel column anti-color fault processing that two internal dual port RAM in RAM store respectively View data carry out described sub-pix down-sampling during, described four internal dual port RAM In another two internal dual port RAM be received and stored on respectively described RAM control module control Under the figure of next adjacent two pixel column anti-color fault processing that reads from described dynamic RAM As data.