CN107659800A - A kind of DMD high frame frequency and high resolutions synchronous dynamic display system - Google Patents
A kind of DMD high frame frequency and high resolutions synchronous dynamic display system Download PDFInfo
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- CN107659800A CN107659800A CN201710692977.8A CN201710692977A CN107659800A CN 107659800 A CN107659800 A CN 107659800A CN 201710692977 A CN201710692977 A CN 201710692977A CN 107659800 A CN107659800 A CN 107659800A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/12—Picture reproducers
- H04N9/31—Projection devices for colour picture display, e.g. using electronic spatial light modulators [ESLM]
- H04N9/3141—Constructional details thereof
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/12—Picture reproducers
- H04N9/31—Projection devices for colour picture display, e.g. using electronic spatial light modulators [ESLM]
- H04N9/3179—Video signal processing therefor
Abstract
The present invention relates to a kind of DMD high frame frequency and high resolutions synchronous dynamic display system, including：Host computer, interface module, control module, DMD；The host computer connects the interface module, for sending the view data of specific frame frequency；The interface module connects the control module, is decoded for receiving the view data of the specific frame frequency, and to described image data；The control module connects the DMD, for carrying out gray modulation and format conversion processing to decoded view data, to meet the display frame frequency of the DMD and display format, and the view data after processing is loaded into the DMD；The DMD is used to show the view data after the processing.The present invention can realize that high frame per second, real-time Transmission, high-resolution are shown, compensate for it is domestic lack in HWIL simulation field can utilize the defects of DMD is to high frame frequency, high grey scale image progress real-time display.
Description
Technical field
The invention belongs to technical field of image processing, and in particular to a kind of DMD high frame frequency and high resolutions synchronous dynamic is shown
System.
Background technology
Digital micro mirror projection system is a kind of reflecting light spatial modulator based on micro electromechanical structure, its core device
Part is the DMD (Digital Micromirror Device DMDs) of TI companies production.DMD is one by micro- anti-
Penetrate microscope group into micro mirror array, each micro mirror represents a pixel, by controlling the upset of micro mirror come the outside spoke of break-make light source
Penetrate.The device is now widely used in the projecting apparatus using DLP technologies, is developed in terms of visible ray projection more rapid.It is logical
Crossing the transmission window of replacing DMD micro mirrors can be used for infrared projection field, no matter applied to which light radiation wave band, DMD
What the control principle of micro mirror was just as, and the country does not also limit too much in DMD purchase, and this gives it to be led in military affairs
The application in domain starts to provide a great convenience.Compared to other Infrared scene generation systems, DMD have image resolution ratio it is high,
The advantages that uniformity is good, geometric form diminishes, frame frequency is high, energy is concentrated.
Shanghai Institute of Technical Physics, Harbin Institute of Technology, the Suo Deng research units of weapons 211 all change to DMD
Corresponding infrared image optical projection system is have developed on the basis of window.Wherein Kang Weimin of Harbin Institute of Technology et al. developed in 2008
The infrared dynamic scene simulator resolution ratio of DMD be 800 × 600, tonal gradation 8bit, frame frequency 60Hz, temperature resolution scale
For 0.1 DEG C, image flicker free is (referring to " Kang Weimin, Li Yanbin, the high big infrared dynamic scene simulator of will digital micromirror arrays
Development [J] is infrared and laser engineering, 2008, (05):753-756”)；Harbin Institute of Technology appoint state's great waves development based on DMD's
Visual light imaging Guidance System Simulation, frame frequency is up to 60Hz (referring to " visual light imaging guidance emulation systems of a state cover based on DMD
System design [D] Harbin Institute of Technology, 2016. ").The Zhang Kai of Northwestern Polytechnical University, Ma Jun et al. were in the base developed in 2011
It is 1024 × 768 in DMD infrared dynamic goal simulator resolution ratio, image is similarly tonal gradation 8bit, frame frequency 10-100
Continuously adjustabe is (referring to " Zhang Kai, the infrared dynamic goal simulator driving of Ma Jun, the good of grandson heir and Control System Design [J] laser
With infrared, 2011, (01):58-62. ", " beam is brave, Zhao Xiaobei, Ma Jun, Li Shaoyi, Infrared scene simulations of the Sun Li based on DMD
Device Hardware Design [J] infrared techniques, 2011, (12):683-686.”).The infrared projection system that weapons 211 are developed
Resolution ratio is 1024 × 768, and frame frequency has reached 100Hz.The base that Chinese Inst. of Air-to-Air Missiles Zhang Erlei, Qi Ming et al. are developed
100Hz is similarly in DMD Infrared scene simulation with image device frame frequency, energy contrast has reached 91:1 (referring to " Zhang Erlei, Qi Ming
Dynamic IR Scene generation system [J] electronics technologies based on DMD, 2011, (07):140-143.”).
However, the scheme of prior art has the following disadvantages：1st, existing DMD carries out the frame frequency that high gray level image is shown
It is not high.A width bianry image can only be given expression to by simply carrying out switching manipulation to DMD micro mirrors, wanted monolithic DMD and be can show that
Gray level image, it is necessary to which gray modulation is carried out to DMD.Traditional gray modulation algorithm, in the display of the high gray level image such as 8bit
During, frame frequency is difficult lifting more than 150Hz, it is impossible to meets the requirement of high frame per second.2nd, DMD image display lacks real-time.
The country is carried out in the development of the scenario simulation device based on DMD to the high frame frequency more than 200Hz frame frequencies, high gray level image at present
During Projection Display, its view data mostly be it is pre- first pass through translation cache, be not from host computer synchronous transfer
, the IR Scene of DMD projections is not the real-time display to host computer institute simulated scenario.
The content of the invention
In order to solve the above-mentioned problems in the prior art, the invention provides one kind can realize high frame per second, in real time
Transmit the DMD high frame frequency and high resolution synchronous dynamic display systems of display.
In order to realize foregoing invention purpose, the technical solution adopted by the present invention is：
A kind of DMD high frame frequency and high resolutions synchronous dynamic display system, including：Host computer, interface module, control module,
DMD；
The host computer connects the interface module, for sending the view data of specific frame frequency；
The interface module connects the control module, for receiving the view data of the specific frame frequency, and to described
View data is decoded；
The control module connects the DMD, for carrying out gray modulation to decoded view data
And format conversion processing, to meet the display frame frequency of the DMD and display format, and by the picture number after processing
According to being loaded into the DMD；
The DMD is used to show the view data after the processing.
Further, the control module includes control processor, DMD driver elements, memory cell；
The control processor is used to carry out gray modulation to the decoded view data, by the gray scale after modulation
Value image is converted to bit-plane image；
The DMD driver elements connect the control processor, for the bit-plane image to be loaded into the numeral
Micro mirror element；
The memory cell connects the control processor, for storing the decoded view data, the ash more
At least one of angle value view data, described bit-plane image data.
Further, the gray modulation algorithm is PWM algorithm.
Further, the memory cell includes at least two subspaces, and each subspace includes multiple bit planes
Space, wherein, the several bit wides according to pixel data in institute's bit planes space determine.
Further, in addition to display, the display connect the interface module；
The control module is additionally operable to carry out frame rate reduction processing to the decoded view data, by the frame rate reduction processing
View data display is sent to by the interface module；
The display is used for the view data for showing the frame rate reduction processing.
Further, the control processor is FPGA.
Further, the memory cell is DDR2 SDRAM high-speed memories.
Further, the interface module includes DVI interface and HDMI.
The embodiment of the present invention, compensate for it is domestic lack in HWIL simulation field can utilize DMD to high frame frequency, high ash
Spend the defects of level images carry out real-time display.Traditional PWM algorithm is optimized first so that DMD can be shown
The frame frequency of 8bit gray level images reaches more than 200Hz.Then the data buffer storage of the piecemeal storage based on DDR2 SDRAM is proposed
Mode, solve the problems, such as DMD in the high frame frequency Dynamic Graph of progress as the data buffer storage during form conversion and gray modulation.
DMD real-time display XGA resolution ratio, 8bit gray level images finally are realized, frame frequency is up to 200Hz design object.
Brief description of the drawings
Fig. 1 is the DMD high frame frequency and high resolution synchronous dynamic display system module frame charts of the present invention.
Fig. 2 is the module frame chart of the control module of the present invention.
Fig. 3 is the DMD high frame frequency and high resolution synchronous dynamic display system hardware in an embodiment of the invention
Structure chart.
Fig. 4 is the time chart in the continuous loading procedures of DMD in the embodiment of the present invention.
Fig. 5 is traditional PWM algorithm timing diagram in the embodiment of the present invention.
Fig. 6 is the operational flowchart of the clearing repositioning in the embodiment of the present invention.
Fig. 7 is the clearing repositioning timing diagram in the embodiment of the present invention.
Fig. 8 is the form transition diagram that " pixel bag " form is converted to " bit plane " form.
The memory space that Fig. 9 is the DDR2 SDRAM of the piecemeal storage of the present invention divides schematic diagram.
Figure 10 is the data flow schematic diagram of the piecemeal caching of the present invention.
Figure 11 is the parallel-serial conversion schematic diagram of the present invention.
Embodiment
With reference to embodiment, the present invention is described in further detail.But this should not be interpreted as this hair
The scope of bright above-mentioned theme is only limitted to following embodiment, all to belong to the present invention based on the technology that present invention is realized
Scope.
Embodiment one
The present embodiment is illustrated exemplified by display frame frequency 200Hz with gradation of image grade 8bit.
Fig. 1 is the DMD high frame frequency and high resolution synchronous dynamic display system module frame charts of the present invention, including：Host computer 1,
Interface module 2, control module 3, DMD 4；
The host computer 1 connects the interface module 2, for sending the view data of specific frame frequency；
The interface module 2 connects the control module 3, for receiving the view data of the specific frame frequency, and to institute
View data is stated to be decoded；
The control module 3 connects the DMD 4, for carrying out gray scale tune to decoded view data
System and format conversion processing, to meet the display frame frequency and display format of the DMD 4, and by the figure after processing
As data are loaded into the DMD 4；
The DMD 4 is used to show the view data after the processing.
Referring to Fig. 2, the control module 3 includes control processor 31, DMD driver elements 32, memory cell 33；
The control processor 31 is used to carry out gray modulation to the decoded view data, by the ash after modulation
Angle value image is converted to bit-plane image；
The DMD driver elements 32 connect the control processor 31, described for the bit-plane image to be loaded into
Digital micromirror device 4；
The memory cell 33 connects the control processor 31, for storing the decoded view data, described
At least one of more gray-value image data, described bit-plane image data.
The memory cell includes at least two subspaces, and each subspace includes multiple bit plane spaces, its
In, the several bit wides according to pixel data in institute's bit planes space determine.Wherein, pixel data is gradation of image to be stored
The bit wide of value.In the present embodiment by taking gradation of image grade 8bit as an example, therefore bit plane space number is 8.
The hardware composition of the present invention is introduced first.Hardware components of the present invention are divided by function, can be divided into data transfer and
System controls two modules.The content of data transfer mainly includes picture signal and synchronous control signal, data channel
It is present between host computer, DMD and display and control core FPGA, systems control division point mainly is responsible for realizing DMD gray scales
Modulation algorithm and control DMD are accurately shown.In the present embodiment, hardware system block diagram of the present invention is as shown in Figure 3.
The core control processor of control module is that (Field-Programmable Gate Array scenes can by FPGA
Program gate array)；Interface module has HDMI (the more matchmakers of High Definition Multimedia Interface fine definition
Body interface) and DVI (Digital Visual Interface digital visual interfaces) two kinds of data transmission interfaces of dual link,
For meeting different data transfer demands.
Specifically, interface module is mainly responsible for receiving the high frequency realtime graphic of host computer, and passed through all the way to display output
Cross the low-frequency image of drop frame.The realtime graphic frame frequency of the host computer transmission of the present invention is up to 200Hz, is shown with host computer NVIDIA
VESA (Video Electronics Standards Association VESAs) sequential of card output is carried out
Calculate, pixel clock 250MHz, it is single consider the steady of sequential even if manually self-defined sequential reduces pixel clock
Qualitative, pixel clock is also not less than 200MHz.Therefore interface must support the biography of the image more than 200MHz pixel clocks
It is defeated.At present in the video output interface of computer, most commonly DVI and HDMI, both of which are that high bandwidth pure digi-tal connects
Mouthful, and respectively have feature.In order to meet different application demands, the present invention devises DVI in the video inputs of interface module
With two kinds of interfaces of HDMI, for receiving host computer image.For the ease of debugging and the working condition of monitoring system, the present invention
HDMI output interface all the way is have also been devised, is connected to display.
The DMD high frame frequency and high resolution synchronous dynamic display systems of the present invention devise satisfaction height in the input of data
The high-speed video coffret module of bandwidth Image Real-time Transmission demand.Wherein DVI dual link interfaces and HDMI transmission
The pixel clock of RGB 8bit images reaches as high as 300MHz, supports transmission XGA image in different resolution frame frequencies up to more than 200Hz.
For the ease of debugging and monitoring system working condition, interface board also added HDMI output interface, be connected to display.
According to above-mentioned design, two-way HDMI is devised in interface module, all the way as input another way conduct
Output.That wherein HDMI input chip is selected is the ADV7619 of ADI companies, and the chip supports HDMI1.4 versions, image face
Color depth reaches as high as 36bit.Physically, ADV7619 supports two interface inputs, output image color depth simultaneously
In the case of 24bit, pixel clock reaches as high as 300MHz.Data transfer between ADV7619 and FPGA, if it is desired to make pixel
Clock reaches 300MHz, and its data transfer sequential is similar with DVI dual links, is equally separately transmitted using odd and even number pixel
Mode.Although this mode can cause the increase of data/address bus bit wide, more chips IO (Input/Output inputs/defeated are taken
Go out) pin, but the transmission rate of data can reduce, and help to lift the stability of data transfer.
Selection for HDMI pio chips, present invention employs the SiI9136-3 of Silicon Image companies, the core
Piece supports HDMI1.4 versions, and color of image depth highest supports 48bit, and the same highest of pixel clock supports 300MHz.In RGB
Form, in the case of 24bit color depths, the data format of this two chip is all R [23:16]、G[15:8]、B[7:0].Will
RGB channel is assigned into identical value, then gray level image just occurs on display.It is defeated in image by taking 8bit gray level images as an example
When entering any 8bit of 24bit passages can be selected to be used as valid data input bit, can be with when monitoring output
Give 8bit data to tri- passage assignment of RGB respectively, export to display.
, it is necessary to use display to monitor algorithm output result in debugging and the course of work.Due to currently marketed display
The highest frame frequency of device display image is less than 100Hz mostly, and the system picture frame frequency is 200Hz, so being exported in monitoring picture
When need to carry out drop frame to image.In order to simplify logic, the present invention has carried out the drop frame of integral multiple to image, by image
Frame frequency drops to 50Hz.
Exported by dropping the image of frame, or with VESA sequential standards, exported by FPGA to HDMI transmission chips
SiI9136-3, inside SiI9136-3, the TMDS by the data encoding that FPGA is sent into suitable interface high-speed transfer
(Transition-minimized differential signaling minimize differential signal transmission) form, delivers to display
Device.Before ADV7619 and SiI9136-3 work, it is also necessary to which FPGA passes through I2C (Inter-Integrated Circuit)
Bus (being made up of clock SCL and data/address bus SDA) configures to chip, is at current desired mode of operation.
Specifically, control module is the control core of whole system, mainly it is responsible for DMD gray modulations algorithm and video figure
As dropping the work such as the realization of frame algorithm and DMD display driving.The core control processor of control module is Xilinx companies
A Virtex-5LX series (XC5VLX50) FPGA, the DDR2 SDRAM (KTL-TP667/ of a plug-in Jin Shidun company
2G) high-speed memory.Control module is connected by plate to plate high-speed interface (QTE-060-01) with interface module, carries out data
Communication.
Image is delivered to DVI and HDMI by host computer by video card with TMDS forms, and view data is solved by DVI and HDMI
The FPGA of control core plate is delivered to after code chip decoding by QTE-060-01 interfaces.FPGA combines according to the data received
DDR2 SDRAM complete DMD gray modulations and drop the computing of frame algorithm, and drive DMD and HDMI coding chips respectively by algorithm
As a result output display.
DMD driving instruction is sent to the DMD controller DLPC410 in dmd chip group, is driven by DLPC410 combinations DMD
Dynamic device DAD2000 co- controllings DMD is shown.Pass through QTE-060-01 according to VESA standards by the view data for dropping frame
Interface be sent to HDMI the coding chips SII9136-3, SII9136-3 of interface board after being encoded to view data with
TMDS forms are delivered to display and shown.
For DMD gray scale display algorithms, gray scale is to represent an important indicator of image, and tonal gradation is higher, image layer
Secondary abundanter, picture is softer.For a width black white image, what tonal gradation embodied is pixel by between white to black
Luminance level.The strong and weak judgement of the visual system on luminance of people is determined by many factors, except the brightness of luminous object in itself
It is also relevant with the fluorescent lifetime and light-emitting area of luminous object outside power.For the illuminator of fast blink, human eye and spy
Certain " persistence of vision " effect can all be produced by surveying device., can be by changing illuminator using this " persistence of vision " effect
Lighting time, reach the purpose for producing different gray level images, so as to realize the gray modulation of image.It is right outside certain distance
In very small and weak illuminator, the area of illuminator is lighted by changing, the effect for changing vision gray scale can also be reached.DMD
Two kinds of working condition "ON" and "Off", represent just " 0 " and " 1 " of pixel value, project to obtain is a width binary map
Picture, its gray scale bit wide only have 1bit.Want to allow DMD to show more bit tonal gradations, it is necessary to carry out gray modulation to DMD.DMD
It is based primarily upon the time and the aspect of space two carries out gray modulation, so its gray modulation mode also can be largely classified into space ash
Degree modulation and the class of time gray modulation two.
Spatial gradation modulation advantage is that control is simple, and in single-frame images, micro mirror need not be overturn, and the frame frequency of image can be with
Reach very high.But it has the defects of inevitable again, " sub-pixel " number that pixel cell is divided into first is limited, causes
It can not show higher gray scale.Secondly, it expands pixel cell area to lift tonal gradation, causes the resolution ratio of image
Decline, on the premise of high-resolution is kept, existing specification DMD is difficult the too many tonal gradation of lifting.Therefore when the present invention uses
Between gray modulation.
Specifically, the present invention carries out gray scale using PWM (Pulse Width Modulation pulse width modulations) algorithm
Modulation.
In general, in the technical field of the present invention, resolution ratio is more than 1024 × 768, more than frame frequency 1bit 32000hz,
8bit real-time synchronizations can reach more than 200hz, and real-time synchronization not can reach more than 400hz and may be considered high frame frequency, high-resolution
Rate.The gradation of image requirement of the present invention is 8bit, and display frame frequency 200Hz, traditional PWM algorithm is extremely difficult to of the invention
Frame rate requirement, therefore the present invention provides a kind of PWM optimized algorithms.
The time that principal element by limiting DMD frame frequencies is DMD data loading and RESET is consumed.And select
DMD data transfer clocks be up to 400Mhz, DMD completes once complete data renewal, at least needs 30.72us, receives
" micro mirror commutator pulse ", which carries out reset, needs 5us, and 8us micro mirror stabilization time is also needed to after reset, and during reset and micro mirror is steady
New data can not be all loaded in fixing time.Fig. 4 show the time relationship in the continuous loading procedures of DMD.One as seen from the figure
The minimum time that frame is shown is 30.72us+8us=38.72us.
If showing the image of 8bit gray scales, it is necessary to which original image is divided into 8 " bit planes " using traditional PWM algorithm,
The loading of 8 data and RESET are carried out to DMD, in order to ensure continuity that image shows, it is necessary to current bit plane display
The data loading work of next bit plane is completed in time.So the display time t of " basic bit plane " should meet t >=
38.72us.In order to calculate the limit frame frequency of 8bit images, it is assumed here that t=38.72us.
DMD carries out the loading of the data of bit plane 0 first, and " micro mirror commutator pulse " is sent to DMD after data loaded,
Reset micro mirror and enter " micro mirror stabilization time ", start the loading of the data of bit plane 1, DMD during this after waiting micro mirror stable
It is shown that the data of bit plane 0.After the loading of the data of bit plane 1 is completed, the display time of bit plane 0 just terminates, at once
Sending " micro mirror commutator pulse " to DMD resets micro mirror, resets the display time for entering bit plane 1 after terminating, this time
According to PWM algorithm principle, it may be that 2t ((30.72us × 2) us), this time completes the loading of the data of bit plane 2 enough.
After the display time of bit plane 1 terminates, the data loading of bit plane 2 is completed already, sends " micro mirror commutator pulse " to DMD at once
Reset micro mirror, into the display time of bit plane 2.Completed by that analogy within the upper bit plane display time next
The data loading work of bit plane, so just can guarantee that the continuity that image is shown.Traditional PWM algorithm sequential relationship is specific such as
Shown in Fig. 5.
After the completion of waiting the display of bit plane 7, the PWM of a width 8bit gray level images just terminates.Whole process, disappear
Time-consuming tp1Time t is shown equal to all bit planesdWith resetting time trSum.Its computational methods is：
tp1=tr+td
=(5 × 8+255 × 38.72) us
=9913.6us
Frame frequency, which can be obtained, is：
fp1=1/tp1=100.9Hz
It can show that traditional PWM algorithm, the display limit of 8bit gray level image frame frequencies is 100.9Hz by analysis,
It is difficult to the design requirement for meeting the present invention.So it must be optimized on the basis of PWM algorithm.
The present invention is optimized using repositioning is reset to PWM algorithm.
Under the pattern of Global reset, the display time of basic bit plane is set as t=18us, utilizes " block clearing " behaviour
The whole DMD that opposes, which is reset, to be needed to consume 0.64us.Wait 8us micro mirror stabilization time is needed after resetting every time, during this period
DMD can not carry out data renewal.Only when the display time of bit plane being more than 38.72us, it could meet in current bit plane
The loading work of next bit-plane data is completed during display.Otherwise, at the end of bit plane shows the time, by micro mirror number
According to resetting, resetting, it is closed micro mirror, image, which is shown, is in blanking zone.Since bit plane 2, bit plane is shown
Time can all be more than 38.72us, so need to only carry out " block clearing " operation when the first two bit plane is shown.Reset multiple
The operating process of position method is as shown in Figure 6.
Fig. 7 show the sequential relationship for resetting repositioning.The data of bit plane 0 are loaded to DMD first, it is then aobvious at it
When having shown 17.36us, operate, clear operation completion after 0.64us, then sent to DMD to all pieces of transmissions " block clearing " of DMD
" micro mirror commutator pulse " makes its reset, and the now display of DMD bit planes 0 terminates, and DMD is in BLANK states, and display is completely black.It is micro-
Mirror resets the micro mirror stabilization time of wait 8us after reset, and the data of bit plane 1 are so loaded to DMD, equally time-consuming 30.72us,
DMD is resetted after data loaded, after DMD will show that bit plane 1, bit plane 1 show 35.36us, equally to DMD
All pieces carry out " block clearing " operation.The data of bit plane 2 are loaded in DMD second BLANK section, bit plane 2 shows
It is 72us to show the time, and the display time is more than 38.72us, so during bit plane below is shown, it is not necessary to carries out that " block is clear again
Zero " operation.
Reset under repositioning, the minimum time t that display 8bit images are consumedp3Calculating formula is：
tp3=tr+td
=(5 × 8+255 × 18+43.72 × 2) us
=4717.44us
Frame frequency is：
fp3=1/tp3=211.9Hz
By can be calculated, after clearing method is resetted, DMD shows that the frame frequency of 8bit images has reached 211.9Hz, full
Sufficient design requirement.Clearing method is resetted, although can occur of short duration BLANK sections during the data of low two are shown,
The BLANK times are very short, occupy effect shows the time 3.5%, can be with so the influence to gradation of image precision is not very big
Ignore.Therefore invention is used as DMD 8bit gray modulation algorithms using reset clearing method.In order to match host computer
The display time of basic bit plane is set to 19.11us by 200Hz picture frame frequency, the present invention during realization.Image
Show time tp4Calculation formula is：
tp4=tr+td
=(5 × 8+255 × 19.11+43.72 × 2) us
=5000.49us
Limit frame frequency is：
fp4=1/tp4=200.0Hz
Existing PWM algorithm basic bit HUD shows overlong time, limits the frame frequency that DMD shows high gray level image, this hair
The bright clearing using DMD resets operation, and traditional PWM algorithm is optimized, the basic bit plane time is reduced to
19.11us so that picture frame frequency reaches more than 200Hz, meets the design requirement of system.
Because the displaying principle of the DMD based on PWM algorithm requires that data loading is in the form of bit plane, by a frame figure
Shown successively as being divided into several bit planes, the number of bit plane determines the tonal gradation of image.Due to inputting and output figure
The data format of picture is different, and this just needs the image of the host computer to receiving before DMD is shown to enter row format conversion,
The picture signal of " pixel bag " form based on VESA standards is converted to the image suitable for DMD " bit plane " forms shown
Signal.
Fig. 8 show the schematic diagram of form conversion.Left side is that a grey scale pixel value bit wide is 8bit, it then follows during VESA
The image of " pixel bag " form of sequence, 8 bit planes are converted to by form.Bit plane 0 is equivalent to be owned by original image
The lowest order of pixel combines formed a width bianry image, and other bit planes are substantially also corresponding with original image
" position " bianry image for being formed.
Enter row format conversion to image to be equivalent to once recombinate view data, then in data recombination
During be exactly inevitably to need to cache data.Certain Block RAM be present inside FPGA, there is operation
The features such as convenient, controllability is strong, and logic is simple, and read-write is stable, it is especially suitable for doing the caching of high-speed data.But Block RAM
It is FPGA embedded resource after all, limited storage space.As it was previously stated, the system of the present invention also has one piece outside FPGA
DDR2 SDRAM, its capacity is enough, and also quickly, but be constrained to FPGA stone resources, a carry is a piece of for read-write speed
DDR2 SDRAM, and read-write operation is relative complex, along with the particularity of PWM algorithm, is implemented using external memory storage
Also there is certain difficulty.
The image data amount that the system requirement is handled in real time is XGA@200Hz, image intensity value bit wide 8bit.For connecing
The host computer view data being subject to, first have to do is exactly to be stored.In the realization of the storage mode of data, one
Kind for the treatment of method is global storage, is directly stored to together, it is necessary to when output, each data of reading of step-by-step, so
8 corresponding bit planes can be obtained by reading 8 times repeatedly to whole memory space.Another method is piecemeal storage, right first
It is split, and is then stored separately.Each bit plane is stored to a single memory space.
During using global storage, because the bit wide of DDR2 SDRAM data/address bus is 64bit, and the bit wide of pixel data
For 8bit, if memory is only stored in 8bit data every time, data/address bus in work can be caused idle bandwidth waste to be present.
In order to make full use of the transmission bandwidth of memory, before data storage, the present invention has carried out serioparallel exchange to pixel data,
Namely data merge.It is a 64bit data by continuous 8 potting gums, every 8 pixels carry out write-once, so
One two field picture one shares 98304 data., it is necessary to which what is obtained is bit plane form when DMD carries out data loading
Data, and DDR2 SDRAM read operation is directed to address, a DQ [63 can all be obtained by often reading an address date:
0].DQ[63:0] 64bit data are had altogether, but system is not to be all required for, so data selection must be carried out.Such as
When carrying out bit plane 0 and load, the DQ [63 that reads:0] there was only DQ [0], DQ [8], DQ [16], DQ [24], DQ [32], DQ in
[40], DQ [48], DQ [56] belong to preceding 8 pixels of bit plane 0, and remaining is all the data of other 7 bit planes.For
There is also same case for other bit plane loadings., it is necessary to be deposited to whole two field picture within a complete PWM algorithm time
Store up space to read 8 times, respectively obtain 8 bit planes.
Due to 56bit invalid data in the data that in memory read process, obtain every time be present, this is resulted in
The significant wastage of data transfer bandwidth, the effective rate of utilization of actually data transfer bandwidth only have 12.5%.Operated in this
Under mode, to meet DMD loading demands, it is necessary to DDR2 SDRAM transmission rate is 98304 ÷ 30.72us=3.2GHz,
This is beyond the DDR2 SDRAM transmission rate upper limit, even if the DDR4 SDRAM of highest ranking data transfer at present
Speed also is difficult to meet demand.So although global storage logic is simple, to DDR2 SDRAM when digital independent
Transmission bandwidth utilization rate is too low.
In order to solve the problems, such as that such scheme data transfer bandwidth utilization rate is too low, the invention also provides deblocking
The mode of storage., it is necessary to be split before data storage to data step-by-step by the way of piecemeal storage, and in DDR2
The data after fractionation are separately deposited inside SDRAM.For the purposes of making full use of DDR2 SDRAM readwrite bandwidth, in data
Before write-in, for the data after fractionation, need also exist for carrying out serioparallel exchange, continuous 64 1bit data are merged into one
Individual 64bit data carry out depositing read operation.It is of the invention by the way of Pingpang Memory in order to ensure the continuity of data processing,
Whole memory is divided into two sub-spaces, data read the previous frame number of subspace 2 during being write to subspace 1
According to during data write to subspace 2 in turn, the previous frame data of reading subspace 1, two sub-spaces are alternately read
Write the continuity for ensureing data processing.It is being divided into 8 bit plane spaces again inside per sub-spaces.One bit plane includes
1024 × 768 × 1bit data, a memory cell in bit plane space can deposit 64bit data, so a position is put down
Space of planes comprises at least 12288 memory cell.The memory space that Fig. 9 show DDR2 SDRAM under piecemeal storage condition is drawn
Point.
During the peak of DDR2 SDRAM data transfers is equally the loading of DMD data, using the side of piecemeal storage
Formula, due to initial data has been carried out into segmentation restructuring so that read DDR2 SDRAM every time when DMD data load and obtain
To be valid data entirely, it is only necessary to read 12288 addresses and can be obtained by a complete bit plane.During this
DDR2 SDRAM message transmission rate is 12288 ÷ 30.72us=400MHz.This speed is less than DDR2 SDRAM data
The upper limit is transmitted, logic is complicated still can greatly to reduce DDR2 SDRAM so although the mode of piecemeal storage implements
The bandwidth pressure of data transfer, thus the mode for the data buffer storage being used as present invention employs piecemeal storage in PWM algorithm.
Its data flow block diagram is as shown in Figure 10.
Each of the 8bit data transmitted first to the host computer received carries out serioparallel exchange respectively, this process
It can be realized with RAM.Because RAM conversion ratio at most can be to 1:32, so present invention uses two-stage FIFO cascades
Mode, every grade of RAM conversion ratio respectively 1:16 and 1:4, changing for two-stage cascade is compared into 1:64.By the number of serioparallel exchange
According to that should be sent into DDR2 SDRAM, ping-pong operation selecting unit first can be selected subspace, select the subspace of free time
Data are deposited into, 8 in selected subspace bit plane space can be accessed one by one, is divided 8 times and first time will be gone here and there and turn
The 8 64bit data got in return are sequentially stored into corresponding bit plane space.While current frame data is stored in DDR2 SDRAM,
For another sub-spaces also in the output for coordinating DMD loadings to carry out bit plane, output end equally also has a ping-pong operation selection single
Member, the subspace that it can select to be updated over data and stopped inputting are exported, each one bit plane space of output
Data give DMD, and within 8 bit plane load times of a two field picture, from bit plane space 0, plane space 7 is successively in place
Run through.
In DDR2 SDRAM use, present invention employs the MIG3.61 DDR2 controllers built in FPGA, use
DDR2 core controllers can make system save preliminary filling during SDRAM reads and writes during control DDR2 SDRAM work
The complicated logical operations such as electricity, refreshing, it is only necessary to be written and read according to the read-write sequence of user interface.
When carrying out data input output, DMD loading speeds reach as high as 800MHz, and DMD loads one under the speed
Bit plane takes 30.72us.This time is the limit of DMD data renewal, if DMD loading speeds do not reach 800MHz, that
The DMD data load time will extend, that is, add DMD and load the consumed time, and this will reduce DMD's
Display frame frequency.Simultaneously from PWM algorithm, the DMD load times, which extend, also can increase the blanking time in clearing reseting procedure,
So as to influence the precision that the high gray scales of DMD are shown.
The present invention reduces the mode of the FPGA speed of service using multiple processing modules are replicated, and makes total data processing
Speed will not reduce.The present invention has done parallel-serial conversion, conversion proportion 4 before the output of view data and control signal:1.
The LVDS buses of two-way bit wide 16bit in DMD data load process, corresponding to during carrying out computing inside FPGA
It is two bit wide 64bit data-signal DATA_B [63:0] and DATA_B [63:0].After parallel-serial conversion, inside FPGA
200MHz speed of service can is only needed to meet data 800MHz data output.Referring specifically to shown in Figure 11 and go here and there
The schematic diagram of conversion.
Finally it should be noted that：The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；To the greatest extent
The present invention is described in detail with reference to the foregoing embodiments for pipe, it will be understood by those within the art that：It is still
Technical scheme described in foregoing embodiments can be modified, or which part technical characteristic is equally replaced
Change；And these modifications or replacement, the essence of appropriate technical solution is departed from the essence of various embodiments of the present invention technical scheme
God and scope.
Claims (8)
- A kind of 1. DMD high frame frequency and high resolutions synchronous dynamic display system, it is characterised in that including：Host computer, interface module, Control module, DMD；The host computer connects the interface module, for sending the view data of specific frame frequency；The interface module connects the control module, for receiving the view data of the specific frame frequency, and to described image Data are decoded；The control module connects the DMD, for carrying out gray modulation and form to decoded view data Conversion process, to meet the display frame frequency of the DMD and display format, and the view data after processing is loaded To the DMD；The DMD is used to show the view data after the processing.
- 2. DMD high frame frequency and high resolutions synchronous dynamic display system according to claim 1, it is characterised in that the control Molding block includes control processor, DMD driver elements, memory cell；The control processor is used to carry out gray modulation to the decoded view data, by the gray-value image after modulation Be converted to bit-plane image；The DMD driver elements connect the control processor, for the bit-plane image to be loaded into the digital micro-mirror Device；The memory cell connects the control processor, for storing the decoded view data, more gray values At least one of view data, described bit-plane image data.
- 3. DMD high frame frequency and high resolutions synchronous dynamic display system according to claim 2, it is characterised in that the ash Degree modulation algorithm is PWM algorithm.
- 4. DMD high frame frequency and high resolutions synchronous dynamic display system according to claim 2, it is characterised in that described to deposit Storage unit includes at least two subspaces, and each subspace includes multiple bit plane spaces, wherein, institute's bit planes space Several bit wides according to pixel data determine.
- 5. DMD high frame frequency and high resolutions synchronous dynamic display system according to claim 2, it is characterised in thatAlso include display, the display connects the interface module；The control module is additionally operable to carry out frame rate reduction processing to the decoded view data, by the image of the frame rate reduction processing Data are sent to display by the interface module；The display is used for the view data for showing the frame rate reduction processing.
- 6. DMD high frame frequency and high resolutions synchronous dynamic display system according to claim 2, it is characterised in that the control Processor processed is FPGA.
- 7. DMD high frame frequency and high resolutions synchronous dynamic display system according to claim 2, it is characterised in that described to deposit Storage unit is DDR2SDRAM high-speed memories.
- 8. DMD high frame frequency and high resolutions synchronous dynamic display system according to claim 2, it is characterised in that described to connect Mouth mold block includes DVI interface and HDMI.
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| CN117714655A (en) * | 2024-02-06 | 2024-03-15 | 长春理工大学 | Ultra-high frame rate projection method and device based on quaternary pulse width modulation |
| CN117714655B (en) * | 2024-02-06 | 2024-04-09 | 长春理工大学 | Ultra-high frame rate projection method and device based on quaternary pulse width modulation |
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