CN106710515B - Programmable logic device, sending card and LED display control system - Google Patents
Programmable logic device, sending card and LED display control system Download PDFInfo
- Publication number
- CN106710515B CN106710515B CN201510442741.XA CN201510442741A CN106710515B CN 106710515 B CN106710515 B CN 106710515B CN 201510442741 A CN201510442741 A CN 201510442741A CN 106710515 B CN106710515 B CN 106710515B
- Authority
- CN
- China
- Prior art keywords
- module
- data
- dual port
- ram
- sub
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The present invention relates to a kind of programmable logic device, a kind of sending card and a kind of LED display control systems.The programmable logic device includes: sub-pix coding module, for carrying out sub-pix addressing and down-sampling to the image data of input to obtain down-sampled images data；Buffer module is inputted, for caching the down-sampled images data；RAM control module, for controlling the external RAM that the down-sampled images data are written to the programmable logic device；And data packing block, for carrying out packing output to the down-sampled images data obtained from the external RAM by the RAM control module.Therefore, the present invention, which can be realized, shows high-resolution, high resolution pictures on the LED display of limited cost or lower physical resolution.
Description
Technical field
The present invention relates to image procossing and field of display technology, in particular to a kind of programmable logic device, a kind of transmission
Card and a kind of LED display control system.
Background technique
Modern flat-panel display mostly uses greatly space law to synthesize color, and each pixel on display includes that can generate three
The sub-pix of primary colours.When sub-pix spacing is sufficiently small, color blending phenomenon will occur and show various different colours.
The sub-pix of LED display corresponds to the light emitting diode of different base colors (red, green, blue), under the control of driving signal, three bases
Color shows a variety of different colors by color mixture and constitutes a LED pixel.The process of image is shown in LED display
In, the pixel data of video source one-to-one can be completely mapped on LED display.
The advantages that Full color LED display screen is high, imaging area is big with its light emission luminance, it is big almost to occupy entire indoor and outdoor
Type display field.However by various limitations such as technical level, manufacturing process and cost so that pel spacing is big, resolution ratio is low
As the major obstacle for restricting its development, LED display is also caused to be difficult to reach the high-resolution of similar LCD, PDP flat-panel monitor
Rate and clarity.
To realize that high-resolution LED is shown, there is proposition to reduce LED lattice distance, increase LED dot matrix scale in the prior art
Etc. schemes, but the cost that those schemes will lead to LED display is significantly increased, system stability be deteriorated, LED display correction
The deficiencies of link difficulty and complexity are promoted, failure rate increases；In addition, the prior art, which also has, proposes LED sub-pix multiplexing technology,
By taking the traditional RBGR mosaic arrangement of LED display (or diagonal form arrangement) as an example, due to four sub-pixes of arbitrary neighborhood
A pixel can be formed, therefore this additional pixels between physical picture element are called virtual pixel；Physical picture element is differentiated
Rate is the LED display of M × N, the resolution ratio of LED display can be made in horizontal and vertical side by sub-pix multiplexing technology
It is each upwards to promote about 2 times, namely it is expanded to (2M-1) × (2N-1).Although sub-pix multiplexing technology increases the addressable of system
Property, the scale for improving displayable image, but shadow of the color value of each sub-pix of flash trimming out-of-bounds by 4 pixels
It rings, causes image to generate blurring effect, so that image definition cannot be effectively improved.
Therefore, how on the display screen of limited cost or lower physical resolution high-resolution, high-resolution to be shown
Rate picture is one of the Main way of display field research.
Summary of the invention
To overcome shortcomings and deficiencies in the prior art, the present invention proposes a kind of programmable logic device, a kind of sending card
And a kind of LED display control system.
Specifically, a kind of programmable logic device that the embodiment of the present invention proposes, comprising: sub-pix coding module, input
Buffer module, RAM control module and data packing block.Wherein, sub-pix coding module is used for the image data to input
Sub-pix addressing and down-sampling are carried out to obtain down-sampled images data；Input buffer module is for caching the down-sampled images
Data；RAM control module is for controlling the external RAM that the down-sampled images data are written to the programmable logic device；
And data packing block is used for the down-sampled images obtained from the external RAM by the RAM control module
Data carry out packing output.
In one embodiment of the invention, above-mentioned sub-pix coding module includes the first dual port RAM, the second dual port RAM
With third dual port RAM；In the adjacent rows pixel data stored respectively to first dual port RAM and second dual port RAM
During carrying out the sub-pix addressing and down-sampling, the third double-interface RAM buffer next line pixel data.
In one embodiment of the invention, above-mentioned input buffer module include the 4th dual port RAM, for cache it is described under
Sampling image data.
In one embodiment of the invention, above-mentioned programmable logic device further includes anti-color error handling module, is used
It compiles in carrying out convolution algorithm according to default size template and be input to the sub-pix to obtain anti-color error handle image data
Code module.
In one embodiment of the invention, above-mentioned color error handling module includes the 5th dual port RAM, the 6th twoport
RAM, the 7th dual port RAM, the 8th dual port RAM, and it is connected to each dual port RAM in the 5th to the 8th dual port RAM
Multiple registers of outlet side.
In addition, a kind of sending card that the embodiment of the present invention proposes, including video receiver, programmable logic device, storage
Module and data outputting module, the programmable logic device are connected electrically in the video receiver and data output mould
Between block, the memory module is electrically connected the programmable logic device.The sending card further includes MCU control module, is electrically connected
Connect the programmable logic device；And the programmable logic device include: sub-pix coding module, input buffer module,
RAM control module and data packing block.Interim, sub-pix coding module is used under the control of the MCU control module
Sub-pix addressing and down-sampling are carried out to obtain down-sampled images data to the image data of input；Input buffer module is for delaying
Deposit the down-sampled images data；For controlling the memory module is written in the down-sampled images data by RAM control module；
And data packing block is used for the down-sampled images obtained from the memory module by the RAM control module
Data be packaged output to the data outputting module.
In one embodiment of the invention, the sub-pix coding module in the programmable logic device in above-mentioned sending card
Including the first dual port RAM, the second dual port RAM and third dual port RAM；To first dual port RAM and second dual port RAM
During the adjacent rows pixel data stored respectively carries out the sub-pix addressing and down-sampling, the third dual port RAM
Cache next line pixel data；The input buffer module includes third dual port RAM, for caching the down-sampled images number
According to.
In one embodiment of the invention, the programmable logic device in above-mentioned sending card further includes at anti-color mistake
Manage module, for carrying out convolution algorithm according to default size template with obtain anti-color error handle image data be input to it is described
Sub-pix coding module.
In one embodiment of the invention, at the color mistake in the programmable logic device in above-mentioned sending card
Managing module includes the 5th dual port RAM, the 6th dual port RAM, the 7th dual port RAM, the 8th dual port RAM, and is connected to the described 5th
Multiple registers of the outlet side of each dual port RAM into the 8th dual port RAM.
In addition, a kind of LED display control system that the embodiment of the present invention proposes, carries out figure suitable for driving LED display
As display, the LED display control system includes receiving card and any one aforementioned sending card, and the sending card is suitable for being electrically connected
Video source is connect to obtain desire display image data, the reception card is suitable for being connected electrically in the sending card and the LED display
Between.
Therefore, the above embodiment of the present invention can be reached following one or more the utility model has the advantages that (1) to can be improved plate aobvious
The system senses resolution ratio for showing device, can be applied on a variety of flat-panel monitors, realize higher resolution on same display
The clear display of picture reduces display effect to the rigors of hardware system physical picture element resolution ratio；(2) it is able to ascend
LED display display capabilities, realized under conditions of not changing original LED display control system sub-pix addressing and under adopt
Sample technology is simultaneously preferably added anti-color error handle, reduces due to directly carrying out sub-pix addressing and down-sampling bring face
Color Problem-Error is effectively guaranteed the clarity of picture while providing display resolution；(3) it can be shown according to LED
The arrangement feature of LED light point selects suitable sub-pix addressing and down-sampling mode to be encoded on screen, while may be implemented not
With the resume module algorithm of size, the video source image data being more suitable for is exported to LED display control system, so as to mention
Height while also improving display effect to the compatibility of different lamp points arrangement LED display.
Through the following detailed description with reference to the accompanying drawings, other aspects of the invention and feature become obvious.But it should know
Road, which is only the purpose design explained, not as the restriction of the scope of the present invention, this is because it should refer to
Appended claims.It should also be noted that unless otherwise noted, it is not necessary to which scale attached drawing, they only try hard to concept
Ground illustrates structure and process described herein.
Detailed description of the invention
Below in conjunction with attached drawing, specific embodiments of the present invention will be described in detail.
Figure 1A is the pixel arrangement schematic diagram of the evenly dispersed formula LED display of 3 sub-pixes.
Figure 1B is the pixel arrangement schematic diagram of the evenly dispersed formula LED display of 4 sub-pixes.
Fig. 2A is the sub-pix addressing and down-sampling schematic illustration corresponding to pixel arrangement mode shown in Figure 1A.
Fig. 2 B is the sub-pix addressing and down-sampling schematic illustration corresponding to pixel arrangement mode shown in Figure 1B.
Fig. 3 is that the internal data of the programmable logic device of the embodiment of the present invention handles main functional modules figure.
Fig. 4 is the realization block diagram of sub-pix coding module shown in Fig. 3 and input buffer module.
Fig. 5 is the built-in function frame that the programmable logic device of anti-color error handling module is added on the basis of Fig. 3
Figure.
Fig. 6 is the realization block diagram of anti-color error handling module shown in Fig. 5.
Fig. 7 is that the row traversal of anti-color error handle realizes explanatory diagram.
Fig. 8 is that explanatory diagram is realized in 3 × 3 template operations.
The addressing of 4 sub-pixes and 4 sub-pix data weights in each pixel data after down-sampling that Fig. 9 is the embodiment of the present invention
Group output process schematic.
Figure 10 is the structural schematic diagram of the sending card of the embodiment of the present invention.
Figure 11 shows a kind of LED display control system of the embodiment of the present invention.
Specific embodiment
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
During sub-pix addressing and down-sampling technical application are handled image data to sending card by the embodiment of the present invention,
And corresponding pretreatment operation, these above-mentioned behaviour are carried out preferably for sub-pix down-sampling bring color Problem-Error
Make have no need to change the hardware configuration of original sending card, it is achieved that process is more efficient and convenient, and it can be
The clear display of high-definition picture is completed in the case where not changing original hardware system.
Hold above-mentioned, the embodiment of the present invention can be applied to the evenly dispersed formula LED display of 3 sub-pixes, 4 sub-pixes, pixel row
Mode for cloth difference is as shown in FIG. 1A and 1B.Both arrangement modes in Figure 1A and Figure 1B are typically arranged in LED display
The advantages of mode for cloth, these kinds of arrangements is that light-emitting area is big, can be set by flexibly addressing to have display with restructing algorithm
It is standby that there is bigger room for promotion in perceived resolution.In addition, it is noted that 4 sub-pixes are not limited to institute in Figure 1B
The 1R1B2G shown is also possible to 2R1B1G etc. arrangement mode.
For both sub-pix arrangement modes of LED display in Figure 1A and Figure 1B, the embodiment of the present invention is correspondingly to defeated
Enter high-resolution both full-pixel image data and carries out sub-pix addressing and down-sampling as shown in Figure 2 A and 2 B respectively.Fig. 2A and figure
Dotted line upper area is input high-resolution both full-pixel image data in 2B, is by sub-pix addressing and down-sampling below dotted line
Output image data afterwards；Two ways can largely reduce display data volume, while not influence display resolution, this
Requirement of the full resolution pricture to display equipment physical resolution can largely be reduced.Herein it is noted that sub- picture
It is the constraint for casting aside original physical picture element in element addressing and down-sampling technical spirit, it is basic using sub-pix as showing, addressing
Unit improves the sample rate of display system equivalent to increase reticular density under conditions of not changing original display equipment.
Fig. 3 is the internal data processing major function of such as fpga chip of programmable logic device 31 in the embodiment of the present invention
Module map.Entire flow chart of data processing fully considers these high speed designs such as " serioparallel exchanges ", " ping-pong operation " and " assembly line "
Thought improves treatment effeciency, realizes the real-time processing of system.The function of sub-pix coding module 312 mainly receives input
High resolution image data realized 4 shown in 3 sub-pixes or Fig. 2 B shown in Fig. 2A under the control of MCU control module 33
Then input buffer module 314 is written in down-sampled images data by sub-pix addressing and down-sampling；Input buffer module 314
Function is mainly the pixel data coordinating the time sequence difference of sub-pix coding module 312 and RAM controller 316 and encoding
(namely down-sampled images data) are orderly written in memory module 35 under the control of RAM control module 316.Sub-pix encodes mould
There may be differences for block 312 and the clock of RAM control module 316, and the two clock ability in sub-pix coding module 312
A sub-pix data are obtained, so being provided with input buffer module 314 in order to coordinate the timing differential of former and later two modules.
The function of RAM control module 316 is mainly to receive the down-sampled images data that input buffer module 314 caches to carry out real-time storage
Certain image procossing and logic control are carried out, into memory module 35 and to image data after sub-pix down-sampling to realize figure
Packing and bus arbitration as data.Memory module 35 be equipped with SDRAM1 in two panels SDRAM storage chip namely Fig. 3 and
SDRAM2.It is a piece of for storing by sub-pix addressing and the resulting image data of down-sampling in a frame image temporal, it is another
Piece send stored good down-sampled images data to data packing block 318 according to certain net through RAM control module 316
Network agreement carries out packing output.
Fig. 4 is the realization block diagram of sub-pix coding module 312 and input buffer module 314.Sub-pix coding module 312
Function is mainly that the high resolution image data of input is carried out sub-pix addressing and down-sampling, then by sub-pix after down-sampling
Data give input buffer module 314.In the present embodiment, sub-pix coding module 312 is 32bits by three bit wides, and capacity is
1024 dual port RAM namely RAM1~RAM3 shown in Fig. 4 are constituted, and three RAM cooperatings realize the high-resolution to input
The sub-pix of image data encodes.Synchronization, two RAM in three RAM carry out sub- according to method shown in Fig. 2A or Fig. 2 B
Code pixel data, another RAM buffer next line pixel data；Output data is given input buffer module 314 and is cached.
The function of input buffer module 314 is mainly to coordinate the timing differential of former and later two modules, according to analysis it is found that input buffering mould
It is 32bits that a bit wide is arranged in block 314, and the dual port RAM namely RAM4 shown in Fig. 4 that capacity is 1024 can satisfy system
It is required that.
Fig. 5 is the inside of such as fpga chip of programmable logic device 31 after anti-color error handle is added in sending card
Functional block diagram.Fig. 5 increases anti-color error handling module 310 compared to Fig. 3, other Module implementations are same as above,
It repeats no more below.The function of anti-color error handling module 310 is mainly the anti-face realized to the high-definition picture of input
Color error handle, the processing are substantially a mask convolution process, and the selection of template size is needed from precision is realized, institute is time-consuming
Between, the various aspects such as complexity comprehensively consider.The module for the use of size being 3 × 3 in the present embodiment.
The pixel data of each location of pixels will be modified repeatedly in anti-color error processing procedure, so this hair
It is selected in bright embodiment and carries out data processing convenient for addressing data and the dual port RAM of rewriting.When peak demand processing resolution ratio is
1920 × 1080 image, four dual port RAMs namely RAM5~RAM8 in Fig. 6 access one-row pixels data respectively, so
The bit wide of dual port RAM is set as 32bits, and depth is set as 2048.12 registers namely it is as shown in FIG. 6 be located at each RAM
1~register of register 12 of outlet side stores the pixel data of 12 positions in four row pixels respectively.Wherein three twoports
Nine pixel datas in subsequent nine registers of RAM cooperate the quick processing template of realization 3 × 3, another RAM is slow
One-row pixels data are left, the data of 3 × 3 templates can be obtained in each clock, as shown in the dot-dash wire frame in Fig. 6,
The pile line operation to data is realized, the time has been saved, improves data-handling efficiency.
Fig. 7 is that the row traversal of anti-color error handle realizes explanatory diagram.In Fig. 7, (n, m) is a pixel in a width figure
Coordinate position as in shows it in line n, m column.It is n-th, the n+ stored in RAM5, RAM6, RAM7 first in Fig. 7
1, n+2 row raw pixel data participates in 3 × 3 template operations, starts caching the n-th+3 row original image prime number in RAM8 at the same time
According to.In n-th, n+1, the n-th+3 row raw pixel data has been stored in after the pixel data of n+2 row finishes template operation, in RAM8.
Start again at this time to (n+1)th, the n+2 stored in RAM6, RAM7, RAM8, n+3 row pixel data carries out template operation, while handle
Line n pixel data in RAM5 after template operation gives sub-pix coding module 312, and the n-th+4 untreated original of row
Beginning pixel data is written in RAM5.Synchronization is left there are three template operation is carried out in four RAM namely RAM5~RAM8
One give processed pixel data to sub-pix coding module 312 and the RAM be written into next line raw pixel data.
And so on, it moves in circles, is completed until all pixels row of full frame image is traversed.
Fig. 8 is that explanatory diagram is realized in 3 × 3 template operations.When doing template operation, it is assumed that 3 × 3 templates exist in first clock
Fig. 8 dotted line frame position, register Isosorbide-5-Nitrae at this time, what is stored in 7 is pixel (n, m), (n+1, m), the data of (n+2, m).?
It needs for the first row pixel data in 3 × 3 templates to be stored in corresponding RAM after finishing convolution algorithm, i.e., will post respectively
The data of pixel (n, m) in storage 1,4,7, (n+1, m), (n+2, m) are stored in RAM5, RAM6, RAM7.When by one
Clock, 3 × 3 template movements solid box position into such as Fig. 8, register Isosorbide-5-Nitrae at this time, that store in 7 is pixel (n, m+1),
(n+1, m+1), the data of (n+2, m+1).Equally by the pixel (n, m+1) in register 1,4,7, (n+1, m+ after template operation
1), in data deposit RAM5, RAM6, the RAM7 of (n+2, m+1).Using a clock, 3 × 3 templates continue to translate a position
It sets, and so on, up to 3 × 3 template movements are to the end of one-row pixels, to realize at the template of each pixel data of full line
Reason.Like this, it is convolution algorithm, convolution algorithm process that 3 × 3 templates, which orderly shift in the picture and do the process of corresponding operation,
In the algorithm used can be found in Xi'an Novastar Electronic Technology Co., Ltd. filed on February 12nd, 2015 application No. is
The application for a patent for invention of CN201510075267.1, entitled " image processing method and image processing apparatus ", are taken off
The content quotation of dew is used as reference in this, and dotted line frame corresponds to 3 × 3 block of pixels in the application for a patent for invention in Fig. 8.It needs
Illustrate, the time needed for convolution algorithm is related with the complexity of algorithm.Before and after doing template operation, pixel value is that have can
Can variation, has carried out the processing of template so every and the first row pixel data (final result) in 3 × 3 templates will have been weighed
In new deposit RAM.Other two column pixel data is not most to terminate due to continue to participate in following template operation, value in template
Fruit, so temporarily not needing to store.
In addition, it is noted that most of video decoding circuit in sending card export be 24 true color (R, G,
Each 8 of B) image data, and every 4 sub-pixes, 32 data obtained in the addressing of 4 sub-pixes shown in Fig. 2 B and down-sampling
One new pixel of composition, the transmission of a new pixel is unable to complete by a clock.Although actual data transfer mode
Can there are many, it is recommended here that use mode shown in Fig. 9, dotted line with the arrow reflects sub- when data actual transmissions in Fig. 9
4 reconfigured in process namely down-sampled images data in each pixel data of the same pixel column of pixel data
Sub-pix data are split to two to transmit in pixel data (the 3 sub-pix data combination in Fig. 9) and be exported.Correspondingly,
Comparison diagram 9 and Fig. 2 B pixel number can be carried out again after pixel data is received in the reception clamping of the LED display of 4 sub-pix rectanglar arrangements
According to reduction.
Figure 10 is a kind of structural schematic diagram of the sending card of the embodiment of the present invention.The sending card 100 of the present embodiment includes: view
Frequency receiver 101, data outputting module 103 and programmable logic device above-mentioned 31, MCU (Microcontroller, list
Piece machine) control module 33 and memory module 35.Wherein, video receiver 101 is adapted to video source such as host computer video card etc.,
It is for example including video decoding circuit as TDMS (Transition Minimized Differential Signaling, conversion
Minimum differential signal) decoding circuit etc..Programmable logic device 31 is connected electrically in video receiver 101 and data outputting module
Between 103, being, for example, FPGA (Field Programmable Gate Array, field programmable gate array) or other can
Programming device.Data outputting module 103 is for example including multiple network PHY chips and multiple network interfaces.The electrical connection of memory 35 can compile
Journey logical device 31, for example including SDRAM1 above-mentioned and SDRAM2.MCU control module 33 is electrically connected programmable logic device
31, sub-pix addressing and down-sampling operation are carried out for controlling the programmable logic device 31.
Referring to Figure 11, a kind of LED display control system of the embodiment of the present invention is shown.As shown in figure 11, LED is aobvious
Display screen control system includes aforementioned sending card 100 and receives card 200 and be suitable for that LED display 300 is driven to perform image display.Its
In, sending card 100 is suitable for electrical connection video source to obtain desire display image data, receives card 200 and is connected electrically in 200 He of sending card
Between LED display 300.
In conclusion the above embodiment of the present invention may achieve following one or several the utility model has the advantages that (1) can be improved plate
The system senses resolution ratio of display, can be applied on a variety of flat-panel monitors, and more high-resolution is realized on same display
The clear display of rate picture reduces display effect to the rigors of hardware system physical picture element resolution ratio；(2) it is able to ascend
LED display display capabilities, realized under conditions of not changing original LED display control system sub-pix addressing and under adopt
Sample technology is simultaneously preferably added anti-color error handle, reduces due to directly carrying out sub-pix addressing and down-sampling bring face
Color Problem-Error is effectively guaranteed the clarity of picture while providing display resolution；(3) it can be shown according to LED
The arrangement feature of the LED light point of screen selects suitable sub-pix addressing and down-sampling mode to be encoded, while may be implemented not
With the resume module algorithm of size, the video source image data being more suitable for is exported to LED display control system, so as to mention
Height while also improving display effect to the compatibility of different LED light points arrangement LED display.
Finally, it is noted that aforementioned is to carry out anti-color error handle with 3 × 3 templates, but the present invention is not with this
It is limited, 2 × 2 templates or triangle template etc. can also be used.In addition, the embodiment of the present invention is mainly to compiling in sending card
Journey logical device carries out innovative design, therefore those skilled in the art are on this basis to other circuits and device in sending card
The transformation such as increase and decrease appropriate are carried out, should be included within the scope of the present invention.
So far, specific case used herein is to programmable logic device of the invention, sending card and LED display control
The principle and embodiment of system processed is expounded, method of the invention that the above embodiments are only used to help understand
And its core concept；At the same time, for those skilled in the art, according to the thought of the present invention, in specific embodiment and
There will be changes in application range, in conclusion the contents of this specification are not to be construed as limiting the invention, the present invention
Protection scope should be subject to the attached claims.
Claims (10)
1. a kind of programmable logic device characterized by comprising
Sub-pix coding module, for carrying out sub-pix addressing and down-sampling to the image data of input to obtain down-sampled images
Data；
Buffer module is inputted, for caching the down-sampled images data；
RAM control module, for controlling the external RAM that the down-sampled images data are written to the programmable logic device；
And
Data packing block, for the down-sampled images obtained from the external RAM by the RAM control module
Data carry out packing output.
2. programmable logic device as described in claim 1, which is characterized in that the sub-pix coding module includes first pair
Mouth RAM, the second dual port RAM and third dual port RAM；What is stored respectively to first dual port RAM and second dual port RAM
During adjacent rows pixel data carries out the sub-pix addressing and down-sampling, the third double-interface RAM buffer next line
Pixel data.
3. programmable logic device as claimed in claim 2, which is characterized in that the input buffer module includes the 4th twoport
RAM, for caching the down-sampled images data.
4. programmable logic device as described in claim 1, which is characterized in that further include anti-color error handling module, use
It compiles in carrying out convolution algorithm according to default size template and be input to the sub-pix to obtain anti-color error handle image data
Code module.
5. programmable logic device as claimed in claim 4, which is characterized in that the color error handling module includes the 5th
Dual port RAM, the 6th dual port RAM, the 7th dual port RAM, the 8th dual port RAM, and be connected in the 5th to the 8th dual port RAM
Multiple registers of the outlet side of each dual port RAM.
6. a kind of sending card, including video receiver, programmable logic device, memory module and data outputting module, described
Programmable logic device is connected electrically between the video receiver and the data outputting module, the memory module electrical connection
The programmable logic device；It is characterized in that, the sending card further includes MCU control module, it is electrically connected described may be programmed and patrols
Collect device；And the programmable logic device includes:
Sub-pix coding module is sought for carrying out sub-pix to the image data of input under the control of the MCU control module
Location and down-sampling are to obtain down-sampled images data；
Buffer module is inputted, for caching the down-sampled images data；
For controlling the memory module is written in the down-sampled images data by RAM control module；And
Data packing block, for the down-sampling figure obtained from the memory module by the RAM control module
As data be packaged output to the data outputting module.
7. sending card as claimed in claim 6, which is characterized in that the sub-pix coding module includes the first dual port RAM, the
Two dual port RAMs and third dual port RAM；In the adjacent rows stored respectively to first dual port RAM and second dual port RAM
During pixel data carries out the sub-pix addressing and down-sampling, the third double-interface RAM buffer next line pixel data；
The input buffer module includes the 4th dual port RAM, for caching the down-sampled images data.
8. sending card as claimed in claim 6, which is characterized in that the programmable logic device further includes at anti-color mistake
Manage module, for carrying out convolution algorithm according to default size template with obtain anti-color error handle image data be input to it is described
Sub-pix coding module.
9. sending card as claimed in claim 8, which is characterized in that the color error handling module include the 5th dual port RAM,
6th dual port RAM, the 7th dual port RAM, the 8th dual port RAM, and it is connected to each in the 5th to the 8th dual port RAM pair
Multiple registers of the outlet side of mouth RAM.
10. a kind of LED display control system is performed image display suitable for driving LED display, the LED display control
System includes receiving card and the sending card as described in claim 6 to 9 any one, and the sending card is suitable for electrical connection video source
It is intended to display image data to obtain, the reception card is suitable for being connected electrically between the sending card and the LED display.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510442741.XA CN106710515B (en) | 2015-07-24 | 2015-07-24 | Programmable logic device, sending card and LED display control system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510442741.XA CN106710515B (en) | 2015-07-24 | 2015-07-24 | Programmable logic device, sending card and LED display control system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106710515A CN106710515A (en) | 2017-05-24 |
| CN106710515B true CN106710515B (en) | 2019-01-29 |
Family
ID=58894711
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510442741.XA Active CN106710515B (en) | 2015-07-24 | 2015-07-24 | Programmable logic device, sending card and LED display control system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106710515B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109801586B (en) | 2019-03-26 | 2021-01-26 | 京东方科技集团股份有限公司 | Display controller, display control method and system and display device |
| CN111768723B (en) * | 2020-08-05 | 2021-12-14 | 浙江德广信电子科技股份有限公司 | LED display screen unit and spatial resolution adjusting method thereof |
| TWI792668B (en) * | 2021-11-10 | 2023-02-11 | 大陸商集創北方（珠海）科技有限公司 | Data receiving circuit, display driver chip and information processing device |
| CN114822375A (en) * | 2022-03-18 | 2022-07-29 | 长春希达电子技术有限公司 | Display panel virtual pixel multiplexing structure, control method and system |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101770759A (en) * | 2008-12-17 | 2010-07-07 | 香港应用科技研究院有限公司 | Method and device for downsampling based on sub-pixel |
| CN101990103A (en) * | 2010-11-10 | 2011-03-23 | 香港应用科技研究院有限公司 | Method and device for multi-view video coding |
| KR20120052739A (en) * | 2010-11-16 | 2012-05-24 | 삼성전자주식회사 | Display driving device and method for compressing and decompressing image data in the same |
| CN103338378A (en) * | 2013-07-24 | 2013-10-02 | 西安电子科技大学 | Two-dimensional sub-pixel sampling-based super-resolution display method and device |
| CN104185011A (en) * | 2014-08-26 | 2014-12-03 | 四川虹微技术有限公司 | Multi-view image fusion device |
-
2015
- 2015-07-24 CN CN201510442741.XA patent/CN106710515B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101770759A (en) * | 2008-12-17 | 2010-07-07 | 香港应用科技研究院有限公司 | Method and device for downsampling based on sub-pixel |
| CN101990103A (en) * | 2010-11-10 | 2011-03-23 | 香港应用科技研究院有限公司 | Method and device for multi-view video coding |
| KR20120052739A (en) * | 2010-11-16 | 2012-05-24 | 삼성전자주식회사 | Display driving device and method for compressing and decompressing image data in the same |
| CN103338378A (en) * | 2013-07-24 | 2013-10-02 | 西安电子科技大学 | Two-dimensional sub-pixel sampling-based super-resolution display method and device |
| CN104185011A (en) * | 2014-08-26 | 2014-12-03 | 四川虹微技术有限公司 | Multi-view image fusion device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106710515A (en) | 2017-05-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105989802B (en) | Programmable logic device and its sub-pix Downsapling method and related application | |
| CN106710515B (en) | Programmable logic device, sending card and LED display control system | |
| CN103247247B (en) | Display device and driving method for the same | |
| CN108389552B (en) | Backlight illumination processing method and system, back light brightness regulating method, storage medium | |
| EP3134804B1 (en) | Multiple display pipelines driving a divided display | |
| KR101909367B1 (en) | Data transfer method, data transfer module, related display panel and method for driving the same, and related display device | |
| CN103325320B (en) | LED display screen with same-color chips arrayed diagonally and method for reusing pixels | |
| CN108604436A (en) | Device and method for pixel data rearrangement | |
| US8401339B1 (en) | Apparatus for partitioning and processing a digital image using two or more defined regions | |
| CN1713264A (en) | Digital OSD controller based on FRGA | |
| US7868898B2 (en) | Methods and apparatus for efficiently accessing reduced color-resolution image data | |
| CN108428435B (en) | The verifying display methods of one sub-pixel rendering | |
| CN107659800A (en) | A kind of DMD high frame frequency and high resolutions synchronous dynamic display system | |
| CN106328045B (en) | Programmable logic device and its sub-pix Downsapling method and data encoding circuit | |
| CN105609033A (en) | Pixel rendering method, pixel rendering device and display device | |
| CN107734337A (en) | Image processing method and relevant apparatus | |
| CN108022552A (en) | Emitting diode display device and its operating method | |
| CN106710514B (en) | Programmable logic device receives card and LED display control system | |
| CN115410525A (en) | Sub-pixel addressing method and device, display control system and display screen | |
| CN106328044B (en) | LED display control card and LED display control system | |
| CN105007444B (en) | A kind of single pixel video display devices and display methods | |
| CN114554171A (en) | Image format conversion method, device, display screen control equipment and storage medium | |
| CN102254515A (en) | Parallel LED drive system based on three-dimensional display | |
| CN114093312A (en) | Display data generation method and device based on virtual pixels | |
| KR101468995B1 (en) | Method for displaying image in linear-disposed plurality of lighting diodes of scene lighting display system and cene lighting display system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 710075 DEF101, Zero One Square, Xi'an Software Park, No. 72 Zhangbajie Science and Technology Second Road, Xi'an High-tech Zone, Shaanxi Province Patentee after: Xi'an Nova Nebula Technology Co., Ltd. Address before: 710075 Qinfengge D District 401, Xi'an Software Park, 68 Science and Technology Second Road, Xi'an High-tech Zone, Shaanxi Province Patentee before: Xian Novastar Electronic Technology Co., Ltd. |
|
| CP03 | Change of name, title or address |