CN117541456A - Image enhancement processing system design method based on SOC - Google Patents
Image enhancement processing system design method based on SOC Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/60—Memory management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T5/00—Image enhancement or restoration
- G06T5/20—Image enhancement or restoration by the use of local operators
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2207/00—Indexing scheme for image analysis or image enhancement
- G06T2207/10—Image acquisition modality
- G06T2207/10016—Video; Image sequence
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2207/00—Indexing scheme for image analysis or image enhancement
- G06T2207/20—Special algorithmic details
- G06T2207/20024—Filtering details
- G06T2207/20032—Median filtering
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses an image enhancement processing system design method based on SOC, which is based on SOC architecture to realize real-time image processing and peripheral control system in the FPGA, wherein the real-time image processing comprises an image input module, an image output module, an image storage module and an image operation module; the image input module performs selection analysis on the multipath video data to generate frame header, line validity and image data; the image output module generates a character mark according to the software configuration value, and the mark and the image data after image processing are synthesized to form a video signal in a PAL format and output the video signal to the display; based on the SOC architecture, the system is realized on the FPGA, the adjustment is carried out according to the change of the requirement, the dependence of an image enhancement processing algorithm on the DSP is reduced, all image operation and peripheral control are realized in the FPGA, the cost is reduced, a high-speed communication interface is not needed, and the parallel characteristic of the FPGA can reduce the working frequency of the whole system, so that the heat generation is less.
Description
Technical Field
The invention belongs to the technical field of image enhancement processing, and particularly relates to an image enhancement processing system design method based on SOC.
Background
The current mainstream method is to use FPGA and DSP as intelligent image processing and peripheral control devices, namely, the FPGA is used for realizing the image preprocessing function, the DSP is used for realizing the image processing algorithm and peripheral control, because the image data volume is relatively large, the data interaction between the FPGA and the DSP often needs a high-speed interface such as SRIO, the high-speed interface has high requirements on the design of a circuit board, and the DSP has relatively high requirements on the performance of the DSP due to the serial working mode of the DSP, so that the cost is high, the power consumption is high, and the heat is serious.
The invention relates to an FPGA implementation method of Hamilton self-adaptive interpolation in real-time image processing (application number: 201810581495. X). The invention utilizes 6 line RAMs to circularly buffer original Bayer data, utilizes 2 paths of G components to recover parallel operation, 3 paths of R, B components to operate in parallel, pipeline processing, data synchronization and the like, and the method realizes the Hamilton self-adaptive interpolation algorithm on the FPGA, can realize real-time processing of high-resolution (maximally supporting 4K by 4K resolution) video streams, obtains higher-quality images, has better image recovery processing effect than the traditional linear interpolation algorithm, and has great margin in consuming logic resources and maximum working frequency.
Aiming at the defects of the currently adopted DSP+FPGA real-time image processing and control system, the SOC architecture is used for realizing an algorithm circuit and performing peripheral control, the acquired image can be subjected to image processing such as tracking, identification and matching, and the external device is controlled and interacted according to software configuration, and the verification test result of large-size convolution operation shows that the designed SOC architecture has the characteristics of good universality, high reliability, high processing speed and accurate control, and can completely adapt to high-complexity convolution operation, so that the design method of the image enhancement processing system based on the SOC is needed.
Disclosure of Invention
The invention aims to provide an image enhancement processing system design method based on SOC, all image operation and peripheral control are realized in an FPGA, so that cost is reduced, a high-speed communication interface is not needed, the parallel characteristic of the FPGA can reduce the working frequency of the whole system, heat is less, an SOC architecture is used for realizing an algorithm circuit and peripheral control, acquired images can be subjected to image processing such as tracking, identification and matching, and the like, and meanwhile, the external devices are controlled and interacted according to software configuration, and the verification test result of large-size convolution operation shows that the designed SOC architecture has the characteristics of good universality, high reliability, high processing speed and accurate control, can completely adapt to the high-complexity convolution operation, so that the problem that the data interaction between the FPGA and the DSP in the prior art needs a high-speed interface such as SRIO in the prior art is solved, the high-speed interface has high design requirement on a circuit board, and the DSP serial working mode often has high requirements on the DSP performance, so that the cost is high, the power consumption is serious, and the currently adopted DSP+the FPGA image processing and the control system is insufficient.
In order to achieve the above purpose, the invention adopts the following technical scheme: an image enhancement processing system design method based on SOC comprises the following steps:
step 1: realizing real-time image processing and a peripheral control system in the FPGA based on the SOC architecture, wherein the real-time image processing comprises an image input module, an image output module, an image storage module and an image operation module;
step 2: the image input module performs selection analysis on the multipath video data to generate frame header, line validity and image data;
step 3: the image output module generates a character mark according to the software configuration value, and the mark and the image data after image processing are synthesized to form a video signal in a PAL format and output the video signal to the display;
step 4: the image storage module is used for highlighting certain useful information before storing the image, weakening harmful useless information and carrying out the processing of geometric form changes such as position, shape, size and the like on the whole or part of the image;
step 5: image preprocessing and target monitoring, identification and tracking are realized by verilo, a circuit is formed in an FPGA, the working frequency is low, the method is not applicable to a high-performance DSP, and software changes the parameter configuration of an image operation module according to a scene;
step 6: based on the SOC architecture, the image enhancement processing algorithm is realized on the FPGA, and is adjusted according to the change of the requirement, so that the dependence of the image enhancement processing algorithm on the DSP is reduced.
Preferably, in step 1, the image input module: analyzing the image data of the front-stage device input according to a protocol to generate an image time sequence and format which can be processed internally; an image output module: performing character superposition on the processed digital image; an image storage module: the image data is stored, so that the operation of the image is convenient; an image operation module: preprocessing the analyzed image, and carrying out image processing operations such as target detection, identification, tracking and the like to generate parameters; and the peripheral control module is used for: initializing and controlling an external device, and simultaneously performing visual field control on the external device according to parameters generated by the image operation module; the SOC, which is an abbreviation of System on Chip, is also referred to as a System on Chip, and we refer to as a "System" because it is not a single module but an aggregate of multiple modules. In a narrow sense, the information system is integrated by a chip of a core of the information system, and key components of the system are integrated on one chip; in a broad sense, SOC is a miniature system.
Preferably, the hardware composition of the SOC chip approximately includes: core, bus, memory module, interrupt module, clock module, peripheral interface, etc. through the combination of different modules, a complete system is formed together, and the function of an electronic system can be completed on a single chip, and the system usually needs one or more circuit boards before and various electronic devices, chips and interconnection lines on the board cooperate together to realize, but SoC is more integrated to processors (including CPU, DSP), memories, various interface control modules, various interconnection buses.
Preferably, in step 2, the image data is mainly divided into two types, i.e. an identifier and an image, the software firstly configures different registers to analyze the image according to the reported identifier information, for example, multiple paths of video inputs are provided, and the registers can be configured to select a mixed packet analysis mode or a pure data analysis mode according to the identifier read back by the software.
Preferably, in the step 3, the method is divided into four functional parts according to scenes: the image invariant position changing function block can complete functions according to corresponding coordinates configured by software, the image invariant position changing function block can read addresses of a character library according to the software configuration, the image invariant position changing function block can calculate fixed graphics only by giving coordinates, and the PAL_SND is used as a video signal output end. For even fields, the effective data lines are all even lines of a frame of image, and for odd fields, the effective data lines are all odd lines of a frame of image, when the effective data lines are realized on the FPGA, two dual-port RAMs are needed inside, one is used for storing the effective data of the odd fields, the other is used for storing the effective data of the even fields, after writing into a frame is finished, the counter is used for selectively sending the anti-shadow data, the effective data of the odd fields and the effective data of the even fields, and the anti-shadow data, the effective data of the odd fields and the effective data of the even fields are synthesized into a complete frame of image.
Preferably, in step 4, a large amount of noise is effectively removed by a low-pass spatial filter, so that the image is better smoothed and a certain damage is caused to the boundary. For the regular stripes, the method is suitable, and the common homogenization template in the low-pass spatial filter is to sum all gray values in the template and average the gray values, then write the average value into the pixel of the corresponding point in the middle of the template, and the next pixel is processed after the next template is moved, so the method is also called a moving average filter. This filter removes noise but also produces the negative effect of image blurring.
Preferably, in step 5, the oscillations are smoothed by median filtering, so that the edges of the image are better protected, the sorting operation of the template is a nonlinear filtering mode to sort the gray scales of all pixels in the template, then the gray scale values sorted in the middle are selected, and the values are substituted into the corresponding pixels, so that the filtering operation of one pixel is completed. The low-pass filtering is an averaging method, the edge effect of which is destroyed, the image is blurred, and the median filtering is a sorting method, the image and the edge of which have better retaining effect, and on the noise treatment, the noise is hardly seen in the image after the median filtering treatment.
Preferably, in step 6, the FPGA needs to initialize the peripheral device and also needs to interact with the peripheral device to obtain the information detection state during normal operation, so a CPU needs to be designed as a master control, I2C, UART, SPI and the like as a peripheral interface, and the CPU is implemented inside the FPGA by using a soft core as a master control unit. The UART module can be used for communicating with a PC, performing the functions of writing parameters, sending data to an upper computer and the like, and can realize FLASH program upgrading, program debugging and data readback of the system. The I2C bus is a bus commonly used in device interconnection and is used for initializing peripheral devices such as a video encoding and decoding chip, and SPI can realize read-write control on the SPI device and is used for rewriting and reading SPI FLASH data and the like.
Preferably, the SoCpartification algorithm places state machine software (those algorithms that provide application control, sequencing, user interface control, event driven software, etc.) on a RISCprocessor, places signal processing software on a DSP, and places high-rate, computationally intensive algorithms in the hardware accelerator using the application-specific architecture provided by the DSP for the signal processing functions.
Preferably, the DSP comprises a similar chip support library, an aDSP-centric kernel, a set of DSP-specific algorithms, and interfaces to high-level applications, and the accelerator comprises a set of apis for programmer access and some very specific algorithms mapped to acceleration.
The invention has the technical effects and advantages that: compared with the prior art, the image enhancement processing system design method based on the SOC has the following advantages:
the invention realizes the real-time image processing and the peripheral control system in the FPGA based on the SOC architecture, wherein the real-time image processing comprises an image input module, an image output module, an image storage module and an image operation module; the image input module performs selection analysis on the multipath video data to generate frame header, line validity and image data; the image output module generates a character mark according to the software configuration value, and the mark and the image data after image processing are synthesized to form a video signal in a PAL format and output the video signal to the display; the image storage module is used for highlighting certain useful information before storing the image, weakening harmful useless information and carrying out the processing of geometric form changes such as position, shape, size and the like on the whole or part of the image; image preprocessing and target monitoring, identification and tracking are realized by verilo, a circuit is formed in an FPGA, the working frequency is low, the method is not applicable to a high-performance DSP, and software changes the parameter configuration of an image operation module according to a scene; based on the SOC architecture, the image enhancement processing algorithm is realized on the FPGA, and is adjusted according to the change of the requirement, so that the dependence of the image enhancement processing algorithm on the DSP is reduced.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
FIG. 1 is a microstructure diagram of a real-time image processing and control system of the present invention;
FIG. 2 is a flow chart of the steps of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. The specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention provides an image enhancement processing system design method based on SOC, which is shown in fig. 1-2, and comprises the following steps:
step 1: realizing real-time image processing and a peripheral control system in the FPGA based on the SOC architecture, wherein the real-time image processing comprises an image input module, an image output module, an image storage module and an image operation module;
step 2: the image input module performs selection analysis on the multipath video data to generate frame header, line validity and image data;
step 3: the image output module generates a character mark according to the software configuration value, and the mark and the image data after image processing are synthesized to form a video signal in a PAL format and output the video signal to the display;
step 4: the image storage module is used for highlighting certain useful information before storing the image, weakening harmful useless information and carrying out the processing of geometric form changes such as position, shape, size and the like on the whole or part of the image;
step 5: image preprocessing and target monitoring, identification and tracking are realized by verilo, a circuit is formed in an FPGA, the working frequency is low, the method is not applicable to a high-performance DSP, and software changes the parameter configuration of an image operation module according to a scene;
step 6: based on the SOC architecture, the image enhancement processing algorithm is realized on the FPGA, and is adjusted according to the change of the requirement, so that the dependence of the image enhancement processing algorithm on the DSP is reduced.
In step 1, the image input module: analyzing the image data of the front-stage device input according to a protocol to generate an image time sequence and format which can be processed internally; an image output module: performing character superposition on the processed digital image; an image storage module: the image data is stored, so that the operation of the image is convenient; an image operation module: preprocessing the analyzed image, and carrying out image processing operations such as target detection, identification, tracking and the like to generate parameters; and the peripheral control module is used for: initializing and controlling an external device, and simultaneously performing visual field control on the external device according to parameters generated by the image operation module; the SOC, which is an abbreviation of System on Chip, is also referred to as a System on Chip, and we refer to as a "System" because it is not a single module but an aggregate of multiple modules. In a narrow sense, the information system is integrated by a chip of a core of the information system, and key components of the system are integrated on one chip; in a broad sense, SOC is a miniature system.
The hardware composition of the SOC chip roughly includes: core, bus, memory module, interrupt module, clock module, peripheral interface, etc. through the combination of different modules, a complete system is formed together, and the function of an electronic system can be completed on a single chip, and the system usually needs one or more circuit boards before and various electronic devices, chips and interconnection lines on the board cooperate together to realize, but SoC is more integrated to processors (including CPU, DSP), memories, various interface control modules, various interconnection buses.
In step 2, the image data is mainly divided into two types of identification and image, the software firstly configures different registers to analyze the image according to the reported identification information, for example, multiple paths of video inputs exist, and the registers can be configured according to the identification read back by the software to select a mixed package analysis mode or a pure data analysis mode.
In step 3, the method is divided into four functional parts according to scenes: the image invariant position changing function block can complete functions according to corresponding coordinates configured by software, the image invariant position changing function block can read addresses of a character library according to the software configuration, the image invariant position changing function block can calculate fixed graphics only by giving coordinates, and the PAL_SND is used as a video signal output end. For even fields, the effective data lines are all even lines of a frame of image, and for odd fields, the effective data lines are all odd lines of a frame of image, when the effective data lines are realized on the FPGA, two dual-port RAMs are needed inside, one is used for storing the effective data of the odd fields, the other is used for storing the effective data of the even fields, after writing into a frame is finished, the counter is used for selectively sending the anti-shadow data, the effective data of the odd fields and the effective data of the even fields, and the anti-shadow data, the effective data of the odd fields and the effective data of the even fields are synthesized into a complete frame of image.
In step 4, a large amount of noise is effectively removed through a low-pass spatial filter, so that the image is better smoothed and has a certain damage to the boundary. For the regular stripes, the method is suitable, and the common homogenization template in the low-pass spatial filter is to sum all gray values in the template and average the gray values, then write the average value into the pixel of the corresponding point in the middle of the template, and the next pixel is processed after the next template is moved, so the method is also called a moving average filter. This filter removes noise but also produces the negative effect of image blurring.
In step 5, the oscillations are smoothed by median filtering, so that the edges of the image are better protected, the sorting operation of the template is a nonlinear filtering mode for sorting the gray scales of all pixels in the template, then the gray scale values sorted in the middle are selected, and the values are substituted into the corresponding pixels, so that the filtering operation of one pixel is completed. The low-pass filtering is an averaging method, the edge effect of which is destroyed, the image is blurred, and the median filtering is a sorting method, the image and the edge of which have better retaining effect, and on the noise treatment, the noise is hardly seen in the image after the median filtering treatment.
In step 6, the FPGA needs to initialize the peripheral device and also needs to interact with the peripheral device to obtain the information detection state during normal operation, so it is necessary to design a CPU as a master control, I2C, UART, SPI and the like as peripheral interfaces, the CPU as a master control unit, and the soft core is used to implement in the FPGA. The UART module can be used for communicating with a PC, performing the functions of writing parameters, sending data to an upper computer and the like, and can realize FLASH program upgrading, program debugging and data readback of the system. The I2C bus is a bus commonly used in device interconnection and is used for initializing peripheral devices such as a video encoding and decoding chip, and SPI can realize read-write control on the SPI device and is used for rewriting and reading SPI FLASH data and the like.
The SoCpartification algorithm places state machine software (those algorithms that provide application control, sequencing, user interface control, event driven software, etc.) on a RISCprocessor, places signal processing software on a DSP, and places high-rate, computationally intensive algorithms in the hardware accelerator using the application-specific architecture provided by the DSP for the signal processing functions.
The DSP comprises a similar chip support library, an aDSP-centric kernel, a set of DSP-specific algorithms and interfaces with advanced application software, and the accelerator comprises a set of apis for access by programmers and some very specific algorithms mapped to the acceleration
Working principle: realizing real-time image processing and a peripheral control system in the FPGA based on the SOC architecture, wherein the real-time image processing comprises an image input module, an image output module, an image storage module and an image operation module; the image input module performs selection analysis on the multipath video data to generate frame header, line validity and image data; the image output module generates a character mark according to the software configuration value, and the mark and the image data after image processing are synthesized to form a video signal in a PAL format and output the video signal to the display; the image storage module is used for highlighting certain useful information before storing the image, weakening harmful useless information and carrying out the processing of geometric form changes such as position, shape, size and the like on the whole or part of the image; image preprocessing and target monitoring, identification and tracking are realized by verilo, a circuit is formed in an FPGA, the working frequency is low, the method is not applicable to a high-performance DSP, and software changes the parameter configuration of an image operation module according to a scene; based on the SOC architecture, the image enhancement processing algorithm is realized on the FPGA, and is adjusted according to the change of the requirement, so that the dependence of the image enhancement processing algorithm on the DSP is reduced.
Finally, it should be noted that: the foregoing description is only illustrative of the preferred embodiments of the present invention, and although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described, or equivalents may be substituted for elements thereof, and any modifications, equivalents, improvements or changes may be made without departing from the spirit and principles of the present invention.
Claims (10)
1. An image enhancement processing system design method based on SOC is characterized in that: the method comprises the following steps:
step 1: realizing real-time image processing and a peripheral control system in the FPGA based on the SOC architecture, wherein the real-time image processing comprises an image input module, an image output module, an image storage module and an image operation module;
step 2: the image input module performs selection analysis on the multipath video data to generate frame header, line validity and image data;
step 3: the image output module generates a character mark according to the software configuration value, and the mark and the image data after image processing are synthesized to form a video signal in a PAL format and output the video signal to the display;
step 4: the image storage module is used for highlighting certain useful information before storing the image, weakening harmful useless information and carrying out the processing of geometric form changes such as position, shape, size and the like on the whole or part of the image;
step 5: image preprocessing and target monitoring, identification and tracking are realized by verilo, a circuit is formed in an FPGA, the working frequency is low, the method is not applicable to a high-performance DSP, and software changes the parameter configuration of an image operation module according to a scene;
step 6: based on the SOC architecture, the image enhancement processing algorithm is realized on the FPGA, and is adjusted according to the change of the requirement, so that the dependence of the image enhancement processing algorithm on the DSP is reduced.
2. The SOC-based image enhancement processing system design method of claim 1, wherein: in step 1, the image input module: analyzing the image data of the front-stage device input according to a protocol to generate an image time sequence and format which can be processed internally; an image output module: performing character superposition on the processed digital image; an image storage module: the image data is stored, so that the operation of the image is convenient; an image operation module: preprocessing the analyzed image, and carrying out image processing operations such as target detection, identification, tracking and the like to generate parameters; and the peripheral control module is used for: initializing and controlling an external device, and simultaneously performing visual field control on the external device according to parameters generated by the image operation module; the SOC, which is an abbreviation of System on Chip, is also referred to as a System on Chip, and we refer to as a "System" because it is not a single module but an aggregate of multiple modules. In a narrow sense, the information system is integrated by a chip of a core of the information system, and key components of the system are integrated on one chip; in a broad sense, SOC is a miniature system.
3. The SOC-based image enhancement processing system design method of claim 2, wherein: the hardware composition of the SOC chip approximately includes: core, bus, memory module, interrupt module, clock module, peripheral interface, etc. through the combination of different modules, a complete system is formed together, and the function of an electronic system can be completed on a single chip, and the system usually needs one or more circuit boards before and various electronic devices, chips and interconnection lines on the board cooperate together to realize, but SoC is more integrated to processors (including CPU, DSP), memories, various interface control modules, various interconnection buses.
4. The SOC-based image enhancement processing system design method of claim 1, wherein: in step 2, the image data is mainly divided into two types, namely an identification and an image, the software firstly configures different registers to analyze the image according to the reported identification information, for example, multiple paths of video inputs exist, and the registers can be configured to select a mixed package analysis mode or a pure data analysis mode according to the identification read back by the software.
5. The SOC-based image enhancement processing system design method of claim 1, wherein: in the step 3, the method is divided into four functional parts according to scenes: the image invariant position changing function block can complete functions according to corresponding coordinates configured by software, the image invariant position changing function block can read addresses of a character library according to the software configuration, the image invariant position changing function block can calculate fixed graphics only by giving coordinates, and the PAL_SND is used as a video signal output end. For even fields, the effective data lines are all even lines of a frame of image, and for odd fields, the effective data lines are all odd lines of a frame of image, when the effective data lines are realized on the FPGA, two dual-port RAMs are needed inside, one is used for storing the effective data of the odd fields, the other is used for storing the effective data of the even fields, after writing into a frame is finished, the counter is used for selectively sending the anti-shadow data, the effective data of the odd fields and the effective data of the even fields, and the anti-shadow data, the effective data of the odd fields and the effective data of the even fields are synthesized into a complete frame of image.
6. The SOC-based image enhancement processing system design method of claim 1, wherein: in step 4, a large amount of noise is effectively removed through a low-pass spatial filter, so that the image is better smoothed and has a certain damage to the boundary. For the regular stripes, the method is suitable, and the common homogenization template in the low-pass spatial filter is to sum all gray values in the template and average the gray values, then write the average value into the pixel of the corresponding point in the middle of the template, and the next pixel is processed after the next template is moved, so the method is also called a moving average filter. This filter removes noise but also produces the negative effect of image blurring.
7. The SOC-based image enhancement processing system design method of claim 1, wherein: in step 5, the oscillations are smoothed by median filtering, so that the edges of the image are well protected, the sorting operation of the template is a nonlinear filtering mode for sorting the gray scales of all pixels in the template, then the gray scale values sorted in the middle are selected, and the values are substituted into the corresponding pixels, so that the filtering operation of one pixel is completed. The low-pass filtering is an averaging method, the edge effect of which is destroyed, the image is blurred, and the median filtering is a sorting method, the image and the edge of which have better retaining effect, and on the noise treatment, the noise is hardly seen in the image after the median filtering treatment.
8. The SOC-based image enhancement processing system design method of claim 1, wherein: in step 6, the FPGA needs to initialize the peripheral device and also needs to interact with the peripheral device to obtain the information detection state during normal operation, so it is necessary to design a CPU as a master control, I2C, UART, SPI and the like as peripheral interfaces, and the CPU as a master control unit and implemented inside the FPGA using a soft core. The UART module can be used for communicating with a PC, performing the functions of writing parameters, sending data to an upper computer and the like, and can realize FLASH program upgrading, program debugging and data readback of the system. The I2C bus is a bus commonly used in device interconnection and is used for initializing peripheral devices such as a video encoding and decoding chip, and SPI can realize read-write control on the SPI device and is used for rewriting and reading SPI FLASH data and the like.
9. The SOC-based image enhancement processing system design method of claim 8, wherein: the SoCpartification algorithm places state machine software (those algorithms that provide application control, sequencing, user interface control, event driven software, etc.) on a RISCprocessor, places signal processing software on a DSP, and places high-rate, computationally intensive algorithms in the hardware accelerator using the application-specific architecture provided by the DSP for the signal processing functions.
10. The SOC-based image enhancement processing system design method of claim 9, wherein: the DSP contains a similar chip support library, an aDSP-centric kernel, a set of DSP-specific algorithms, and interfaces to high-level applications, and the accelerator contains a set of api's for programmer access and some very specific algorithms mapped to acceleration.
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