CN203191970U - Switchable USB port design - Google Patents
Switchable USB port design Download PDFInfo
- Publication number
- CN203191970U CN203191970U CN 201320181619 CN201320181619U CN203191970U CN 203191970 U CN203191970 U CN 203191970U CN 201320181619 CN201320181619 CN 201320181619 CN 201320181619 U CN201320181619 U CN 201320181619U CN 203191970 U CN203191970 U CN 203191970U
- Authority
- CN
- China
- Prior art keywords
- usb
- usb interface
- south
- usb port
- path
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000001514 detection method Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 102100032616 Caspase-2 Human genes 0.000 description 2
- 102100025597 Caspase-4 Human genes 0.000 description 2
- 101100273284 Homo sapiens CASP4 gene Proteins 0.000 description 2
- 101000867612 Homo sapiens Caspase-2 Proteins 0.000 description 2
- 101000941170 Homo sapiens U6 snRNA phosphodiesterase 1 Proteins 0.000 description 2
- 102100031314 U6 snRNA phosphodiesterase 1 Human genes 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Images
Abstract
The utility model discloses a switchable USB port design. The switchable USB port design comprises USBSWITCH chips, a complex programmable logic device or an FPGA and two sets of USB ports including UI1s and UI2s, wherein the two sets of USB ports are arranged on a front panel, switching is carried out between a main four-path south bridge and a secondary four-path south bridge on two USB port signals of the UI2s through the USBSWITCH chips, detection is carried out on a TS850 system through the CPLD or the FPGA, when the TS850 system is in a single-eight-path mode or a single-four-path mode, the two USB port signals of the U12s are switched to the main four-path south bridge, and when the TS850 system is in a double-four-path mode, the two USB port signals of the UI2s are switched to the secondary four-path south bridge. In the TS850 system, due to the design of the USB ports, simultaneous use of the four USB ports of the front panel is achieved, and the use rate of the ports is improved.
Description
Technical field
The utility model relates to field of computer technology, specifically a kind of switchable USB interface design.
Background technology
In the TS850 system, front panel has two groups of UI1﹠amp; UI2, having 4 USB interface is respectively UI1_USB_PORT1/UI1_USB_PORT2 ﹠amp; UI2_USB_PORT1/UI2_USB_PORT2.Under two 4 tunnel patterns, two USB interface of UI1 are connected under master 4 tunnel the south bridge, and as main 4 tunnel USB interface usefulness, two USB interface of UI2 are connected under 4 tunnel south bridge, as using from 4 tunnel USB interface.And at single 8 Lu ﹠amp; Under single 4 tunnel patterns, owing to the south bridge that does not have from 4 tunnel, two USB interface of UI2 can not be used, and cause the interface waste.
The utility model content
The utility model provides a kind of switchable USB interface design at the problem that prior art exists.
The utility model discloses a kind of switchable USB interface design, its technical scheme is as follows: in the TS850 system, but the design of described USB interface comprises two groups of USB interface UI1﹠amp of USB SWITCH chip logic compiler device CPLD or FPGA and front panel; UI2, two USB interface signals of described UI2 are being led 4 south of road bridges and are being switched between 4 south of road bridges by described USB SWITCH chip, but by described logic compiler device CPLD or FPGA detecting TS850 system, if system is in list 8 road or single 4 tunnel patterns, then two of UI2 USB interface signals switch to main 4 south of road bridges, if system is in two 4 tunnel patterns, then two of UI2 USB interface signals switch to from 4 south of road bridges.
The beneficial effect that switchable USB interface design disclosed in the utility model has is: in the TS850 system, by this USB interface design, can utilize USB SWITCH chip that the signal of two USB interface of UI2 is being led 4 south of road bridges and switched between 4 south of road bridges, use when having realized in the front panel four USB interface, improved the interface utilization factor.
Description of drawings
Accompanying drawing 1 is the synoptic diagram of front panel USB interface in the utility model TS850 system;
Accompanying drawing 2 is the logic diagram of USB interface design described in the utility model;
Accompanying drawing marking explanation: 1, front panel; 2, UI1_USB_PORT1; 3, UI1_USB_PORT2; 4, UI2_USB_PORT1; 5, UI2_USB_PORT2.
Embodiment
Below in conjunction with accompanying drawing, switchable USB interface design disclosed in the utility model is described in further details.
Switchable USB interface disclosed in the utility model designs, but comprises two groups of USB interface UI1﹠amp of USB SWITCH chip logic compiler device CPLD or FPGA and front panel; UI2, two USB interface signals of described UI2 are being led 4 south of road bridges and are being switched between 4 south of road bridges by described USB SEITCH chip, but by described logic compiler device CPLD or FPGA detecting TS850 system, if system is in list 8 road or single 4 tunnel patterns, then two of UI2 USB interface signals switch to main 4 south of road bridges, and 4 of front panel USB interface are all available like this; If system is in two 4 tunnel patterns, then two of UI2 USB interface signals switch to from 4 south of road bridges, 4 USB interface of front panel like this, and principal and subordinate 4 tunnel is respectively with two.
Fig. 1 is the USB interface synoptic diagram of front panel in the TS850 system, and visible front panel (1) has two groups of USB interface UI1﹠amp; UI2, described UI1﹠amp; UI2 is respectively UI1_USB_PORT1(2)/UI1_USB_PORT2 (3) ﹠amp; UI2_USB_PORT1(4)/UI2_USB_PORT2(5).Fig. 2 is the synoptic diagram of described USB interface design, and as we know from the figure, in the TS850 system, two USB interface UI1_USB_PORT1/UI1_USB_PORT2 of UI1 are connected under master 4 tunnel the south bridge; But logic compiler device CPLD or FPGA link to each other with USB SWITCH chip, when being in list 8 road or single 4 tunnel patterns by CPLD or FPGA detecting TS850 system, UI2_USB_PORT1 is connected under main 4 south of road bridges by circuit ICH1 USB1, and UI2_USB_PORT2 is connected under main 4 south of road bridges by circuit ICH1 USB2; When being in two 4 tunnel patterns by CPLD or FPGA detecting TS850 system, UI2_USB_PORT1 is connected under main 4 south of road bridges by circuit ICH2 USB1, and UI2_USB_PORT2 is connected under 4 south of road bridges by circuit ICH2 USB2.
Except technical characterictic described in the utility model, be the known technology of those skilled in the art.
Claims (1)
1. a switchable USB interface design is characterized in that, but comprises two groups of USB interface UI1﹠amp of USB SWITCH chip logic compiler device CPLD or FPGA and front panel; UI2, two USB interface signals of described UI2 are being led 4 south of road bridges and are being switched between 4 south of road bridges by described USB SWITCH chip, but by described logic compiler device CPLD or FPGA detecting TS850 system, if system is in list 8 road or single 4 tunnel patterns, then two of UI2 USB interface signals switch to main 4 south of road bridges, if system is in two 4 tunnel patterns, then two of UI2 USB interface signals switch to from 4 south of road bridges.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320181619 CN203191970U (en) | 2013-04-12 | 2013-04-12 | Switchable USB port design |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320181619 CN203191970U (en) | 2013-04-12 | 2013-04-12 | Switchable USB port design |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203191970U true CN203191970U (en) | 2013-09-11 |
Family
ID=49108813
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201320181619 Expired - Fee Related CN203191970U (en) | 2013-04-12 | 2013-04-12 | Switchable USB port design |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203191970U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109960674A (en) * | 2019-04-08 | 2019-07-02 | 济南浪潮高新科技投资发展有限公司 | A kind of USB interface interconnected method and system based on FPGA |
-
2013
- 2013-04-12 CN CN 201320181619 patent/CN203191970U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109960674A (en) * | 2019-04-08 | 2019-07-02 | 济南浪潮高新科技投资发展有限公司 | A kind of USB interface interconnected method and system based on FPGA |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN203480022U (en) | Super-high speed general radar signal processing board | |
| CN205193795U (en) | Multi -functional interface system of extensible | |
| CN202443357U (en) | Multi-PCIE (peripheral component interconnect express)-signal interface mainboard with peer-to-peer communication function | |
| CN101630182A (en) | Computer system capable of configuring SIO | |
| CN102902829B (en) | A kind of high speed magnanimity real-time data acquisition disposal system | |
| CN204203964U (en) | The portable type ground testing apparatus that a kind of multichannel data stores | |
| CN203191970U (en) | Switchable USB port design | |
| CN203038046U (en) | Control panel | |
| CN203117981U (en) | High-speed synchronous analog quantity acquisition board of relay protection device | |
| CN205068383U (en) | Many channel data synchronous sampling system | |
| CN204991907U (en) | Big dipper four -frequency point multiplexer | |
| CN103729320A (en) | Method for implementing CY7C68013 communication on basis of FPGA (field programmable gate array) | |
| CN202721686U (en) | Network processing controller card with state detection | |
| CN204406391U (en) | A kind of data of optical fiber gyroscope R-T unit based on SPI | |
| CN205334462U (en) | USB changes interface converting device of two serial portss | |
| CN207649880U (en) | A kind of optical module test system of changeable circuit | |
| CN207516997U (en) | A kind of outband management module that NVMe SSD are carried out using CPLD | |
| CN103063853B (en) | A kind of blood type reagent card | |
| CN203191892U (en) | Multiport collocated board card based on field programmable gate array (FPGA) | |
| CN201576298U (en) | Automatic detecting and switching device for dual interface smartcard clock sources | |
| CN202495943U (en) | Bluetooth chip rapid detection system | |
| CN205942681U (en) | Serial communication interface that can dispose | |
| CN204576136U (en) | A kind of parallel data high speed acquisition device | |
| CN203561983U (en) | Computer testing OCIO function board card | |
| CN204203965U (en) | A kind of data transmission board for portable type ground testing apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130911 Termination date: 20160412 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |