CN207115115U - A kind of microcontroller single line detail programming interface arrangement - Google Patents

Abstract

The utility model discloses a kind of microcontroller single line detail programming interface arrangement, device includes：Control chip and objective chip, it is used as debugging using an I/O pin D_IO between the control chip and the objective chip.It is less using pin using method of the present utility model, resource is more saved, and communication speed scope is wider, pin uses less, to communication clock without fixed demand.In addition, the utility model possesses communication speed adaptive ability.

Description

A kind of microcontroller single line detail programming interface arrangement

Technical field

Debugging interface and software debugging field are the utility model is related to, more particularly to a kind of microcontroller single line programming is adjusted Try interface arrangement.

Background technology

JTAG (Joint Test Action Group, joint test working group) interfacing, it is that a kind of international standard is surveyed Agreement (IEEE 1149.1 is compatible) is tried, is mainly used in chip internal test.It is applied to microcontroller memory programming with And the debugging of microcontroller is relatively broad, high-grade devices now most JTAG all supports JTAG protocol, such as DSP, FPGA device Deng.The jtag interface of standard is 4 lines：TMS, TCK, TDI, TDO, respectively model selection, clock, data input and data output Line.Jtag interface technology is due to having special Data In-Line and DOL Data Output Line, so the transmission to data is ageing and imitates Rate is relatively high, but its most important shortcoming is：It is relatively more to take pin, in the micro-control that some pin resources are more nervous Device processed using be very waste of resource or in developer using above bringing some unnecessary troubles.

Chip is when secondary development is carried out, in order to more accurately use chip, it is often necessary to chip running status Real-time query is carried out, chip internal running situation can accurately be recognized by debugging interface, is carried out by third-party platform visual Change conversion, quick search chip runs in the state of whether operating in desired by developer, timely error correction, can so saved out The time of originator.There are some solution methods in the prior art, such as, a kind of chips of Chinese patent application CN200810016527.8 Debugging interface device, including：USB port, for link information processing equipment；I2C ports, for connecting chip；Main process task fills Put, for supporting the data transfer of USB port and I2C ports respectively, the I2C ports, USB port are mutual by primary processing unit Phase control；The primary processing unit includes the first general controls interface, the second general controls interface；The I2C ports include number According to transmission mouth, clock control mouth, the first general controls interfacing data transmission mouth carries out data transfer reception, and described the Two general control interface connection clock control mouths carry out clock information transmission and received；The USB port includes differential signal interface, The primary processing unit also includes differential signal output interface, and the differential signal interface connects differential signal output interface, uses To carry out the transmission of differential signal and reception.Although the advantages of being attached chip using I2C ports is clock and data point Open, be that debugger is initiated, disadvantage is that taking two chip pins without requiring clock.Again for example, China Patent application CN201480013721.4 single lines program and debugging interface, and it includes having the shell of external pin and use only single The integrated debugging interface of one signal pins.The speed of docking port has carried out strict agreement in this application, it is desirable to uses fixation Traffic rate, higher requirement is proposed to objective chip for asynchronous-sampling in single line debugging.In the other patent clearly MCLR is needed to coordinate operation with high pressure to open monofilar mode, therefore the device is except using objective chip VDD VSS one-wire interfaces also Need to be in advance using once MCLR pins, also and non-critical one-wire interface device.

To sum up, there is one kind to be supplied fewer using pin, more save resource, communication speed scope is wider and to communication Single line detail programming interface arrangement of the clock without fixed demand.

Utility model content

The technical problems to be solved in the utility model is to provide one kind and uses pin fewer, more saves the micro- of resource Controller single line detail programming interface arrangement.

Solves above-mentioned technical problem, the utility model provides a kind of microcontroller single line detail programming interface arrangement, wraps Include：Control chip and objective chip, it is used as adjusting using an I/O pin D_IO between the control chip and the objective chip Examination.

Further, the control chip is connected by UART communications protocol with objective chip.

Further, power pin VDD, VSS are connected with the control chip in the objective chip.

The beneficial effects of the utility model：

Microcontroller single line detail programming interface arrangement in the utility model, due to including：Control chip and target core Piece, it is used as debugging using an I/O pin D_IO between the control chip and the objective chip.By using objective chip VDD, VSS (are often referred to circuit common ground terminal voltage GND), and D_IO is used as adjusting in addition to power pin, using only an I/O pin Examination.In addition, also configure port collision testing mechanism in device, by it is abnormal disturb such as occur peripheral debugger send order with Objective chip debugging pin clashes, and detects pin level, then the present apparatus can exit output mode, avoid conflict.

In addition, in the utility model in the adjustment method of microcontroller single line detail programming interface arrangement, compatibility standard UART communications protocol, target can adapt to communication speed, communication speed scope 1.2Khz~1000Khz automatically.With prior art phase Than method of the present utility model is less using pin, more saves resource, and communication speed scope is wider, and pin uses less, to logical Clock is interrogated without fixed demand.

Brief description of the drawings

Fig. 1 is the structural representation of the microcontroller single line detail programming interface arrangement in the embodiment of the utility model one；

Fig. 2 is synch command frame schematic diagram；

Fig. 3 is data frame or return data frame schematic diagram；

Fig. 4 is synch command frame schematic diagram；

Fig. 5 is forms data write-in schematic diagram；

Fig. 6 is that forms data write-in reads schematic diagram；

Fig. 7 is more data write-ins or reads schematic diagram；

Fig. 8 is the adjustment method overall flow schematic diagram in the utility model；

Fig. 9 is the schematic flow sheet for carrying out real-time query in Fig. 8 to chip running status.

Embodiment

The principle of the disclosure is described referring now to some example embodiments.It is appreciated that these embodiments are merely for saying It is bright and help it will be understood by those skilled in the art that with the purpose of the embodiment disclosure and describe, rather than suggest the model to the disclosure Any restrictions enclosed.Content of this disclosure described here can in a manner of described below outside various modes implement.

As described herein, term " comprising " and its various variants are construed as open-ended term, it means that " bag Include but be not limited to ".Term "based" is construed as " being based at least partially on ".Term " one embodiment " it is understood that For " at least one embodiment ".Term " another embodiment " can be with

Fig. 1 is the structural representation of the microcontroller single line detail programming interface arrangement in the embodiment of the utility model one, A kind of microcontroller single line detail programming interface arrangement in the present embodiment, including：Control chip and objective chip, the control It is used as debugging using an I/O pin D_IO between chip and the objective chip.As preferred in the present embodiment, the control Coremaking piece is connected by UART communications protocol with objective chip.As preferred in the present embodiment, power supply in the objective chip Pin VDD, VSS are connected with the control chip.

As shown in figure 1, also include in debugging enironment PC1, download debugging control machine 2, control chip 21, objective chip 3, under Debugging apparatus 31 is carried, specific debud mode, refer to Fig. 8 is the adjustment method overall flow schematic diagram in the utility model, tool Body includes the steps：

It is electric on step S1,

Step S2 completes self-test and initialization,

Step S3 inquires about objective chip,

Step S4 configures objective chip status inquiry command, reconfigures and is no more than three times,

Step S6 reads objective chip data,

Step S7 uploads visualization interface,

Step S8 monitors new querying command, if once running completion without step S9 is entered.

Above-mentioned querying command then carries out reviewing inquiry without endless loop, inquiry beyond the time.

In the adjustment method of the present embodiment, the UART communications protocol of compatibility standard, target can adapt to communication speed automatically, lead to Interrogate speed range 1.2Khz~1000Khz.Compared with prior art, method of the present utility model is less using pin, more saves Resource, and communication speed scope is wider, pin uses less, to communication clock without fixed demand.

Fig. 2 is refer to, above-mentioned querying command also includes：One synch command frame, the synch command frame are assisted for standard UART View, and configured according to following requirement：

START is configured to start bit,

BIT0 is configured to 0,

BIT1 is configured to high level, according to low level clock count, to obtain the logical of START and/or BIT0 Interrogate speed,

BIT3~BIT7 order and check bit is correctly identified according to the communication speed.

It is synch command frame in Fig. 3, is standard UART protocol, it is desirable to which START is position in fact, is often low level, and BIT0 will It is high level to ask and be configured to 0, BIT1 requirements, so by low level clock count, showing that START and BIT0 communication is fast Rate, after obtaining correct communication frequency, BIT3~BIT7 order, and check bit subsequently can be correctly identified, so ordered Can correctly it be performed.Because each synch command frame has synchronization mechanism, clock change does not interfere with next frame communication yet.

Fig. 2, Fig. 3 are refer to, above-mentioned querying command also includes：Data frame and/or return data frame,

Data frame and/or the return data frame is configured in after the synch command frame.

For data frame and return data frame, it is desirable to which the data frame is followed behind synch command frame, and communication speed is by command frame It is synchronized, therefore data frame can be communicated accurately.

Method in the present embodiment also includes：Multiple format frames, multiple format frames include：

Forms data writes frame：

{ synch command frame+data frame }

Forms data writes or read frame：

{ synch command frame+data frame+return data frame }

More data write-ins read frame：

{ synch command frame+multiple data frames }.

Specifically, refer to Fig. 4~Fig. 6 is conventional frame format, and Fig. 4 and Fig. 5 are entered by synch command frame BIT2 height Row is distinguished, and is then performed Fig. 5 if low level, can so be carried out the input of one group of data；If BIT2 is high level, perform Fig. 6 only to a data write-in and is read.

Specifically, it refer to Fig. 7：For multiple digital frame format, the order is special command, and first data frame is to follow-up number Indicated according to write-in or the length read, most one 8bit of heel CRC check frame, read write-in and pass through synch command frame BIT2 make a distinction, BIT2 be it is low be write-in, BIT2 is that height is then reading.

As preferred in the present embodiment, the communication speed scope of communication protocol is：1.2Khz~1000Khz.

As preferred in the present embodiment, the running environment of the PC is：Windowsxp, windows7 or windows10。

Fig. 9 is the schematic flow sheet for carrying out real-time query in Fig. 8 to chip running status, and method specifically includes：

Step S100 synch command frames, communication speed is detected,

The synch command frame is standard UART protocol, and is configured according to following requirement：

START is configured to start bit,

BIT0 is configured to 0,

BIT1 is configured to high level, according to low level clock count, to obtain the logical of START and/or BIT0 Interrogate speed,

BIT3~BIT7 order and check bit is correctly identified according to the communication speed.

Step S101 internal counters, communication speed is identified,

The communication speed scope of communication protocol is：1.2Khz~1000Khz.

Step S102 orders perform, and only partial order frame directly performs order,

Step S103 forms data frames,

Step S104 identifications are only written or write-in is read,

Step S105 completes data communication,

Forms data writes frame：{ synch command frame+data frame }, { synch command frame } refer to by internal recognition mechanism, only Input is needed to order.{ synch command frame+data frame+return data frame } then mainly passes through synch command frame BIT2 height Make a distinction, { synch command frame+data frame } is then performed if low level, can so carry out the input of one group of data；If BIT2 is high level, then performs { synch command frame+data frame+return data frame } only to a data write-in and read.

The more data frames of step S106,

The write-in of step S107 identification datas or reading,

Step S108 identification data length,

Step S109 completes data check and communication.

More data write-ins read frame：

{ synch command frame+multiple data frames }

{ synch command frame+multiple data frames }, is multiple digital frame format, and the order is special command, first data frame The length for writing or reading to follow-up data indicates, and most one 8bit of heel CRC check frame, reads and writes by same The BIT2 of step command frame makes a distinction, BIT2 be it is low be write-in, BIT2 is that height is then reading.

It should be appreciated that each several part of the present utility model can be realized with hardware, software, firmware or combinations thereof. In above-mentioned embodiment, what multiple steps or method can be performed in memory and by suitable instruction execution system with storage Software or firmware are realized.If, and in another embodiment, can be with known in this field for example, realized with hardware Any one of following technology or their combination realize：With the gate for realizing logic function to data-signal The discrete logic of circuit, the application specific integrated circuit with suitable combinational logic gate circuit, programmable gate array (PGA), Field programmable gate array (FPGA) etc..

In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show The description of example " or " some examples " etc. means specific features, structure, material or the spy for combining the embodiment or example description Point is contained at least one embodiment or example of the present utility model.In this manual, to the schematic table of above-mentioned term State and be not necessarily referring to identical embodiment or example.Moreover, specific features, structure, material or the feature of description can be Combined in an appropriate manner in any one or more embodiments or example.

In general, the various embodiments of the disclosure can be with hardware or special circuit, software, logic or its any combination Implement.Some aspects can be implemented with hardware, and some other aspect can be with firmware or software implementation, and the firmware or software can With by controller, microprocessor or other computing devices.Although the various aspects of the disclosure be shown and described as block diagram, Flow chart is represented using some other drawing, but it is understood that frame described herein, equipment, system, techniques or methods can With in a non limiting manner with hardware, software, firmware, special circuit or logic, common hardware or controller or other calculating Equipment or some combinations are implemented.

Although in addition, operation is described with particular order, this is understood not to require this generic operation with shown suitable Sequence is performed or performed with generic sequence, or requires that all shown operations are performed to realize expected result.In some feelings Under shape, multitask or parallel processing can be favourable.Similarly, begged for although the details of some specific implementations is superincumbent By comprising but these are not necessarily to be construed as any restrictions to the scope of the present disclosure, but the description of feature is only pin in To specific embodiment.Some features described in some embodiments of separation can also be held in combination in single embodiment OK.Mutually oppose, the various features described in single embodiment can also in various embodiments be implemented separately or to appoint The mode of what suitable sub-portfolio is implemented.

Claims (3)

1. a kind of microcontroller single line detail programming interface arrangement, including：Control chip and objective chip, it is characterised in that

It is used as debugging using an I/O pin D_IO between the control chip and the objective chip.

2. microcontroller single line detail programming interface arrangement according to claim 1, it is characterised in that the control chip It is connected by UART communications protocol with objective chip.

3. microcontroller single line detail programming interface arrangement according to claim 1, it is characterised in that the objective chip Middle power pin VDD, VSS are connected with the control chip.