CN113626274B - Interface for realizing hardware debugging and method for realizing debugging of microcontroller - Google Patents
Interface for realizing hardware debugging and method for realizing debugging of microcontroller Download PDFInfo
- Publication number
- CN113626274B CN113626274B CN202111178709.7A CN202111178709A CN113626274B CN 113626274 B CN113626274 B CN 113626274B CN 202111178709 A CN202111178709 A CN 202111178709A CN 113626274 B CN113626274 B CN 113626274B
- Authority
- CN
- China
- Prior art keywords
- debugging
- output
- input
- port
- debug
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
- G06F11/2733—Test interface between tester and unit under test
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only
- H03K19/01806—Interface arrangements
- H03K19/01818—Interface arrangements for integrated injection logic (I2L)
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- Quality & Reliability (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Abstract
The application provides an interface for realizing hardware debugging and a method for realizing debugging of a microcontroller, wherein the interface comprises the following steps: the input/output debugging port is used for connecting a debugging adapter; the output logic comprises an output drive and a buffer resistor, the GPIO output signal and the debugging output signal are connected with the input end of the output drive through a multiplexer, one end of the buffer resistor is connected with the output end of the output drive, and the other end of the buffer resistor is connected with an input/output debugging port; the input end of the input logic is connected with the input/output debugging port, and the output end of the input logic outputs a debugging input signal, a GPIO input signal or an analog input signal; and the debugging detection logic is connected with the output end of the input logic. In the application, no matter the interface is used as a common input/output port or the microcontroller is in the period of the power-on detection window, the debugging adapter can immediately enter the debugging state as long as the debugging adapter sends out a specific sequence, and power-on reset is not needed again.
Description
Technical Field
The present application relates to the field of integrated circuits, and more particularly, to a method for implementing hardware debug by using an interface and a microcontroller.
Background
In order to download the program code to the microcontroller and perform the debugging operation, a debugging adapter needs to be connected between the microcontroller and the PC. In order to reduce the number of ports of the microcontroller, especially in a small-package chip, a debugging interface of the microcontroller can be generally multiplexed into a common input/output port, and can be used as the common input/output port when debugging is not needed. Whether the debug port is used as a dedicated debug interface or a normal input/output port may be determined by the debug detect logic.
The debug detection logic is coupled to the input logic of the input/output debug port for detecting whether the input/output debug port receives a debug entry detection sequence. When the debugging port is used as a common input/output port or the microcontroller is in a window period of power-on detection, if the debugging port is to enter a debugging state, the debugging adapter sends out a specific time sequence signal, and if the debugging detection logic detects a debugging sequence, the input/output debugging port is configured as a special debugging interface to carry out programming debugging.
However, when the debug port is used as a general input/output port or the microcontroller is in a window of power-on detection, the debug adapter sends out a specific sequence, and when a chip is to be debugged, a level conflict may occur between an output level signal of the debug adapter and an output level of the general input/output port inside the chip, the level of the debug port cannot be determined, the debug detection logic cannot accurately detect a signal sent by the debug adapter, the error rate is high, power-on reset of the chip is required when the debug mode is entered, and time is wasted when power-on reset is performed again. Meanwhile, the unstable level of the debugging port can cause large current and the circuit has the risk of short circuit.
At present, no solution to this problem exists, and therefore, the present invention provides a method for implementing a hardware debug interface to solve this problem.
Disclosure of Invention
The purpose of the present application is to provide an interface for implementing hardware debugging, wherein no matter a chip port is used as a common input/output port or a microcontroller is in a power-on detection window period, as long as a debugging adapter sends a specific sequence, the chip can be immediately switched to a debugging state without power-on reset again.
An embodiment of the present application discloses an interface for implementing hardware debugging, including:
the input/output debugging port is used for connecting a debugging adapter;
the output logic comprises an output driver and a buffer resistor, a GPIO output signal and a debugging output signal are connected with the input end of the output driver through a multiplexer, one end of the buffer resistor is connected with the output end of the output driver, and the other end of the buffer resistor is connected with the input/output debugging port;
the input end of the input logic is connected with the input/output debugging port, and the output end of the input logic outputs a debugging input signal, a GPIO input signal or an analog input signal;
and the debugging detection logic is connected with the output end of the input logic.
In a preferred embodiment, the output driver includes a PMOS transistor and an NMOS transistor, the gates of the PMOS transistor and the NMOS transistor are connected to the output terminal of the multiplexer, the source of the PMOS transistor is connected to a power supply terminal, the drain of the PMOS transistor is connected to the drain of the NMOS transistor and to one end of the buffer resistor, the source of the NMOS transistor is connected to a ground terminal, and the other end of the buffer resistor is connected to the input/output debug port.
In a preferred embodiment, the input logic includes a resistor, a flip-flop, a first switch and a second switch, one end of the resistor is connected to a power supply terminal via the first switch, the other end of the resistor is connected to an input terminal of the flip-flop and to a ground terminal via the second switch, and outputs an analog input signal, an output terminal of the flip-flop is connected to the debug detection logic, and an output terminal of the flip-flop outputs a debug input signal or a GPIO input signal.
In a preferred embodiment, the resistance value of the buffer resistor ranges from 100 ohms to 5000 ohms.
An embodiment of the present application discloses a method for implementing debugging of a microcontroller, which employs the foregoing interface for implementing hardware debugging, and the method includes:
the debugging adapter sends out a specific timing sequence signal;
the debugging detection logic receives the specific time sequence signal, and the input/output debugging port is used as a debugging port, wherein when the level output by the debugging adapter is different from the level output by the output drive in the process of receiving the specific time sequence signal, the debugging detection logic is coupled through the buffer resistor, and the level of the input/output debugging port is the level output by the debugging adapter;
the level received by the debugging detection logic is the level output by the debugging adapter, and the microcontroller carries out debugging state.
In a preferred embodiment, before the debug adapter sends out the specific timing signal, the input/output debug port is used as a normal input/output port, or the microcontroller is in a power-on detection phase.
In a preferred embodiment, when the debug adapter outputs a low level and the output drives to output a high level, the input/output debug port is at a low level through the buffer resistor coupling.
In a preferred embodiment, when the debug adapter outputs a high level and the output drives an output low level, the input/output debug port is at a high level through the buffer resistor coupling.
In one embodiment, the present application discloses a microcontroller including one or more of the aforementioned interfaces for implementing hardware debugging.
Compared with the prior art, the method has the following beneficial effects:
the method and the device can ensure that the voltage of the debugging port is stable, ensure the accuracy of detecting the signal sent by the debugging adapter by the debugging detection logic, and ensure that the chip can be immediately switched to a debugging state without power-on reset as long as the debugging adapter sends a specific sequence no matter when the chip port is used as a common input/output port or when the microcontroller is in a window of power-on detection.
Drawings
Fig. 1 is a schematic diagram of an interface for implementing hardware debugging in an embodiment of the present application.
Fig. 2 is a schematic diagram illustrating a state of an interface level when an output driver outputs a low level and a debug adapter outputs a low level according to an embodiment of the present application.
Fig. 3 is a schematic diagram illustrating a state of an interface level when an output driver outputs a high level and a debug adapter outputs a high level according to an embodiment of the present application.
Fig. 4 is a schematic diagram illustrating a state of an interface level when an output driver outputs a high level and a debug adapter outputs a low level according to an embodiment of the present application.
Fig. 5 is a schematic diagram illustrating a state of an interface level when an output driver outputs a low level and a debug adapter outputs a high level according to an embodiment of the present application.
Detailed Description
In the following description, numerous technical details are set forth in order to provide a better understanding of the present application. However, it will be understood by those skilled in the art that the technical solutions claimed in the present application may be implemented without these technical details and with various changes and modifications based on the following embodiments.
To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
Fig. 1 shows a schematic diagram of an interface for implementing hardware debugging, and the interface is used as a part of the microcontroller 100, and can be used as a general input/output port, and can also be used for implementing hardware debugging of the microcontroller 100. It should be understood that the term "interface" as used in this embodiment may also be referred to as a "port", "pin" or "pin", etc., which may represent the same feature.
The interface includes: input/output debug port 101, output logic 102, input logic 103, and debug detect logic 104. The input/output debug port 101 is used to connect the debug adapter 201. The output logic 102 includes an output driver 106 and a buffer resistor R1, the GPIO output signal and the debug output signal are connected to the input terminal of the output driver 106 through the multiplexer 105, one end of the buffer resistor R1 is connected to the output terminal of the output driver 106, and the other end of the buffer resistor R1 is connected to the input/output debug port 101. The input end of the input logic 103 is connected to the input/output debug port 101, and the output end outputs a debug input signal, a GPIO input signal or an analog input signal. Debug detect logic 104 is coupled to an output of input logic 103.
In one embodiment, the output driver 106 comprises a PMOS transistor P1 and an NMOS transistor N1, the gate of the PMOS transistor P1 and the gate of the NMOS transistor N1 are connected to the output terminal of the multiplexer 105, the source of the PMOS transistor P1 is connected to the power supply terminal VCC, the drain of the PMOS transistor P1 is connected to the drain of the NMOS transistor N1 and to one end of the buffer resistor R1, the source of the NMOS transistor N1 is connected to the ground terminal GND, and the other end of the buffer resistor R1 is connected to the input/output debug port 101.
In one embodiment, the input logic 103 comprises a resistor R, a flip-flop U1, a first switch SW1 and a second switch SW2, one end of the resistor R is connected to the power supply terminal VCC via the first switch SW1, the other end is connected to the input terminal of the flip-flop U1 and to the ground terminal GND via the second switch SW2, and an analog input signal is output, the output terminal of the flip-flop U1 is connected to the debug detection logic 104, and the output terminal of the flip-flop outputs the debug input signal or the GPIO input signal.
In one embodiment, the buffer resistor R1 has a resistance range of 100 ohms to 5000 ohms, for example, 500 ohms, 1000 ohms, 2000 ohms, 4000 ohms, etc., and the magnitude of the resistance of the buffer resistor R1 determines the output driving capability of the port.
When there is a signal output, the output signal of output driver 106 is coupled to debug port 101 through resistor R1. When a signal is input, the debug port 101 is connected to the internal circuit of the integrated circuit through input logic.
In the application, the debugging detection logic can accurately detect the specific sequence signal sent by the debugging adapter, and the port can be immediately switched to the debugging function as long as the debugging adapter sends the debugging specific sequence signal no matter when the chip port is used as a common input/output port or the microcontroller is in a power-on detection window period. In the embodiment, only one buffer resistor needs to be connected in series, so that the cost is not high, and the method is simple and easy to implement. In addition, the level of the debugging port is stable, so that the circuit can be protected, and the condition of overlarge current or short circuit cannot occur.
In an embodiment of the present application, a method for implementing debugging of a microcontroller is provided, where an interface for implementing hardware debugging shown in fig. 1 is used, and the method includes:
in step S1, the debug adapter 201 issues a specific timing signal. In one embodiment, before debug adapter 201 issues a particular timing signal, I/O debug port 101 is either acting as a normal I/O port, or microcontroller 100 is in a power-up detection phase (i.e., initial startup phase).
In step S2, the debug detection logic 104 receives the specific timing signal, and the input/output debug port 101 is used as a debug port, wherein when the level output by the debug adapter 201 is different from the level output by the output driver 106 during the process of receiving the specific timing signal by the debug detection logic 104, the level output by the input/output debug port 101 is coupled through the buffer resistor R1, and the level output by the debug adapter 201 is the level output by the input/output debug port 101.
In one embodiment, when the debug adapter 201 outputs a low and the output driver 106 outputs a high, the input/output debug port 101 is low coupled through the buffer resistor R1.
In one embodiment, when the debug adapter 201 outputs a high and the output driver 106 outputs a low, the input/output debug port 101 is coupled high through the buffer resistor R1.
In step S3, after the above steps, the level received by the debug detection logic 104 is the level output by the debug adapter 201, and the microcontroller 100 performs the debug state.
Therefore, no matter the voltage of the chip internal output driving output and the voltage of the debugging adapter output, the voltages on the two sides of the input/output debugging port can not generate voltage conflict. When the input/output debugging port is used as a common input/output port or the microcontroller is in a power-on detection window period, the debugging detection logic can accurately detect a specific time sequence signal sent by the debugging adapter, and the chip can immediately enter a debugging state without performing power-on reset operation on the chip.
In addition, the voltage of the input/output debugging port is stable, and meanwhile, the input/output debugging port can play a role of protecting a circuit, and the circuit is prevented from being short-circuited.
In order to better understand the technical solution of the present application, the following description takes the interfaces of fig. 2 to 5 when the output driver and the debug adapter output different levels as examples, and the listed details in the examples are mainly for easy understanding and are not intended to limit the scope of the present application.
Referring to FIG. 2, when the output voltage U1 of the chip debug port internal (i.e., output logic) output driver 106 is low, the output voltage signal U3 of the debug adapter 201 is low. No voltage difference exists between U1 and U3, the output voltage U2 of the output logic is low, the voltage Ur1 of the buffer resistor R1, i.e., U12, is approximately equal to 0, and the voltage Uio of the input/output debug port 101 is low. The voltage U4 detected by the debug detect logic 104 is a U3 low signal issued by the debug adapter 201.
Referring to fig. 3, when the output voltage U1 of the chip debug port internal output driver 106 is high, the output voltage signal U3 of the debug adapter 201 is high. There is no voltage difference between U1 and U3, the output voltage U2 of the output logic is high, the voltage Ur1 of the buffer resistor R1, i.e., U12, is approximately equal to 0, and the voltage Uio of the input/output debug port 101 is high. The voltage U4 detected by the debug detect logic 104 is a U3 high signal issued by the debug adapter 201.
Referring to FIG. 4, when the output voltage U1 of the on-chip debug port internal output driver 106 is high and the output voltage signal U3 of the debug adapter 201 is low. A voltage difference exists between U1 and U3, and after the voltage difference is coupled through a buffer resistor R1, the output voltage U2 of the output logic is low, | Ur1| = | U12| = U1-U2, and the input/output debug port 101 voltage Uio is low. The voltage U4 detected by the debug detect logic 104 is a U3 low signal issued by the debug adapter 201.
Referring to FIG. 5, when the output voltage U1 of the on-chip debug port internal output driver 106 is low and the output voltage signal U3 of the debug adapter 201 is high. A voltage difference exists between U1 and U3, and after the output voltage U2 of the output logic is high voltage, | Ur1| = | U12| = U2-U1 after the output logic is coupled through the buffer resistor R1, and the input/output debug port 101 voltage Uio is high level. The voltage U4 detected by the debug detect logic 104 is a U3 high signal issued by the debug adapter 201.
As can be seen from the above, no matter what the output voltage of the internal output driver of the chip and the output voltage of the debug adapter are, no voltage conflict occurs between the voltages at the two sides of the debug port. When the port is used as a common input/output port or the microcontroller is in a window period of power-on detection, the debugging detection logic can accurately detect a specific time sequence signal sent by the debugging adapter, and the chip can immediately enter a debugging state without performing power-on reset operation on the chip.
With continued reference to fig. 1, an embodiment of the present application further provides a microcontroller 100, including one or more interfaces for implementing hardware debugging, each interface including: input/output debug port 101, output logic 102, input logic 103, and debug detect logic 104. The input/output debug port 101 is used to connect the debug adapter 201. The output logic 102 includes an output driver 106 and a buffer resistor R1, the GPIO output signal and the debug output signal are connected to the input terminal of the output driver 106 through the multiplexer 105, one end of the buffer resistor R1 is connected to the output terminal of the output driver 106, and the other end of the buffer resistor R1 is connected to the input/output debug port 101. The input end of the input logic 103 is connected to the input/output debug port 101, and the output end outputs a debug input signal, a GPIO input signal or an analog input signal. Debug detect logic 104 is coupled to an output of input logic 103.
It is noted that, in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the use of the verb "comprise a" to define an element does not exclude the presence of another, same element in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that a certain action is executed according to a certain element, it means that the action is executed according to at least the element, and two cases are included: performing the action based only on the element, and performing the action based on the element and other elements. The expression of a plurality of, a plurality of and the like includes 2, 2 and more than 2, more than 2 and more than 2.
All documents mentioned in this specification are to be considered as being incorporated in their entirety into the disclosure of this specification so as to be subject to modification as necessary. It should be understood that the above description is only a preferred embodiment of the present disclosure, and is not intended to limit the scope of the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of one or more embodiments of the present disclosure should be included in the scope of protection of one or more embodiments of the present disclosure.
Claims (9)
1. An interface for implementing hardware debugging, comprising:
the input/output debugging port is used for connecting a debugging adapter;
the output logic circuit comprises an output driving circuit and a buffer resistor, a GPIO output signal and a debugging output signal are connected with the input end of the output driving circuit through a multiplexer, one end of the buffer resistor is connected with the output end of the output driving circuit, and the other end of the buffer resistor is connected with the input/output debugging port;
the input end of the input logic circuit is connected with the input/output debugging port, and the output end of the input logic circuit outputs a debugging input signal, a GPIO input signal or an analog input signal;
and the debugging detection logic circuit is connected with the output end of the input logic circuit.
2. The interface according to claim 1, wherein the output driver circuit comprises a PMOS transistor and an NMOS transistor, a gate of the PMOS transistor and a gate of the NMOS transistor are connected to the output terminal of the multiplexer, a source of the PMOS transistor is connected to a power supply terminal, a drain of the PMOS transistor is connected to a drain of the NMOS transistor and to one end of the buffer resistor, a source of the NMOS transistor is connected to a ground terminal, and another end of the buffer resistor is connected to the input/output debug port.
3. The interface of claim 1, wherein the input logic circuit comprises a resistor, a flip-flop, a first switch and a second switch, one end of the resistor is connected to a power supply terminal via the first switch, the other end of the resistor is connected to an input terminal of the flip-flop and to a ground terminal via the second switch, and outputs an analog input signal, an output terminal of the flip-flop is connected to the debug detection logic circuit, and an output terminal of the flip-flop outputs a debug input signal or a GPIO input signal.
4. The interface for realizing hardware debugging of claim 1, wherein the buffer resistor has a resistance value ranging from 100 ohms to 5000 ohms.
5. A method for debugging a microcontroller, wherein the interface for hardware debugging in any one of claims 1-4 is used, the method comprising:
the debugging adapter sends out a specific timing sequence signal;
the debugging detection logic circuit receives the specific time sequence signal, and the input/output debugging port is used as a debugging port, wherein when the level output by the debugging adapter is different from the level output by the output driving circuit in the process of receiving the specific time sequence signal, the debugging detection logic circuit is coupled through the buffer resistor, and the level of the input/output debugging port is the level output by the debugging adapter;
the level received by the debugging detection logic circuit is the level output by the debugging adapter, and the microcontroller enters a debugging state.
6. The method for debugging of claim 5, wherein before the debugging adapter sends out the specific timing signal, the I/O debugging port is used as a normal I/O port, or the microcontroller is in a power-on detection phase.
7. The method for realizing debugging of claim 5, wherein when the debugging adapter outputs a low level and the output driving circuit outputs a high level, the input/output debugging port is at a low level through the buffer resistor coupling.
8. The method for realizing debugging of claim 5, wherein when the debugging adapter outputs a high level and the output driving circuit outputs a low level, the input/output debugging port is at a high level through the buffer resistor coupling.
9. Microcontroller characterized in that it comprises one or more interfaces enabling hardware debugging according to any one of claims 1-4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111178709.7A CN113626274B (en) | 2021-10-11 | 2021-10-11 | Interface for realizing hardware debugging and method for realizing debugging of microcontroller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111178709.7A CN113626274B (en) | 2021-10-11 | 2021-10-11 | Interface for realizing hardware debugging and method for realizing debugging of microcontroller |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113626274A CN113626274A (en) | 2021-11-09 |
| CN113626274B true CN113626274B (en) | 2022-01-04 |
Family
ID=78390977
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111178709.7A Active CN113626274B (en) | 2021-10-11 | 2021-10-11 | Interface for realizing hardware debugging and method for realizing debugging of microcontroller |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113626274B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116820015B (en) * | 2023-08-29 | 2023-11-17 | 灵动集成电路南京有限公司 | Microcontroller with flexible configurable logic module |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7216276B1 (en) * | 2003-02-27 | 2007-05-08 | Marvell International Ltd. | Apparatus and method for testing and debugging an integrated circuit |
| CN101154207A (en) * | 2006-09-29 | 2008-04-02 | 上海海尔集成电路有限公司 | Operating method for configured interface of microcontroller |
| CN101191819A (en) * | 2006-11-21 | 2008-06-04 | 国际商业机器公司 | FPGAFPGA, FPGA configuration, debug system and method |
| CN205594621U (en) * | 2016-04-22 | 2016-09-21 | 深圳市博巨兴实业发展有限公司 | A debugging for microcontroller |
| CN207115115U (en) * | 2017-08-18 | 2018-03-16 | 上海爱矽半导体科技有限公司 | A kind of microcontroller single line detail programming interface arrangement |
| CN110058541A (en) * | 2018-01-18 | 2019-07-26 | 英飞凌科技奥地利有限公司 | Micro controller system with debugger in circuit |
-
2021
- 2021-10-11 CN CN202111178709.7A patent/CN113626274B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7216276B1 (en) * | 2003-02-27 | 2007-05-08 | Marvell International Ltd. | Apparatus and method for testing and debugging an integrated circuit |
| CN101154207A (en) * | 2006-09-29 | 2008-04-02 | 上海海尔集成电路有限公司 | Operating method for configured interface of microcontroller |
| CN101191819A (en) * | 2006-11-21 | 2008-06-04 | 国际商业机器公司 | FPGAFPGA, FPGA configuration, debug system and method |
| CN205594621U (en) * | 2016-04-22 | 2016-09-21 | 深圳市博巨兴实业发展有限公司 | A debugging for microcontroller |
| CN207115115U (en) * | 2017-08-18 | 2018-03-16 | 上海爱矽半导体科技有限公司 | A kind of microcontroller single line detail programming interface arrangement |
| CN110058541A (en) * | 2018-01-18 | 2019-07-26 | 英飞凌科技奥地利有限公司 | Micro controller system with debugger in circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113626274A (en) | 2021-11-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8656220B2 (en) | System-on-chip and debugging method thereof | |
| EP0717341A1 (en) | Power enabling apparatus and method | |
| US8166222B2 (en) | USB transceiver circuitry including 5 volt tolerance protection | |
| US9476937B2 (en) | Debug circuit for an integrated circuit | |
| US20060015670A1 (en) | Apparatus for detecting connection of a peripheral unit to a host system | |
| US6813672B1 (en) | EMC enhancement for differential devices | |
| CN113626274B (en) | Interface for realizing hardware debugging and method for realizing debugging of microcontroller | |
| CN113168392A (en) | Signal loss detection circuit | |
| CN107210296B (en) | Self-sensing reverse current protection switch | |
| CN111130516A (en) | Switching circuit with high voltage protection with reduced leakage current | |
| US8049475B2 (en) | 5 volt tolerant voltage regulator | |
| CN113341780B (en) | Mode selection circuit for low cost integrated circuits such as microcontrollers | |
| KR100205847B1 (en) | Information processing apparatus with a mode setting circuit | |
| CN108091061B (en) | IC card detection circuit for metering device | |
| CN112363966B (en) | Serial port conversion circuit, base station, circuit conversion method, and computer storage medium | |
| US11163348B2 (en) | Connectors that connect a storage device and power supply control device, and related power supply control devices and host interface devices | |
| US11994888B2 (en) | Power supply handling for multiple package configurations | |
| EP3211508A1 (en) | Semiconductor device | |
| US9652011B2 (en) | Systems and methods for storing information | |
| US12124309B2 (en) | Fault detection during entry to or exit from low power mode | |
| CN116540146B (en) | GPIO short circuit detection method and GPIO short circuit detection system | |
| CN111142916B (en) | Configuration device and method of flash memory | |
| CN220121165U (en) | Control circuit, device and chip | |
| JP5738724B2 (en) | Trimming circuit, system, determination program, confirmation method, and determination method | |
| US20240160265A1 (en) | Fault detection during entry to or exit from low power mode |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |