CN114089157A - Chip testing method and system - Google Patents
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- CN114089157A CN114089157A CN202111287314.0A CN202111287314A CN114089157A CN 114089157 A CN114089157 A CN 114089157A CN 202111287314 A CN202111287314 A CN 202111287314A CN 114089157 A CN114089157 A CN 114089157A
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- G01R31/2851—Testing of integrated circuits [IC]
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Abstract
The application relates to a chip testing method and system. A chip test system is provided, the chip test system includes a tester and a chip to be tested, wherein the chip to be tested includes: a VDD pin through which the chip to be tested receives a power supply signal from the tester and generates an internal reset signal of the chip to be tested based on the received power supply signal to reset the chip to be tested; the chip to be tested is in single-wire communication with the tester through the SWD pin in a test mode; and a single wire OWM module configured to monitor the SWD pin within a predetermined time after the chip under test is reset to determine whether the chip under test enters the test mode, and in response to the chip under test entering the test mode, program the trim bits using programming bit data received from the tester based on single wire communication between the SWD pin and the tester.
Description
Technical Field
The present disclosure relates to the field of integrated circuits, and more particularly, to a method and system for testing a chip.
Background
One chip usually needs to place some trim bits (trim bits) during design, and the purpose of these trim bits is to calibrate analog circuits during the ATE test of the chip, such as calibration of Bandgap/Vref/ROSC; on the other hand, in order to provide some customized options, the internal functions are set, and certain flexibility is realized. The traditional trim approach is to use several electrical test points (Probe PADs) to program a one-time programmable (OTP) memory in the chip to achieve the selection of a logic 0 or 1. Probe PAD increases the chip area, resulting in increased chip cost.
Disclosure of Invention
In order to solve the above problem, the present application provides a single-wire test mechanism, which can implement programming of trim bits inside a chip without adding additional Probe PAD by multiplexing functions of chip pins.
Specifically, according to an embodiment of the present application, a chip testing system is provided, where the chip testing system includes a tester and a chip to be tested, where the chip to be tested includes: a VDD pin through which the chip to be tested receives a power supply signal from the tester and generates an internal reset signal of the chip to be tested based on the received power supply signal to reset the chip to be tested; the chip to be tested is in single-wire communication with the tester through the SWD pin in a test mode; and a single wire OWM module configured to monitor the SWD pin within a predetermined time after the chip under test is reset to determine whether the chip under test enters the test mode, and in response to the chip under test entering the test mode, program the trim bits using programming bit data received from the tester based on single wire communication between the SWD pin and the tester.
According to another embodiment of the present application, there is provided a chip testing method including the steps of: receiving a power supply signal from a tester through a VDD pin in a chip to be tested and generating an internal reset signal of the chip to be tested based on the received power supply signal to reset the chip to be tested; monitoring, by a single-wire OWM module in the chip to be tested, an SWD pin of the chip to be tested within a predetermined time after the chip to be tested is reset to determine whether the chip to be tested enters a test mode, and in response to the chip to be tested entering the test mode, programming the trim bit using programming bit data received from the tester based on single-wire communication between the SWD pin and the tester.
According to yet another embodiment of the present application, there is provided a computer readable storage medium having stored thereon program instructions that, when executed by a processor, cause the processor to perform the method of: receiving a power supply signal from a tester through a VDD pin in a chip to be tested and generating an internal reset signal of the chip to be tested based on the received power supply signal to reset the chip to be tested; monitoring, by a single-wire OWM module in the chip to be tested, an SWD pin of the chip to be tested within a predetermined time after the chip to be tested is reset to determine whether the chip to be tested enters a test mode, and in response to the chip to be tested entering the test mode, programming the trim bit using programming bit data received from the tester based on single-wire communication between the SWD pin and the tester.
Depending on the embodiment, one or more effects may be achieved. These advantages, various additional objects, features, and benefits of the present application will be more fully understood with reference to the detailed description and accompanying drawings that follow.
Drawings
FIG. 1 is a schematic diagram illustrating a single wire test system according to the present application;
FIG. 2 illustrates functional modules of a chip under test according to the present application;
FIG. 3 is a flow chart illustrating detecting whether a chip enters a test mode according to the present application;
FIG. 4 is a timing diagram illustrating detecting whether a chip enters a test mode according to the present application;
FIG. 5 shows an example of a bit period of bit data according to the present application;
fig. 6 shows an example of a signal waveform representing bit data as 1 according to the present application;
fig. 7 shows an example of a signal waveform representing bit data of 0 according to the present application;
fig. 8 shows an example of a waveform of a test start signal issued by the tester;
fig. 9 shows an example of a waveform of a test stop signal issued by the tester;
fig. 10 shows an example of a data transmission format for the test method of the present application; and
FIG. 11 is a flow chart illustrating a testing method according to the present application.
Detailed Description
Features and exemplary embodiments of various aspects of the present application will be described in detail below. The following description encompasses numerous specific details in order to provide a thorough understanding of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a clearer understanding of the technical solutions of the present application by illustrating examples of the present application. The present application is in no way limited to any specific configuration set forth below, but rather covers any modifications, alterations, and improvements in the relevant features, structures, operations, etc., without departing from the spirit of the application.
FIG. 1 is a schematic diagram illustrating a single wire test system according to the present application. As shown in fig. 1, SWD is a test multiplexing pin of a chip to be tested, and is used for performing single-wire communication with a tester during testing; VDD is the power pin of the chip under test through which the tester supplies power to the chip under test.
Fig. 2 shows a chip functional module under test according to the present application. As shown in FIG. 2, the chip contains basic analog circuits such as Bandgap/LDO/VREF/ROSC, which are calibrated by trim bits. A power-on reset (POR) module in the chip generates an internal reset signal reset of the chip; the ROSC is an RC oscillator that generates the internal operating clock signal clk for the chip. The Trim bit module is a one-time programmable memory, i.e., OTP, that stores configuration parameters. The Normal Function module is responsible for operating the main Function logic of the chip to be tested; the One-Wire-Module (OWM) is used for programming trim bits inside the chip to be tested in the test mode. The chip can work in two states of a Normal Mode (Normal Mode) and a Test Mode (Test Mode). In the common mode, the SWD is a common functional pin, and the function of the SWD is defined according to the actual requirement of a chip; in test mode, the SWD is multiplexed into a test pin.
Fig. 3 shows a flow of detecting whether a chip enters a test mode and fig. 4 shows a timing chart of detecting whether a chip enters a test mode. As shown in fig. 3, after the chip is powered on, the internal POR module releases the reset signal to reset the chip to be tested; t of OWM module after reset of chip to be testedwaitAnd monitoring the SWD pin in time to determine whether the chip to be tested enters a test mode. Specifically, if the OWM module monitors that a predetermined mode (pattern) occurs on the SWD pin, the chip to be tested enters a test mode, so that a single-wire communication function is started to communicate with the tester, otherwise, the chip to be tested is at TwaitAfter which time the normal operation mode is entered. According to one embodiment of the present application, TwaitThe value may be set to 4ms-200ms, for example.
The tester controls the power-on time sequence of the chip to be tested, and the power-on time sequence is TwaitThe test entry mode (which may be a set of special waveforms) is sent continuously during this period to ensure that the chip under test can enter the test mode, as shown in fig. 4.
The test method according to the present application will be described in detail below with reference to fig. 5 to 10.
After the chip is powered on and reset, the OWM module starts the single-wire communication function of the SWD after detecting that the SWD pin has a preset mode (namely, a test entering mode). It should be noted here that since the ROSC inside the chip to be tested has not yet passed through trim, a large error, typically 30% -50%, occurs between the initial frequency and the design frequency. Therefore, it is necessary to design a communication method which is not sensitive to the clock frequency deviation inside the chip. For this purpose, the present application presets a Unit Time (TU), which may be equal to, for example, one ideal clock cycle of the internal ROSC of the chip.
The bit period of the bit data received from the tester through the SWD pin is set to, for example, 40TU according to the set unit time, as shown in fig. 5. The tester strictly transmits each bit of data according to the high-low level duty ratio of 30TU/10TU or 10TU/30 TU. It should be noted here that although the bit period is set to 40TU in the present application, other lengths of bit periods may be set according to specific needs. In addition, although the application shows that the tester sends each bit of data according to the high-low level duty ratio of 30TU/10TU or 10TU/30TU, other duty ratios can be set according to specific needs.
And the receiving logic of the OWM module of the chip to be tested counts the high-low level width between two continuous rising edges of each bit of data received, and the count values are CntHigh and CntLow respectively. If the count value of the high level is greater than the count of the low level, that is, cnthhigh > CntLow, it is determined that the received bit data is 1, as shown in fig. 6; otherwise, the received bit data is determined to be 0, as shown in fig. 7. In other words, since the internal ROSC frequency of the chip to be tested has a deviation, the OWM module does not need to determine whether the bit data is 1 or 0 according to the absolute length of the width of the high and low levels of the bit data, but determines according to the relative magnitude of the high and low levels of the bit data.
After the chip under test enters the test mode, the tester sends a test start signal to the chip under test by pulling down the SWD pin of the chip under test (i.e., SWD ═ 0) and holding for a time greater than a predetermined number of unit times (such as 160 TU). The OWM module of the chip under test detects the level of the SWD pin, counts the SWD pin by using the internal clock of the chip under test within a time when the SWD is 0, and when the count value exceeds a predetermined threshold, for example, 60, the chip under test starts to prepare to receive a frame of data from the tester, as shown in fig. 8.
After the tester sends the programming bit data to the chip under test, it first sends a test stop signal to the chip under test by pulling up the level of the SWD pin (i.e., SWD ═ 1) and holding for a time greater than a predetermined number of unit times (e.g., 200 TU). The OWM module of the chip to be tested detects the level of the SWD pin, counts within a time when SWD is 1 by using the internal clock of the chip to be tested, and resets the primary communication logic when the count value exceeds a predetermined threshold, for example, 100, as shown in fig. 9.
Specifically, according to one embodiment of the present application, programming bit data may be transmitted to the chip under test using a data frame having a predetermined data transmission format to program an OTP (e.g., 64-bit OTP) inside the chip under test.
According to an embodiment of the application, the data frame having the predetermined data transmission format includes a header data segment for distinguishing a data frame type, an address data segment for indicating which position of the OTP is programmed, and a verification data segment for verifying the data frame to determine whether it is a correct programmed data frame.
FIG. 10 illustrates a data transmission format of a data frame sent by a tester for programming an OTP for a chip under test according to one embodiment of the application. As shown in fig. 10, the tester may send data frames having the data transmission format as shown:
Satrt_1010_B11B10B9B8B7B6_B5B4B3B2B1B0_Stop，
the data frame has 16 bits (i.e., Bn-B0, where n is 15), the first 4 bits of data 1010(B15-B12) are used as a frame header to distinguish the data frame type, the middle 6 bits of data (B11-B6) are OTP addresses indicating the locations of the OTP pointed by the bits of data to be programmed, and the last 6 bits of data (B5-B0) are inverses of the middle 6 bits of data (B11-B6).
In operation, the OWM module of the chip under test checks whether the first 4 bits of data of the data frame are 1010, and if not, ignores the data frame.
Further, the OWM module of the chip to be tested checks whether the middle 6-bit data and the last 6-bit data in the data frame, which represent the OTP address, satisfy an inversion relation, and if not, ignores the data frame.
Further, if the OWN module of the chip to be tested detects that the first 4 bits of data of the data frame are 1010 and the middle 6 bits of data representing the OTP address and the last 6 bits of data satisfy the inverse relationship, it starts to program the trim bits inside the chip to be tested in the test mode.
Although it is described in the present application that the OTP inside the chip to be tested is programmed by using the data frame of the predetermined data transmission format, it can be understood that other data transmission formats may be designed according to specific situations, for example, a data frame with more or less bits of data may be used according to actual situations, other header data may be set, and other verification methods are used to determine whether the data frame is the correct programmed data frame.
FIG. 11 shows a flow chart of a testing method according to the present application. As shown in fig. 11, the method includes: step S1102 of receiving a power supply signal from a tester through a VDD pin in a chip to be tested and generating an internal reset signal of the chip to be tested based on the received power supply signal to reset the chip to be tested; step S1104, monitoring the SWD pin of the chip to be tested within a predetermined time after the chip to be tested is reset through the single-wire OWM module in the chip to be tested to determine whether the chip to be tested enters a test mode; and step S1106, in response to the chip under test entering the test mode, programming the trim bits using programming bit data received from the tester based on the single wire communication between the SWD pin and the tester.
In some embodiments of the present application, the OWM module is configured to determine that the chip under test enters the test mode when it is monitored that a predetermined test entry mode occurs on the SWD pin within a predetermined time after the chip under test is reset.
In some embodiments of the present application, the OWM module is configured to determine whether the programming bit data received from the tester is "1" or "0" based on counting high and low level widths between two consecutive rising edges of the programming bit data within a predetermined bit period.
In some embodiments of the present application, if a count value of a high level width between two consecutive rising edges of the programming bit data received from the tester within the predetermined bit period is greater than a count value of a low level width, the programming bit data is determined to be "1", and conversely, the programming bit data is determined to be "0".
In some embodiments of the present application, the tester sends a test start signal to the chip under test by setting the SWD pin to a low level for a first predetermined number of the bit periods, the chip under test counts a low level width of the SWD, and starts to prepare to receive programming bit data from the tester when the counted value of the low level width of the SWD is greater than a predetermined threshold value.
In some embodiments of the present application, the tester sends a test stop signal to the chip under test by setting the SWD pin to a high level for a second predetermined number of the bit periods, the chip under test counts a high level width of the SWD, and resets its communication logic when the count value of the high level width of the SWD is greater than a predetermined threshold.
In some embodiments of the present application, the tester sends the programming bit data to the chip to be tested using a data frame having a predetermined data transmission format, where the data frame having the predetermined data transmission format includes header data, address data, and verification data.
In some embodiments of the present application, the OWM module is configured to check whether the header data of the data frame received from the tester is predetermined header data, and if not, to ignore the data frame.
In some embodiments of the present application, the OWM module is configured to check whether the address data and the check data of the data frame received from the tester satisfy a predetermined relationship, and if not, to ignore the data frame.
While specific embodiments of the application have been described, those skilled in the art will appreciate that there are other embodiments of the application that are equivalent to the described embodiments. It is to be understood, therefore, that this application is not limited to the specifically illustrated embodiments, but only by the scope of the appended claims.
Claims (19)
1. A chip test system comprises a tester and a chip to be tested,
wherein, the chip that awaits measuring includes:
a VDD pin through which the chip to be tested receives a power supply signal from the tester and generates an internal reset signal of the chip to be tested based on the received power supply signal to reset the chip to be tested;
the chip to be tested is in single-wire communication with the tester through the SWD pin in a test mode; and
a single wire OWM module configured to monitor the SWD pin within a predetermined time after the chip under test is reset to determine whether the chip under test enters the test mode, and in response to the chip under test entering the test mode, program the trim bits using programming bit data received from the tester based on single wire communication between the SWD pin and the tester.
2. The test system of claim 2, wherein the OWM module is configured to determine that the chip under test enters the test mode when a predetermined test entry mode is monitored to occur on the SWD pin within a predetermined time after the chip under test is reset.
3. The test system of claim 2, wherein the OWM module is configured to determine whether the programming bit data is a "1" or a "0" based on counting high and low level widths between two consecutive rising edges of the programming bit data received from the tester within a predetermined bit period.
4. The test system of claim 3, wherein the program bit data is determined to be "1" if a count value of a high level width between consecutive two rising edges of the program bit data received from the tester within the predetermined bit period is greater than a count value of a low level width, and vice versa.
5. The test system of claim 1, wherein the tester sends a test start signal to the chip under test by setting the SWD pin to a low level for a first predetermined number of the bit periods, the chip under test counting a low level width of the SWD, and starts to prepare to receive programming bit data from the tester when the counted value of the low level width of the SWD is greater than a predetermined threshold value.
6. The test system of claim 1, wherein the tester sends a test stop signal to the chip under test by setting the SWD pin high for a second predetermined number of the bit periods, the chip under test counting a high-level width of the SWD and resetting its communication logic when the counted value of the high-level width of the SWD is greater than a predetermined threshold.
7. The test system of claim 1, wherein the tester sends programming bit data to the chip under test using a data frame having a predetermined data transmission format, the data frame having the predetermined data transmission format including header data, address data, and verification data.
8. The test system according to claim 7, wherein the OWM module is configured to check whether the header data of the data frame received from the tester is a predetermined header data, and if not, to ignore the data frame.
9. The test system of claim 7 wherein the OWM module is configured to check whether the address data and the check data of the data frame received from the tester satisfy a predetermined relationship, and if not, to ignore the data frame.
10. A chip testing method comprises the following steps:
receiving a power supply signal from a tester through a VDD pin in a chip to be tested and generating an internal reset signal of the chip to be tested based on the received power supply signal to reset the chip to be tested;
monitoring the SWD pin of the chip to be tested through the single-wire OWM module in the chip to be tested in a preset time after the chip to be tested is reset to determine whether the chip to be tested enters a test mode or not, and
in response to the chip under test entering the test mode, programming the trim bits using programming bit data received from the tester based on a single wire communication between the SWD pin and the tester.
11. The method of claim 10, wherein the OWM module is configured to determine that the chip under test enters the test mode when a predetermined test entry mode is monitored to occur on the SWD pin within a predetermined time after the chip under test is reset.
12. The method of claim 10, wherein the OWM module is configured to determine whether the programming bit data is "1" or "0" based on counting high and low level widths between two consecutive rising edges of the programming bit data received from the tester within a predetermined bit period.
13. The method of claim 12, wherein if a count value of a high level width between consecutive two rising edges of the program bit data received from the tester within the predetermined bit period is greater than a count value of a low level width, the program bit data is determined to be "1", and otherwise, the program bit data is determined to be "0".
14. The method of claim 10, wherein the tester sends a test start signal to the chip under test by setting the SWD pin to a low level for a first predetermined number of the bit periods, the chip under test counting a low level width of the SWD, and starts to prepare to receive programming bit data from the tester when the counted value of the low level width of the SWD is greater than a predetermined threshold value.
15. The method of claim 10, wherein the tester sends a test stop signal to the chip under test by setting the SWD pin high for a second predetermined number of the bit periods, the chip under test counting the high-level width of the SWD and resetting its communication logic when the count value of the high-level width of the SWD is greater than a predetermined threshold.
16. The method of claim 10, wherein the tester sends programming bit data to the chip under test using data frames having a predetermined data transmission format, the data frames having the predetermined data transmission format including header data, address data, and verification data.
17. The method of claim 16, wherein the OWM module is configured to check whether the header data of the data frame received from the tester is a predetermined header data, and if not, to ignore the data frame.
18. The method of claim 16, wherein said OWM module is configured to check whether said address data and said check data of said data frame received from said tester satisfy a predetermined relationship, and if not, to ignore such data frame.
19. A computer readable storage medium having stored thereon program instructions which, when executed by a processor, cause the processor to perform the method according to any one of claims 10-18.
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| CN117434428A (en) * | 2023-12-18 | 2024-01-23 | 杭州晶华微电子股份有限公司 | Chip calibration system, chip calibration mode entering method and chip |
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| CN207115115U (en) * | 2017-08-18 | 2018-03-16 | 上海爱矽半导体科技有限公司 | A kind of microcontroller single line detail programming interface arrangement |
| US20210156914A1 (en) * | 2018-09-28 | 2021-05-27 | Changxin Memory Technologies, Inc. | Test method and test system |
| CN111157872A (en) * | 2019-12-25 | 2020-05-15 | 上海亮牛半导体科技有限公司 | Method for multiplexing existing logic pin to enter test mode |
| CN111327333A (en) * | 2020-03-02 | 2020-06-23 | 无锡华润矽科微电子有限公司 | Decoding circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117434428A (en) * | 2023-12-18 | 2024-01-23 | 杭州晶华微电子股份有限公司 | Chip calibration system, chip calibration mode entering method and chip |
| CN117434428B (en) * | 2023-12-18 | 2024-03-26 | 杭州晶华微电子股份有限公司 | Chip calibration system, chip calibration mode entering method and chip |
Also Published As
| Publication number | Publication date |
|---|---|
| TW202319768A (en) | 2023-05-16 |
| CN114089157B (en) | 2024-04-12 |
| TWI787006B (en) | 2022-12-11 |
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