CN108766958A - A kind of integrated circuit layout structure convenient for chip testing - Google Patents
A kind of integrated circuit layout structure convenient for chip testing Download PDFInfo
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- CN108766958A CN108766958A CN201810979771.8A CN201810979771A CN108766958A CN 108766958 A CN108766958 A CN 108766958A CN 201810979771 A CN201810979771 A CN 201810979771A CN 108766958 A CN108766958 A CN 108766958A
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- 238000012360 testing method Methods 0.000 title claims abstract description 81
- 239000002184 metal Substances 0.000 claims abstract description 128
- 229910052751 metal Inorganic materials 0.000 claims abstract description 128
- 238000010884 ion-beam technique Methods 0.000 claims abstract description 24
- 238000002474 experimental method Methods 0.000 claims abstract description 21
- 238000005520 cutting process Methods 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 20
- 239000000523 sample Substances 0.000 description 11
- 238000013461 design Methods 0.000 description 8
- 238000012795 verification Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- 238000011161 development Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000010200 validation analysis Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000006698 induction Effects 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000001427 coherent effect Effects 0.000 description 1
- XPPKVPWEQAFLFU-UHFFFAOYSA-J diphosphate(4-) Chemical compound [O-]P([O-])(=O)OP([O-])([O-])=O XPPKVPWEQAFLFU-UHFFFAOYSA-J 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
Abstract
The present invention provides a kind of integrated circuit layout structure convenient for chip testing, include a metal connector 103, preset metal layer and preset top layer metallic layer for cutting, preset top layer metallic layer and preset metal interlevel have the metal contact wires that preset top layer metallic layer and preset metal layer is connected, and the metal contact wires include main signal line and the test signal line to be verified of preset quantity；Preset top layer metallic layer 105 where the test signal line to be verified is with one end of metal connector 103 and in the presence of physical contact, the other end of preset top layer metallic layer 101 where the main signal line and metal connector 103 with there is also physical contacts, for after focused ion beam cuts connection relation of the metal connector 103 to terminate test signal line A to be verified and the main signal line, then it is connected to by the experimental method of focused ion beam the preset top layer metallic layer where the specified new test signal line to be verified.
Description
Technical field
The present invention relates to a kind of semiconductor design and fabrication technology more particularly to a kind of integrated circuits convenient for chip testing
Domain structure.
Background technology
The period of development with integrated circuit technique and prosperity, design of integrated circuit complexity and production constantly contracts
It is short, the verification of chip design is required higher and higher.When chip layout designs, not only to consider to keep internal sensitive signal
Line mass is walked, the requirement of chip debug structure designs and later stage correcting is also considered emphatically, in the face for not increasing chip additionally
It is also cost-effective while product.The development of chip fabrication techniques, internal density of components is increasing, the complexity of connection
Higher and higher, a certain technical parameter of chip checking and the difficulty and cost of analyzing coherent signal when there is bug are also increasing.
With new verification technique method（Such as focused ion beam FIB (focused ion beam) experimental technique）Appearance, to domain
Wire structures also proposed new possibility.
In existing technological means, there are following methods：
（1）Additionally increase device on the basis of original circuit structure so that signal can be switched selection, but such method lacks
Point increases the circuit structure of redundancy, increases the area of chip, while also increasing the layout difficulty of domain；
（2）Probe domain structure is set on signal, but the method needs to carry out observation signal using tester table, increase test at
Sheet and additional probe chip area, while probe pressure also has the risk of damage chip.
Invention content
The present invention provides a kind of integrated circuit layout structure convenient for chip testing, as follows：
A kind of integrated circuit layout structure convenient for chip testing, including preset metal layer and preset top layer metallic layer, wherein pre-
It is the arbitrary gold in metal interconnecting layer in the integrated circuit layout structure other than preset top layer metallic layer to set metal layer
Belong to layer；There is the preset top layer metallic layer of conducting to be connect with the metal of preset metal layer for preset top layer metallic layer and preset metal interlevel
Line, the metal contact wires include main signal line and the test signal line to be verified of preset quantity；Wherein, where main signal line
The preset top layer metallic layer where the preset top layer metallic layer and the test signal line to be verified of preset quantity distinguishes position
In different location；The integrated circuit layout structure further includes a metal connector for cutting, wherein the metal connects
Body is the metal interconnecting layer for connecting conducting main signal and test signal to be verified；Where the test signal line to be verified
For preset top layer metallic layer with one end of the metal connector and in the presence of being physically contacted, the preset top layer where the main signal line is golden
Belong to the other end of layer and the metal connector with there is also physical contact, for focused ion beam cut the metal connector with
After the connection relation for terminating the test signal line to be verified and the main signal line, then the experimental method that passes through focused ion beam
The preset top layer metallic layer being connected to where the specified new test signal line to be verified.
Further, the track lengths of the metal connector are more than 3 microns, and it is adjacent with same metal interconnecting layer
Metal layer spacing be more than 2 microns；Wherein, the metal layer include preset top layer metallic layer where the main signal line and
Preset top layer metallic layer where the test signal line to be verified.
Further, the preset top layer metallic layer where the test signal line to be verified, for according to chip layout knot
Signal to be tested flow direction in structure, is snapped into preset where the main signal line using the experimental method of the focused ion beam
Top layer metallic layer.
Further, the preset top layer metallic layer where the main signal line, for being waited for according in chip layout structure
Test signal flows to, and the test signal line to be verified of specified one is connected to using the experimental method of the focused ion beam
The preset top layer metallic layer at place.
Further, further include through-hole, which is to realize the preset top layer metallic layer and the preset metal layer
Conducting and open up by the dielectric layer between the preset top layer metallic layer and the preset metal layer to be formed.
The invention has the advantages that using existing metal layer routes, need not increase based on probe signals verification processing
Domain module, to simplify circuit complexity；The embodiment of the present invention is to be cut, connected to metal interconnecting layer by FIB experiments
It handles, to change the position connection relation of reserved wiring top layer metallic layer, reaches and by changing mask plate flow again
Identical performance and effect.This technical solution, which modifies to chip, can reduce development cost, shorten the R&D cycle, may be used also
To be verified in advance to design modification, confirmatory experiment success rate is improved, debug experimental periods are shortened.
Description of the drawings
Fig. 1 is a kind of integrated circuit layout structure schematic diagram convenient for chip testing provided in an embodiment of the present invention；
Fig. 2 is the metal connector that provides of the embodiment of the present invention one by the integrated circuit layout structure after FIB technique cutting process
Schematic diagram；
Fig. 3 is that a kind of test signal line to be verified provided by Embodiment 2 of the present invention snaps into main signal by FIB technique processing
The integrated circuit layout structure schematic diagram of line；
Fig. 4 is that a kind of main signal line that the embodiment of the present invention three provides is connected to test signal to be verified by FIB technique processing
The integrated circuit layout structure schematic diagram of line.
Specific implementation mode
The embodiment of the present invention is designed to provide a kind of integrated circuit layout structure convenient for chip testing, is conducive to make
Cutting process is carried out to metal layer with focused ion beam FIB (focused ion beam) experimental technique, to realize quick core
Piece Circuit verification.
The specific embodiment of the invention is described in detail below in conjunction with specific embodiment：
As shown in Figure 1, the integrated circuit layout structure includes preset metal layer 110, preset metal layer 107, preset metal
Layer 111 and preset metal layer 102, aforementioned preset metal layer can be the top layer metallic layers or non-positioned at different metal interconnecting layers
Top layer metallic layer can also be the non-top layer metallic layer of same metal interconnecting layer, to be tested in the integrated circuit layout structure
Card test signal cabling is all located at aforementioned preset metal layer.The integrated circuit layout structure further includes preset top layer metallic layer
101, preset top layer metallic layer 109, preset top layer metallic layer 105 and preset top layer metallic layer 108, aforementioned preset top layer metallic layer
It can be the top layer metallic layer of the top layer metallic layer or same metal interconnecting layer positioned at different metal interconnecting layers.The pre- top set
There is the metal that the preset top layer metallic layer and the preset metal layer is connected to connect for layer metal layer and the preset metal interlevel
Wiring, the metal contact wires include main signal line and the test signal line to be verified of preset quantity, the institute where main signal line
That states the preset top layer metallic layer where preset top layer metallic layer and the test signal line to be verified of preset quantity puts position
Set difference.Have between preset metal layer 102 and preset top layer metallic layer 101 and preset metal layer 102 and preset top-level metallic is connected
The main signal line of layer 101 has between preset metal layer 107 and preset top layer metallic layer 105 and preset metal layer 107 and preset is connected
One test signal line to be verified of top layer metallic layer 105 has between preset metal layer 110 and preset top layer metallic layer 108 and leads
Another test signal line to be verified of logical preset metal layer 110 and preset top layer metallic layer 108, in addition, preset metal layer 111
A test to be verified with conducting preset metal layer 111 and preset top layer metallic layer 109 between preset top layer metallic layer 109
Signal wire.As shown in Figure 1, the integrated circuit layout structure further includes a metal connector 103 for cutting, metal connects
Junctor 103 is a kind of metal interconnecting layer for connecting conducting main signal line and test signal line to be verified.The survey to be verified
Preset top layer metallic layer 101 where trial signal line is with one end of metal connector 103 and in the presence of physical contact, the main signal
The other end of preset top layer metallic layer 101 where line and metal connector 103 with there is also physical contacts.It needs to illustrate
Be, as shown in Figure 1, the integrated circuit layout structure by the main signal line export test signal line A to be verified complete with
The test job of test signal line A to be verified on the preset metal layer 107 of the conducting connection of preset top layer metallic layer 105.Wherein
Signal corresponding to test signal line A to be verified is flowed into from preset metal layer 107.
Specifically, the track lengths of metal connector 103 are more than 3 microns, and it is adjacent with same metal interconnecting layer
The spacing of metal layer is more than 2 microns；Wherein, the metal layer includes the preset top layer metallic layer where the main signal line and institute
State the preset top layer metallic layer where test signal line to be verified.It is preset top layer metallic layer 101, preset top layer metallic layer 108, pre-
It sets spacing between top layer metallic layer 106 and preset top layer metallic layer 109 and is more than 2 microns, and is preset metal layer 102, pre-
The spacing between metal layer 107, preset metal layer 110 and preset metal layer 111 is set also greater than 2 microns.It needs to illustrate
It is, between the track lengths distance of the metal connector 103 or its metal layer adjacent with same metal interconnecting layer
Cannot be arranged away from, their distance values it is too small because the metal connector 103 track lengths apart from it is too small or its with
In the case that the spacing of adjacent metal layer is too small in same metal interconnecting layer, it is unfavorable for the method using focused ion beam to institute
State that the relevant metallization layer in integrated circuit layout structure cut and attended operation again damages main letter if operated by force
Number, it causes to test unstable, influences the function of integrated circuit.
As the embodiment of the present invention one, as shown in Fig. 2, where one end of metal connector 103 and the main signal line
There are physical connections for preset top layer metallic layer 101, in subsequent process flow operating process, for the letter to be tested of chip interior
Number test point change in location, by the experimental method cutting process metal connector 103 of focused ion beam to terminate the master
The connection of the preset top layer metallic layer 105 where preset top layer metallic layer 101 and test signal line A to be verified where signal wire
Conducting relationship, the experimental method stripping that then the preset top layer metallic layer 101 where the main signal line passes through focused ion beam
Surface to be measured（Region in circle）, metal interconnecting layer is exposed, then the Surface Creation exposed in preset top layer metallic layer 101
Intermediate connecting body D1 is connected to the surface to be measured of preset top layer metallic layer 108（Region in circle）It is focused the experiment of ion beam
Method is removed and exposed metal interconnecting layer so that the preset top layer metallic layer 101 where the main signal line and survey to be verified
Preset top layer metallic layer 108 where trial signal line B connects, to export test signal line to be verified by the main signal line
B completes the test work with the test signal line B to be verified on the preset metal layer 110 of the conducting connection of preset top layer metallic layer 108
Make.Signal corresponding to test signal line B wherein to be verified is flowed into from preset metal layer 110.It is used in compared with the existing technology
The mode of probe test chip signal passes through focused ion beam on the basis of keeping the integrated circuit layout structure constant
Experimental method the preset top layer metallic layer 101 where the main signal line is selectively connected to wait for described in specified one
Preset top layer metallic layer where validation test signal wire saves probe device to realize that the validation test of test point works
It introduces, saves time and the cost of verification.
As the embodiment of the present invention two, during carrying out the validation test of chip interior signal, the survey to be verified
Preset top layer metallic layer where trial signal line, it is described for being snapped into according to the signal to be tested flow direction in chip layout structure
Preset top layer metallic layer where main signal line then means to be not limited to cut-out metal connector 103, can also make additional
Test signal line to be verified snaps on the main signal line, as shown in figure 3, when preset where test signal line B to be verified
When top layer metallic layer 108 needs to export test by preset top layer metallic layer 101, in subsequent process flow, using described poly-
The experimental method of pyrophosphate ion beam removes the surface to be measured of preset top layer metallic layer 108 respectively（In 108 surface circle of top layer metallic layer
Region）With the surface to be measured of preset top layer metallic layer 101（Region in 101 surface circle of preset top layer metallic layer）And it is exposed
Go out metal interconnecting layer, is then connected to preset top layer in the Surface Creation intermediate connecting body D2 to be measured of preset top layer metallic layer 108
The surface to be measured of metal layer 101, to set up the connection relation of preset top layer metallic layer 108 and preset top layer metallic layer 101,
To maintain being inputted in the integrated circuit layout structure to induction signal for test signal line B to be verified to flow to constant base
On plinth, the signal connection relation that the preset top layer metallic layer is adjusted by FIB experimental methods completes test signal line B to be verified
Test job.Wherein, the signal corresponding to test signal line B to be verified is flowed into from preset metal layer 110.Relative to existing skill
Use the mode of probe test chip signal, the embodiment of the present invention that need not open a window on the metal layer using probe, herein in art
On the basis of, if the chip after verification needs correcting, only need through FIB experimental methods to the preset top layer gold
Belong to layer and make wire jumper processing, you can realizes by changing the mask plate identical impact of performance of flow again, avoid chip correcting institute band
The wasting of resources come.
As the embodiment of the present invention three, during carrying out the validation test of chip interior signal, the main signal line
The preset top layer metallic layer at place uses the focused ion for being flowed to according to the signal to be tested in chip layout structure
The experimental method of beam is connected to the preset top layer metallic layer where the test signal line to be verified of specified one.Such as Fig. 4 institutes
Show, the signal corresponding to test signal line C to be verified is flowed into from preset metal layer 111, in subsequent process flow, when the signal
When needing to export test by the preset top layer metallic layer 101 where the main signal line, the reality of the focused ion beam is used
Proved recipe method removes the surface to be measured of preset top layer metallic layer 109 respectively（109 surface encircled of preset top layer metallic layer）With it is pre-
Set the surface to be measured of top layer metallic layer 101（101 surface encircled of preset top layer metallic layer）And it is mutual to expose corresponding metal
Even layer, is then connected to preset top layer metallic layer 109 in the Surface Creation intermediate connecting body D3 to be measured of preset top layer metallic layer 101
Surface to be measured, to set up the connection relation of preset top layer metallic layer 108 and preset top layer metallic layer 101, and maintaining
On the basis of being inputted in the integrated circuit layout structure to induction signal of test signal line C to be verified flows to constant, pass through
The signal connection relation that adjustment adjusts the preset top layer metallic layer by FIB experimental methods completes test signal line C to be verified
Test job.Wherein, the signal corresponding to test signal line B to be verified is flowed into from preset metal layer 110.Relative to existing skill
The mode that probe test chip signal is used in art, the selection space of correcting interconnection metal layer is reserved for project.Relative to existing
Technology, the embodiment of the present invention are more to be flexibly utilized by FIB experiments based on the domain structure of simple controllable chip signal debugging
Method cuts off metal layer, connects or wire jumper processing, to realize that chip interior signal debugs the survey in industrial manufacturing process
Try efficiency maximization and theorem about solutions.It should be noted that metal connector 103 is according to chip interior reality in this implementation
Border signal flow direction can be cut or not cut.
In previous embodiment, FIB (Focused Ion Beam focused ion beams) technology can not destroy chip entirety
Under the premise of function, the metal connecting line of modification chip part cuts off metal, connects or wire jumper is handled, reach with by repairing
Change the mask plate identical performance of flow and effect again.Based on the trial signal to be measured inside the integrated circuit layout structure, profit
The integrated circuit layout structure is cut with the experimental method of focused ion beam, to believe the test to be verified specified
Number line is connected on main signal line, completes the new connection of the preset top layer metallic layer between unlike signal line.Utilize FIB skills
Art, which modifies to chip, can reduce development cost, shorten the R&D cycle, can also in advance be verified to design modification.
In previous embodiment, the integrated circuit layout structure further includes through-hole, which is to realize the pre- top set
Layer metal layer be connected with the preset metal layer and by Jie between the preset top layer metallic layer and the preset metal layer
Matter layer, which opens up, to be formed.In conjunction with shown in Fig. 1, Fig. 2, Fig. 3 and Fig. 4, preset metal layer 102 and preset top layer metallic layer 101 pass through
It opens up through-hole 104 and forms the connecting path of the main signal line, preset metal layer 110 and preset top layer metallic layer 108 pass through
It opens up through-hole 112 and forms the connecting path of the test signal line to be verified, preset metal layer 107 and preset top layer metallic layer
105 form the connecting path of the test signal line to be verified, preset metal layer 111 and pre- top set by opening up through-hole 106
Layer metal layer 109 forms the connecting path of the test signal line to be verified by opening up through-hole 113.It should be noted that preceding
It states in embodiment, the placement position of through-hole 112, through-hole 106 and through-hole 113 remains unchanged, therefore the position of the preset metal layer
It sets and does not also change, the function to safeguard the integrated circuit layout structure is constant, and the only preset top layer changed
Metal layer.
The embodiment of the present invention passes through the domain structure of reasonable design, during chip debug, no extra circuits
Structure is without the use of probe device, avoids the Metal contact regions on chip for probe analysis from exposing in air, leads to gold
Category layer is easily oxidised or otherwise loss, so as to shorten the life cycle of chip；Chip interior key is not influenced simultaneously
The transmission quality of signal can be used for being widely used in chip interior key signal key modules signal junction.If by testing
Chip after card needs correcting, then only needing to change the position connection relation of the preset top layer metallic layer, you can realize phase
Same chip correcting effect, to promote chip project faster to complete.
Above example be only it is fully open is not intended to limit the present invention, all creation purports based on the present invention, without creating
Property labour equivalence techniques feature replacement, should be considered as the application exposure range.
Claims (5)
1. a kind of integrated circuit layout structure convenient for chip testing, including preset metal layer and preset top layer metallic layer, wherein
Preset metal layer is arbitrary other than preset top layer metallic layer in the metal interconnecting layer in the integrated circuit layout structure
Metal layer；There is the metal that preset top layer metallic layer and preset metal layer is connected to connect for preset top layer metallic layer and preset metal interlevel
Wiring, which is characterized in that the metal contact wires include main signal line and the test signal line to be verified of preset quantity；Wherein,
The preset top layer metallic layer where main signal line and the pre- top set where the test signal line to be verified of preset quantity
Layer metal layer is located at different location；
The integrated circuit layout structure further includes a metal connector for cutting, wherein the metal connector is to use
In the metal interconnecting layer of connection conducting main signal and test signal to be verified；
One end of preset top layer metallic layer where the test signal line to be verified and the metal connector with there are physics to connect
Touch, the other end of preset top layer metallic layer where the main signal line and the metal connector with there is also physical contacts, use
In cutting the metal connector in focused ion beam to terminate the connection of the test signal line and the main signal line to be verified
After relationship, then it is connected to by the experimental method of focused ion beam pre- where the specified new test signal line to be verified
Set top layer metallic layer.
2. integrated circuit layout structure according to claim 1, which is characterized in that the track lengths of the metal connector are big
In 3 microns, and the spacing of its metal layer adjacent with same metal interconnecting layer is more than 2 microns；Wherein, the metal layer includes
The preset top layer metallic layer where preset top layer metallic layer and the test signal line to be verified where the main signal line.
3. integrated circuit layout structure according to claim 2, which is characterized in where the test signal line to be verified
Preset top layer metallic layer uses the reality of the focused ion beam for being flowed to according to the signal to be tested in chip layout structure
Proved recipe method snaps into the preset top layer metallic layer where the main signal line.
4. integrated circuit layout structure according to claim 2, which is characterized in that the preset top layer where the main signal line
Metal layer is connected for being flowed to according to the signal to be tested in chip layout structure using the experimental method of the focused ion beam
The preset top layer metallic layer being connected to where the test signal line to be verified of specified one.
5. according to integrated circuit layout structure described in claim 1, which is characterized in that further include through-hole, which is to realize institute
Preset top layer metallic layer is stated to be connected with the preset metal layer and by the preset top layer metallic layer and the preset metal layer
Between dielectric layer open up to be formed.
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| CN112118166A (en) * | 2020-09-18 | 2020-12-22 | 上海国微思尔芯技术股份有限公司 | Multi-chip networking system, method and application |
| CN112541320A (en) * | 2020-12-07 | 2021-03-23 | 深圳英集芯科技股份有限公司 | Design method of metal connecting line in power device layout |
| CN113113388A (en) * | 2021-04-09 | 2021-07-13 | 颀中科技（苏州）有限公司 | Wafer rewiring double verification structure, manufacturing method and verification method |
| CN114801522A (en) * | 2021-01-29 | 2022-07-29 | 杭州旗捷科技有限公司 | Print job processing method, chip, consumable container and printer system |
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| CN114801522A (en) * | 2021-01-29 | 2022-07-29 | 杭州旗捷科技有限公司 | Print job processing method, chip, consumable container and printer system |
| CN113113388A (en) * | 2021-04-09 | 2021-07-13 | 颀中科技（苏州）有限公司 | Wafer rewiring double verification structure, manufacturing method and verification method |
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