CN103839921A - Through si via radio frequency test structure and parasitic extracting method thereof - Google Patents
Through si via radio frequency test structure and parasitic extracting method thereof Download PDFInfo
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Abstract
The invention discloses a through si via radio frequency test structure which is formed by a first test structure and a second open circuit de-embedding structure. The first test structure comprises a first port and a second port of a GSG bonding pad structure; signal ends of the first port and the second port are connected in a short circuit manner by a first top metal; a tested through si via is arranged between signal ends of the first port and the second port; the top of the tested through si via is connected with the first top metal; the bottom of tested through si via is connected with a second back metal; and grounding terminals of the first port and the second port are respectively connected with the second back metal through a grounding through si via array. The second open circuit de-embedding structure and the first test structure, after the first top metal and tested through si via are removed, are the same in structure. The invention also discloses a parasitic extracting method of the through si via radio frequency test structure. According to the invention, the accuracy of testing the parasitic resistance and inductance of the through si via can be improved, and the test structure area and the process cost can be reduced.
Description
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field, particularly relate to a kind of radio frequency test structure of silicon through hole.The invention still further relates to a kind of parasitic extracting method of radio frequency test structure of silicon through hole.
Background technology
Silicon through hole (Through Si via, TSV) technique is a kind of emerging ic manufacturing process, the circuit that is produced on silicon chip upper surface is connected to silicon chip back side by the metal of filling in silicon through hole, in conjunction with three-dimension packaging technique, make IC layout from conventional two-dimensional be arranged side by side develop into more advanced three-dimensional stacked, component encapsulation is more compact like this, by shortening chip lead distance, can improve greatly frequency characteristic and the power characteristic of circuit.Silicon via process is widely used, and is suitable as many-sided device performance and promotes.As use it for WLAN (wireless local area network) and mobile phone intermediate power amplifier, will improve greatly frequency characteristic and the power characteristic of circuit.
The major parameter of evaluating silicon through hole is stray inductance and dead resistance, due to stray inductance and dead resistance smaller, very high to the requirement of test.The conventional test structure of industry is tested and is extracted by the method for two TSV series connection at present, as shown in Figure 1A, is the vertical view of the radio frequency test structure of existing silicon through hole; The radio frequency test structure 101 of existing silicon through hole comprises by a signal end 102a and two ground holds 102b to form the port one that is ground-signal-ground (GSG) structure, and forming by a signal end 103a and two ground end 103b the port two that is ground-signal-ground (GSG) structure, signal end 102a, 103a and ground end 102b, 103b are formed by metal etch.Signal end 102a is connected with bonding jumper 104a, and signal end 102b is connected with bonding jumper 104b.As shown in Figure 1B, be the profile along the CC ' line in Figure 1A; First TSV105a and second TSV105b are arranged between signal end 102a and signal end 103a, wherein the top of first TSV105a is connected with bonding jumper 104a, the top of second TSV105b is connected with bonding jumper 104b, and the bottom of first TSV105a and second TSV105b is all connected with bottom metal 106.By adding radiofrequency signal to realize the test to two TSV105a and 105b between signal end 102a and signal end 103a.
The radio frequency test structure of existing silicon through hole also will comprise that an open circuit goes embedding structure and a path to go embedding structure, as shown in Figure 1 C, is that the open circuit of the radio frequency test structure of existing silicon through hole removes the vertical view of embedding structure; Open circuit goes embedding structure 107 to comprise the port one that be made up of (GSG) structure that is earth signal a signal end 108a and two ground end 108b, and holds 109b to form the port two that is ground-signal-ground (GSG) structure by a signal end 109a and two ground.Open circuit goes embedding structure 107 to be with the difference of radio frequency test structure 101: bonding jumper and back metal that open circuit goes the signal end 108a of embedding structure 107 there is no TSV and be connected with TSV with signal end 109a.
As shown in Fig. 1 D, be that the path of the radio frequency test structure of existing silicon through hole removes the vertical view of embedding structure; Path goes embedding structure 110 comprise by a signal end 111a and two hold 111b to form the port one that is ground-signal-ground (GSG) structure, and forms by a signal end 112a and two ground end 112b the port two that is ground-signal-ground (GSG) structure.Path goes embedding structure 110 to go the difference of embedding structure 107 to be with open circuit: path goes the signal end 108a of embedding structure 110 to be also connected by bonding jumper 113 with signal end 109a.
Above-mentioned existing structure can extract more accurate stray inductance and dead resistance, but also exist some defects, cause test result to have certain error, after two TSV series connection, can produce mutual inductance, this part is difficult to remove, although can reduce or eliminate mutual inductance impact by strengthening the method for two distances between TSV, this also can increase the dead resistance of coupling part, two the TSV back side, but also can increase area; From going to embedding aspect, the method need to be equipped with an open-circuit structure and an access structure, goes embedding structure many in addition, and the area that takies chip is also many, and cost is higher.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of radio frequency test structure of silicon through hole, can improve the accuracy of the dead resistance of silicon through hole and the test of stray inductance, can reduce the area of test structure, reduces process costs.For this reason, the present invention also provides a kind of parasitic extracting method of radio frequency test structure of silicon through hole.
For solving the problems of the technologies described above, the radio frequency test structure of silicon through hole provided by the invention goes embedding structure two to form by test structure one and open circuit.
Described test structure one comprises port one and port two, described port one and described port two are all made up of a ground-signal-ground pad respectively, the distance of the signal end of described port one and two ground ends is more than or equal to 150 microns, and the distance of the signal end of described port 21 and two ground ends is more than or equal to 150 microns; The signal end of the signal end of described port one and described port two is connected by top-level metallic one short circuit, tested silicon through hole is arranged between the signal end of described port one and the signal end of described port two, and the top of described tested silicon through hole is connected with described top-level metallic one, the bottom of described tested silicon through hole and be formed at back metal two connections of silicon chip back side; Holding all of described port one and described port two is connected with described back metal two by a ground connection silicon via-hole array respectively each describedly.
It is identical with the structure after described tested silicon through hole that described open circuit goes embedding structure two and described test structure one to remove described top-level metallic one.
Further improving is that the area of described ground connection silicon via-hole array is at least the twice of the area of described tested silicon through hole.
Further improving is that the distance between described ground connection silicon via-hole array and described tested silicon through hole is more than 200 microns.
Further improving is that described back metal two is a block structure.
For solving the problems of the technologies described above, the parasitic extracting method of the radio frequency test structure of silicon through hole provided by the invention comprises the steps:
In test structure of the present invention, only need that a tested silicon through hole is set and just can realize the extraction of the parasitic parameter of silicon through hole, the present invention can eliminate two tested silicon through holes of available technology adopting time, between silicon through hole, can produce the error that mutual inductance causes, so can improve the accuracy of the dead resistance of silicon through hole and the test of stray inductance.The present invention adopts a tested silicon through hole can also reduce the area of test structure, reduces process costs.The present invention only need adopt an open circuit to go embedding structure just can realize and go embedding, with respect to of the prior art go embedding structure need to open a way and closed circuit two kinds remove embedding knot, the shared chip area of embedding structure that goes of the present invention is less, thereby can further reduce the area of test structure, reduces process costs.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Figure 1A is the vertical view of the radio frequency test structure of existing silicon through hole;
Figure 1B is the profile along the CC ' line in Figure 1A;
Fig. 1 C is the vertical view that the open circuit of the radio frequency test structure of existing silicon through hole goes embedding structure;
Fig. 1 D is the vertical view that the path of the radio frequency test structure of existing silicon through hole goes embedding structure;
Fig. 2 A is the vertical view of the test structure one of the radio frequency test structure of embodiment of the present invention silicon through hole;
Fig. 2 B is the profile along the AA ' line in Fig. 2 A;
Fig. 2 C is the profile along the BB ' line in Fig. 2 A;
Fig. 2 D is that the open circuit of the radio frequency test structure of embodiment of the present invention silicon through hole removes the vertical view of embedding structure two;
Fig. 3 A is the equivalent circuit diagram of the test structure one of the radio frequency test structure of embodiment of the present invention silicon through hole;
Fig. 3 B is that the open circuit of the test structure one of the radio frequency test structure of embodiment of the present invention silicon through hole removes the equivalent circuit diagram after embedding;
Fig. 4 A is the stray inductance of embodiment of the present invention method extraction and the correlation curve of emulation;
Fig. 4 B is the dead resistance of embodiment of the present invention method extraction and the correlation curve of emulation.
Embodiment
As shown in Figure 2 A, be the vertical view of the test structure one of the radio frequency test structure of embodiment of the present invention silicon through hole; As shown in Figure 2 B, be the profile along the AA ' line in Fig. 2 A; As shown in Figure 2 C, be the profile along the BB ' line in Fig. 2 A; As shown in Figure 2 D, be that the open circuit of the radio frequency test structure of embodiment of the present invention silicon through hole removes the vertical view of embedding structure two.The radio frequency test structure of embodiment of the present invention silicon through hole goes embedding structure 28 to form by test structure 1 and open circuit.
Described test structure 1 comprises port one and port two, and described port one is made up of a signal end 2a and two ground end 2b, is ground-signal-ground (GSG) structure; Described port two is made up of a signal end 3a and two ground end 3b, is ground-signal-ground (GSG) structure; Signal end 2a and 3a and ground end 2b and 3b are made up of the metal pad that is formed at front side of silicon wafer.
The distance of the signal end 2a of described port one and two ground end 2b is more than or equal to 150 microns, and the distance of the signal end 3a of described port 21 and two ground end 3b is more than or equal to 150 microns.Described signal end 2a and described signal end 3a are a straight line, described signal end 2a and described signal end 3a both sides hold also the laying respectively on a straight line of 2b and corresponding ground end 3b describedly.
The signal end 2a of described port one is connected by top-level metallic one 4 short circuits with the signal end 3a of described port two, tested silicon through hole 5 is arranged between the signal end 2a of described port one and the signal end 3a of described port two, and the top of described tested silicon through hole 5 is connected with described top-level metallic 1, the bottom of described tested silicon through hole 5 is connected with the back metal 27 that is formed at silicon chip back side.
The 2b that holds of described port one and described port two is connected with described back metal 27 by a ground connection silicon via-hole array 6 respectively with 3b each describedly.
The area of described ground connection silicon via-hole array 6 is at least the twice of the area of described tested silicon through hole 5.Distance between described ground connection silicon via-hole array 6 and described tested silicon through hole 5 is more than 200 microns.
Described back metal 27 is a block structure, by same block structure, the bottom of described ground connection silicon via-hole array 6 and described tested silicon through hole 5 is linked together.
It is identical with the structure after described tested silicon through hole 5 that described open circuit goes embedding structure 28 and described test structure 1 to remove described top-level metallic 1.Described open circuit goes the port one of embedding structure 28 to be made up of a signal end 9a and two ground end 9b, is ground-signal-ground (GSG) structure; Described port two is made up of a signal end 10a and two ground end 10b, is ground-signal-ground (GSG) structure; Signal end 9a and 10a and ground end 10b and 10b are made up of metal pad.The 9b that holds of described port one and described port two is connected with back metal two by a ground connection silicon via-hole array 11 respectively with 10b each describedly.
In the embodiment of the present invention by arranging of back metal 27 can guarantee test structure in test process the back side can with the base good contact of tester table, described test structure 1, by four ground end 2b and 3b ground connection, can guarantee described tested silicon through hole 5 good earths.
Distance between described ground connection silicon via-hole array 6 and described tested silicon through hole 5 is set to more than 200 microns, can eliminate the impact between described ground connection silicon via-hole array 6 and described tested silicon through hole 5; Distance between described ground connection silicon via-hole array 6 and described tested silicon through hole 5 is set to more than 200 microns simultaneously, can't bring the problem of the area that increases test structure, because the most general its signal end of probe of the test port of existing conventional GSG pad structure is 150 microns to the distance of earth terminal, to guarantee that like this distance between described ground connection silicon via-hole array 6 and described tested silicon through hole 5 is more than 200 microns, described signal end 2a and 3a do not need very long to the line distance of described tested silicon through hole 5, can not have influence on the area of test structure.
In addition, because the array structure that described ground connection silicon via-hole array 6 is all made up of multiple silicon through holes, and more than the area of described ground connection silicon via-hole array 6 is set to the twice into the area of described tested silicon through hole 5, and consider back metal two can with the base good contact of tester table, hold the ghost effect of 2b and 3b negligible so of the present inventionly.
As shown in Figure 3A, be the equivalent circuit diagram of the test structure one of the radio frequency test structure of embodiment of the present invention silicon through hole; This equivalent electric circuit comprises:
The first parasitic capacitance Cox1 is the parasitic capacitance between described signal end 2a and described silicon chip substrate.
The second parasitic capacitance Cox2 is the parasitic capacitance between described signal end 3a and described silicon chip substrate.
The first dead resistance R1 is the dead resistance of the described top-level metallic 1 between described signal end 2a and described tested silicon through hole 5.
The second dead resistance R2 is the dead resistance of the described top-level metallic 1 between described signal end 3a and described tested silicon through hole 5.
The first stray inductance L1 is the stray inductance of the described top-level metallic 1 between described signal end 2a and described tested silicon through hole 5.
The second stray inductance L2 is the stray inductance of the described top-level metallic 1 between described signal end 2a and described tested silicon through hole 5.
Silicon through hole dead resistance RTSV is the dead resistance of described tested silicon through hole 5.
Silicon through hole stray inductance LTSV is the stray inductance of described tested silicon through hole 5.
As shown in Figure 3 B, be that the open circuit of the test structure one of the radio frequency test structure of embodiment of the present invention silicon through hole removes the equivalent circuit diagram after embedding.Compare with the equivalent circuit diagram shown in Fig. 3 A, open circuit goes the equivalent circuit diagram after embedding to remove described the first parasitic capacitance Cox1 and described the second parasitic capacitance Cox2.
The parasitic extracting method of the radio frequency test structure of embodiment of the present invention silicon through hole comprises the steps:
LTSV=imag ((Zo'
12+ Zo'
21)/2 ω), wherein ω=2 × π × freq, freq is frequency.
RTSV=real((Zo'
12+Zo'
21)/2)。
As shown in Figure 4 A, be the stray inductance of embodiment of the present invention method extraction and the correlation curve of emulation; As shown in Figure 4 B, be the dead resistance of embodiment of the present invention method extraction and the correlation curve of emulation.In Fig. 4 A and Fig. 4 B, the corresponding tested silicon through hole length of serving as reasons is 35 microns, and wide is 2.5 microns, and the degree of depth is 100 microns, and spacing is the array of 8 silicon through holes compositions of 4 microns, and the material of tested silicon through hole is tungsten.Dotted line corresponding in Fig. 4 A and Fig. 4 B is that the open circuit obtaining through the actual measurement of the inventive method according to the test structure of the embodiment of the present invention goes the data after embedding.In Fig. 4 A and Fig. 4 B, the data of wire curve are the data that use the tested tested silicon through hole of EMX software emulation, when emulation only the tested silicon through hole of emulation, do not comprise GSG testing weld pad and line etc.Can be found out by Fig. 4 A and Fig. 4 B, the measurement result of the embodiment of the present invention and simulation architecture coincide very well.So the embodiment of the present invention can improve the accuracy of the dead resistance of silicon through hole and the test of stray inductance.
By specific embodiment, the present invention is had been described in detail above, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (5)
1. a radio frequency test structure for silicon through hole, is characterized in that: radio frequency test structure goes embedding structure two to form by test structure one and open circuit;
Described test structure one comprises port one and port two, described port one and described port two are all made up of a ground-signal-ground pad respectively, the distance of the signal end of described port one and two ground ends is more than or equal to 150 microns, and the distance of the signal end of described port 21 and two ground ends is more than or equal to 150 microns; The signal end of the signal end of described port one and described port two is connected by top-level metallic one short circuit, tested silicon through hole is arranged between the signal end of described port one and the signal end of described port two, and the top of described tested silicon through hole is connected with described top-level metallic one, the bottom of described tested silicon through hole and be formed at back metal two connections of silicon chip back side; Holding all of described port one and described port two is connected with described back metal two by a ground connection silicon via-hole array respectively each describedly;
It is identical with the structure after described tested silicon through hole that described open circuit goes embedding structure two and described test structure one to remove described top-level metallic one.
2. the radio frequency test structure of silicon through hole as claimed in claim 1, is characterized in that: the area of described ground connection silicon via-hole array is at least the twice of the area of described tested silicon through hole.
3. the radio frequency test structure of silicon through hole as claimed in claim 1, is characterized in that: the distance between described ground connection silicon via-hole array and described tested silicon through hole is more than 200 microns.
4. the radio frequency test structure of silicon through hole as claimed in claim 1, is characterized in that: described back metal two is a block structure.
5. the parasitic extracting method of the radio frequency test structure of silicon through hole as claimed in claim 1, is characterized in that, comprises the steps:
Step 1, test the scattering parameter one between port one and the port two of described test structure one, and this scattering parameter one is converted into admittance parameter one;
Step 2, test the scattering parameter two between port one and the port two that described open circuit goes embedding structure two, and this scattering parameter two is converted into admittance parameter two;
Step 3, described admittance parameter one is deducted to described admittance parameter two obtain open circuit and remove admittance parameter three after embedding, described admittance parameter three is converted to impedance parameter, obtains the dead resistance of described tested silicon through hole, obtained the stray inductance of described tested silicon through hole by the imaginary part of described impedance parameter by the real part of described impedance parameter.
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| CN104425293A (en) * | 2013-08-26 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Test structure for monitoring open circuit situation of SRAM through hole, and formation method thereof |
| CN104793120A (en) * | 2015-04-03 | 2015-07-22 | 浙江大学 | TSV (through silicon via) electrical characteristic measuring structure based on de-embedding method |
| CN106654544A (en) * | 2015-11-03 | 2017-05-10 | 南京理工大学 | Parasitic-patch-loaded high-gain microstrip antenna based on GaN processing technology |
| CN107247225A (en) * | 2017-06-12 | 2017-10-13 | 上海华岭集成电路技术股份有限公司 | A kind of calibration method tested based on ATE radio frequencies CP |
| CN108766958A (en) * | 2018-08-27 | 2018-11-06 | 珠海市微半导体有限公司 | A kind of integrated circuit layout structure convenient for chip testing |
| CN108899320A (en) * | 2018-07-20 | 2018-11-27 | 上海华力微电子有限公司 | A kind of MOSFET gate oxide capacitance calibration structure |
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| CN104425293A (en) * | 2013-08-26 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Test structure for monitoring open circuit situation of SRAM through hole, and formation method thereof |
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| CN106654544A (en) * | 2015-11-03 | 2017-05-10 | 南京理工大学 | Parasitic-patch-loaded high-gain microstrip antenna based on GaN processing technology |
| CN107247225A (en) * | 2017-06-12 | 2017-10-13 | 上海华岭集成电路技术股份有限公司 | A kind of calibration method tested based on ATE radio frequencies CP |
| CN108899320A (en) * | 2018-07-20 | 2018-11-27 | 上海华力微电子有限公司 | A kind of MOSFET gate oxide capacitance calibration structure |
| CN108766958A (en) * | 2018-08-27 | 2018-11-06 | 珠海市微半导体有限公司 | A kind of integrated circuit layout structure convenient for chip testing |
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