CN104425293A - Test structure for monitoring open circuit situation of SRAM through hole, and formation method thereof - Google Patents
Test structure for monitoring open circuit situation of SRAM through hole, and formation method thereof Download PDFInfo
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- CN104425293A CN104425293A CN201310376738.3A CN201310376738A CN104425293A CN 104425293 A CN104425293 A CN 104425293A CN 201310376738 A CN201310376738 A CN 201310376738A CN 104425293 A CN104425293 A CN 104425293A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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Abstract
The invention provides a test structure for monitoring an open circuit situation of a static random access memory (SRAM) through hole, and a formation method thereof. The formation method comprises the following steps that: step one, a substrate is provided and at least two shallow channel isolation regions are formed in the substrate; step two, a contact hole is formed in each shallow channel isolation region, wherein the height of the contact hole is equal to the height of the contact hole in the SRAM; step three, a first metal layer is formed at each contact hole; step four, through holes are respectively formed in two ends of the surface of each first metal layer; and step five, the two through holes formed in the two adjacent first metal layers are connected by a second metal layer, thereby obtaining a chain type test structure. With the test structure, the process situation of the SRAM through hole can be reflected accurately; whether an open circuit phenomenon occurs at the though hole of the SRAM is monitored in a real time; and the product yield is improved.
Description
Technical field
The invention belongs to technical field of semiconductors, particularly relate to a kind of test structure and forming method thereof of monitoring SRAM through hole open circuit.
Background technology
Static random access memory (Static Random Access Memory, SRAM) be very important a kind of memory device in current integrated circuit memory devices field, as memory device, its because of have low-power consumption, data access speed fast and with the feature such as CMOS logic process is compatible, be widely used in modern very lagre scale integrated circuit (VLSIC).Along with the development of technology, the growing number of the semiconductor device such as the transistor comprised in integrated circuit is many, in order to be coupled together by semiconductor device, is generally provided with multiple metal level in integrated circuit.Semiconductor device is connected with metal level by contact hole (Contact, CT), is then connected by through hole (Via) between each metal level.
Industry, in ic manufacturing process, in each integrated circuit (IC) chip periphery manufacturing test structure of wafer, then can detect test structure, to test corresponding manufacturing process usually after finalization of the manufacture.Be illustrated in figure 1 in prior art the test structure being manufactured on SRAM periphery, for monitoring the etching situation of through hole in SRAM.The SRAM1 structure of described reality at least comprises: substrate 11, be formed at active area in described substrate 11, the first metal layer 13 that is connected with described active area by contact hole 12, be incorporated into substrate 11 surface and the second metal level 15 being in polysilicon gate 16 between contact hole 12, being connected with described the first metal layer 13 by through hole 14.Described test structure 2A at least comprises: the first metal layer 23A and arrange a through hole 24A respectively at described the first metal layer 23A two ends; Through hole 24A on described adjacent the first metal layer 23A is connected by the second metal wire 25A, the chain structure of formation rule.Described test structure 2A is positioned at above substrate 11, fills between test structure 2A and substrate 11 with dielectric material.As seen from Figure 1, there is difference in height in vertical direction in the first metal layer 13 of SRAM and the first metal layer 23A of existing test structure 2A, due to the existence of this difference in height, follow-up carry out through hole exposure time, in SRAM and test structure, the exposure shape of through hole just has difference, may occur that the through hole in SRAM is not connected with upper lower metal layer the most at last, but the through hole in test structure is connected with upper lower metal layer normal.When carrying out through hole 24A resistance test, be made up of chain type test structure two ends applying voltage the first metal layer 23A, through hole 24A and the second metal level 25A, as shown in Fig. 2, the two ends of structure apply voltage, the through hole 24A contact resistance measured also is in normal range (NR).Like this, in the normal situation of test structure through hole, technical staff will think that through hole is also normal in SRAM, but actual conditions are not like this.Therefore, existing test structure can not reflect via process situation in SRAM exactly, seek a kind of more can accurately reflect the test structure of via process situation in SRAM be those skilled in the art need solve problem.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of test structure and forming method thereof of monitoring SRAM through hole open circuit, accurately can not reflect the problem of via process situation in SRAM for solving test structure in prior art.
For achieving the above object and other relevant objects, the invention provides a kind of formation method of the test structure for monitoring SRAM through hole open circuit, the formation method of described test structure at least comprises:
One substrate is provided, in described substrate, forms at least two shallow trench isolation regions;
On each shallow trench isolation regions, form contact hole, the height of described contact hole equals the height of contact hole in SRAM;
The first metal layer is formed on described each contact hole;
A through hole is respectively arranged with in the surperficial two ends of described each the first metal layer;
Two through holes laid respectively on two adjacent the first metal layers are connected by the second metal level, thus obtain the test structure of chain type.
Preferably, after forming described shallow trench isolation regions, the substrate between adjacent shallow trench isolation regions forms polysilicon gate.
Preferably, the step forming described contact hole comprises:
Deposit one insulating medium layer over the substrate, the consistency of thickness of the insulating medium layer of correspondence position in the thickness of described insulating medium layer and SRAM;
Etch described insulating medium layer until expose substrate, thus formed contact hole, and in contact hole filled conductive material, now, the contact hole height of making equals the height of contact hole in SRAM.
Preferably, the altitude range of described contact hole is 900 ~ 1800 dusts.
Preferably, described the first metal layer is copper product, and described second metal level is copper product.
Preferably, the concrete steps forming described the first metal layer, through hole and the second metal level comprise:
Form a bottom metal layers, the pattern of described bottom metal layers is identical with the pattern of the first metal layer in SRAM;
The described bottom metal layers of part arranges through hole, and the position of the through hole in described bottom metal layers is corresponding consistent with the position of through hole on the first metal layer in SRAM; Described bottom metal layers is arranged in the through hole of same row, often adjacent two through holes are divided into one group, and each through hole only belongs to a group, and often organize through hole all by described second metal level connection;
Often organize the disconnected place of bottom metal break outside through hole and add supplement metal wire being arranged in same row; Be arranged in same a line and often organize bottom metal layers outside through hole and described supplement metal wire forms described the first metal layer;
Remove the bottom metal layers of the part in the ranks that the supplement metal wire of adjacent lines is connected;
The head end of adjacent lines or tail end are connected by the ranks metal wire, form the test structure of described chain type.
The present invention also provides a kind of test structure of monitoring SRAM through hole open circuit, and described test structure at least comprises:
Substrate;
Shallow trench isolation regions, is formed in described substrate;
Contact hole, is formed on described shallow trench isolation regions, and the height of described contact hole equals the height of contact hole in SRAM;
The first metal layer, is formed on described contact hole;
Through hole, is formed at the surperficial two ends of described the first metal layer;
Second metal level, between the through hole being connected to adjacent the first metal layer two ends, thus forms the test structure of chain type.
Preferably, the substrate between described shallow trench isolation regions is formed with grid.
Preferably, the space outside substrate described in test structure, shallow trench isolation regions, the first metal layer, through hole, the second metal level and grid is filled with insulating medium layer.
Preferably, also comprise in described test structure and to be in the first metal layer in same aspect and virtual bottom metal layers for simulating SRAM the first metal layer patterning.
Preferably, described the first metal layer is copper product, and described second metal level is copper product.
As mentioned above, test structure of monitoring SRAM through hole open circuit of the present invention and forming method thereof, there is following beneficial effect: on the one hand, by increasing the height contact hole equal with SRAM contact hole height in test structure, make the first metal layer in test structure in the first metal layer and SRAM contour, expose form via hole image time indifference; On the other hand, by simulating the structural environment of SRAM, make the structure of test structure and SRAM more close, such test structure can reflect the via process situation of SRAM more.
Accompanying drawing explanation
Fig. 1 is existingly made in the SRAM on same substrate and the test structure generalized section for monitoring SRAM through hole.
Fig. 2 is existing test structure vertical view.
Fig. 3 is the flow chart that the present invention forms test structure.
Fig. 4 is test structure generalized section of the present invention.
Fig. 5 is made in existing SRAM on same substrate and the present invention for monitoring the test structure generalized section of SRAM through hole.
Fig. 6 is existing SRAM structure vertical view.
Fig. 7 is the test structure vertical view for monitoring SRAM through hole of the present invention.
Element numbers explanation
1 SRAM
11,21 substrates
12,22 contact holes
13,23,23A the first metal layer
14,24,24A, through hole
241,242,243,244
15,25,25A second metal level
16,26 polysilicon gates
2,2A test structure
27 shallow trench isolation regions
23 ' bottom metal layers
231 virtual bottom metal layers
28 supplement metal wires
29 removed bottom metal layers
30 in the ranks metal wires
Embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this specification can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this specification also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
Refer to accompanying drawing.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, then only the assembly relevant with the present invention is shown in graphic but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
Embodiment one
The invention provides a kind of formation method of monitoring the test structure of SRAM through hole open circuit, as shown in Figure 3, the formation method of described test structure at least comprises:
First carry out step S1, a substrate 21 be provided, described substrate 21 is formed at least two shallow trench isolation regions 27(Shallowtrench isolation, STI), as shown in Figure 4.
It should be noted that, in sram the position of respective substrate, formation be active area (Active Area, AA).Be communicated with polysilicon gate in order to avoid the through hole of follow-up making is at least partially by the active region in test structure, active area is replaced with shallow trench isolation regions.The concrete steps preparing described shallow trench isolation regions 27 comprise: first, etch described substrate 21, form the groove of inverted trapezoidal in the substrate 21; Then, fill in insulating dielectric materials to described groove; Finally, insulating dielectric materials described in polishing, makes insulating dielectric materials surfacing and flushes with substrate surface.The insulating dielectric materials of described shallow trench isolation regions 27 is silicon dioxide, but is not limited thereto, and also can be other insulating material.
In order to make test structure and SRAM structure more close, preferably, after forming described shallow trench isolation regions 27, the substrate 21 between adjacent shallow trench isolation regions 27 forms polysilicon gate 26.Certainly, between polysilicon gate 26 and substrate 21, one deck grid oxygen can also be prepared.
Then carry out step S2, on each shallow trench isolation regions 27, form contact hole 22, the height of described contact hole 22 equals the height of contact hole 12 in SRAM1, as shown in Figure 4 and Figure 5.
The concrete steps forming described contact hole comprise: first, deposit one insulating medium layer (diagram) on described substrate 21, the consistency of thickness of the insulating medium layer of correspondence position in the thickness of described insulating medium layer and SRAM1; Then, etch described insulating medium layer until expose substrate 21, thus formed contact hole 22, and in contact hole 22 filled conductive material, now, the contact hole 22 of making highly equals the height of contact hole 12 in SRAM1.
Preferably, described contact hole 22 altitude range be 900 ~ 1800 dusts.In the present embodiment, the height of described contact hole 22 is 1000 dusts.
Then carry out step S3, on described each contact hole 22, form the first metal layer 23.
Described contact hole 22 is construed as in contact hole 22 has filled full electric conducting material, and the first metal layer 23 is formed at the conductive material surface of filling.
Preferably, described the first metal layer 23 is copper or aluminum, also can be other any suitable metal materials.In the present embodiment, described the first metal layer 23 is copper product.
Chemical vapour deposition (CVD), physical vapour deposition (PVD), vacuum evaporation or other suitable depositing technics is adopted to prepare described the first metal layer 23.In the present embodiment, chemical vapor deposition method is adopted to prepare the first metal layer 23.
Carry out step S4 again, be respectively arranged with a through hole 24 in the surperficial two ends of described each the first metal layer 23.
Described through hole 24 is construed as and is included by the packing material of through hole.The concrete steps making through hole 24 comprise: first, the first metal layer 23 forms insulating dielectric materials; Photoresist (diagram) is applied again on described the first metal layer 23; Then photoresist is exposed to the figure forming through hole on a photoresist; Recycling etching technics etch described insulating dielectric materials formed through hole 24, and in through hole 24 filled conductive material.
First by step S2, the height of contact hole 22 in test structure 2 is made into highly identical with the contact hole 12 in SRAM1, make in step S3, to be formed in the first metal layer 23 on contact hole 22 highly identical with the first metal layer 13 of SRAM1, like this, when carrying out through hole exposure technology, the exposure figure that the first metal layer 23 of test structure 2 and the first metal layer 13 of SRAM1 are formed is basically identical, the process condition of the through hole formed in test structure 2 and SRAM1 afterwards also can be more close, that is: if test finds that in test structure 2, through hole 24 is opened a way, then in SRAM1, through hole 14 is also opened a way, if test finds that in test structure 2, through hole 24 is communicated with the first metal layer 23, then in SRAM1, through hole 14 is also communicated with corresponding the first metal layer 13.Illustrate that this test structure 2 directly and more effectively can reflect the process condition of the through hole 14 of SRAM1 thus.
Finally carry out step S5, two through holes 24 laid respectively on adjacent the first metal layer 23 are connected by the second metal level 25, thus obtain the test structure 2 of chain type.
Chemical vapour deposition (CVD), physical vapour deposition (PVD), vacuum evaporation or other suitable depositing technics is adopted to prepare described second metal level 25.In the present embodiment, chemical vapor deposition method is adopted to prepare the second metal level 25.On the second metal level 25 insulating medium layer of being positioned at step S4 that preparation is formed and through hole 24, by the second metal level 25, two through holes 24 on adjacent the first metal layer 23 are communicated with, as shown in Figure 4.
Preferably, described second metal level 25 is copper or aluminum, also can be other any suitable metal materials.In the present embodiment, described second metal level 25 is copper product.
In addition, the space that the formation method of described test structure is also included in outside described substrate 21, shallow trench isolation regions 27, the first metal layer 23, through hole 24, second metal level 25 and polysilicon gate 26 forms insulating medium layer, prevents intermetallic from leaking electricity.
Embodiment two
The difference of the present embodiment and embodiment one is, formed described the first metal layer 23, through hole 24 and the second metal level 25 method different.The concrete grammar forming described the first metal layer 23, through hole 24 and the second metal level 25 in the present embodiment comprises:
First, as shown in Figure 7, form a bottom metal layers 23 ', the pattern of described bottom metal layers 23 ' is identical with the pattern of the first metal layer in SRAM1 13.
In described SRAM1, the pattern of the first metal layer 13 is determined by the SRAM domain of specific design, and different SRAM has different the first metal layer 13 patterns, and in the present embodiment, in described SRAM, the pattern of the first metal layer 13 as shown in Figure 6.
Be illustrated in figure 6 the structure vertical view of the first metal layer 13 in SRAM1.The bottom metal layers 23 ' of the test structure formed is identical with the patterning of the first metal layer in SRAM 13, and described bottom metal layers 23 ' as shown in Figure 7.
It should be noted that for the sake of simplicity, be illustrated in figure 7 Local map, intercepting be only a part in whole SRAM structure.Equally, Fig. 7 is also a part for test structure.
Then, the described bottom metal layers 23 ' of part arranges through hole 24, the position of the through hole 24 in described bottom metal layers 23 ' is corresponding consistent with the position of through hole 14 on the first metal layer in SRAM1 13, the position that in described SRAM1, through hole 14 distributes on the first metal layer 13 as shown in Figure 6, accordingly, as Fig. 7 shows bottom metal layers 23 ' in test structure and the upper through hole 24 arranged of section bottom metal level 23 '.
Described bottom metal layers 23 ' is arranged in the through hole 24 of same row, define every two through holes 24 and be divided into one group, each through hole only belongs to a group, exemplarily, as shown in Figure 7, be arranged in same a line through hole 241 and through hole 242 is divided into one group, through hole 243 and through hole 244 are divided into one group, and each group through hole is all connected by described second metal level 25.
Then, often organize bottom metal layers outside through hole 23 ' and lack disconnected place and add supplement metal wire 28 being arranged in same row, be arranged in same a line and often organize bottom metal layers 23 ' outside through hole and described supplement metal wire 28 forms described the first metal layer 23.
The bottom metal layers 23 ' that same a line breaks by supplement metal wire 28 as shown in Figure 7 is communicated with, the first metal layer 23 that described bottom metal layers 23 ' and supplement metal wire 28 are formed.
Remove the bottom metal layers of the part in the ranks that the supplement metal wire 28 of adjacent lines is connected again.Dotted portion is as shown in Figure 8 removed bottom metal layers 29, and after removing these bottom metal layers, the first metal layer 23 of adjacent lines is opened a way mutually, is independent of each other.
Finally the head end of adjacent lines or tail end are passed through metal wire 30 to be in the ranks connected, form described chain type test structure, as shown in Figure 7.
Therefore, the present embodiment improves the test structure becoming needs on the architecture basics of SRAM, section bottom metal level is only had to participate in defining the test structure of chain type in this test structure, and have the bottom metal layers of part and have neither part nor lot in the test structure forming chain type, such as, virtual bottom metal layers 231 in Fig. 7, but the existence of this bottom metal layers better can simulate the structural environment of SRAM, makes the via process situation of test structure effectively reflect the process condition of SRAM through hole.
In addition, the space that the formation method of described test structure is also included in outside described substrate 21, shallow trench isolation regions 27, the first metal layer 23, through hole 24, second metal level 25 and polysilicon gate 26 is formed with insulating medium layer (diagram), avoids intermetallic electric leakage.
Existing test structure is the chain structure of a rule, as shown in Figure 2.And utilize the chain structure that the formation method of the present embodiment is formed, although the structure presented in appearance is not as existing rule, as shown in Figure 7, but its structure distribution is more close to the structural environment of SRAM, so test structure of the present invention can reflect the process condition of through hole in SRAM more accurately.
Embodiment three
The present invention also provides a kind of test structure of monitoring SRAM through hole open circuit, and this test structure utilizes the formation method of embodiment one to be made, and as shown in Figure 4, described test structure at least comprises:
Substrate 21;
Shallow trench isolation regions 27, is formed in described substrate 21;
Contact hole 22, is formed on described shallow trench isolation regions 27, and the height of described contact hole 22 equals the height of contact hole in SRAM;
The first metal layer 23, is formed on described contact hole 22;
Through hole 24, is formed at the surperficial two ends of described the first metal layer 23;
Second metal level 25, between the through hole 24 being connected to adjacent the first metal layer 23 two ends, thus forms the test structure of chain type.
Described substrate 21 comprises silicon substrate, silicon-on-insulator substrate (SOI) or other semi-conducting materials.In the present embodiment, described substrate 21 is preferably silicon substrate.
The insulating dielectric materials of described shallow trench isolation regions 27 is silicon dioxide, but is not limited thereto, and also can be other insulating material.
In order to make test structure and SRAM structure more close, the substrate 21 between the shallow trench isolation regions 27 of described test structure is formed with polysilicon gate 26.Certainly, between polysilicon gate 26 and substrate 21, one deck grid oxygen can also be prepared.
In addition, space in test structure except described substrate 21, shallow trench isolation regions 27, the first metal layer 23, through hole 24, second metal level 25 and polysilicon gate 26 is formed with insulating medium layer (diagram), and this insulating medium layer can prevent intermetallic from leaking electricity.
Preferably, described the first metal layer 23 is copper or aluminum, also can be other any suitable metal materials.In the present embodiment, described the first metal layer 23 is copper product.
Preferably, described second metal level 25 is copper or aluminum, also can be other any suitable metal materials.In the present embodiment, described second metal level 25 is copper product.
In addition, it should be noted that, utilize test structure that the formation method of embodiment two is made as shown in Figure 7.Preferably, also comprise in described test structure and to be in the first metal layer 23 in same aspect and virtual bottom metal layers 231 for simulating SRAM the first metal layer patterning.
In sum, the invention provides a kind of test structure and forming method thereof of monitoring SRAM through hole open circuit, this test structure by increasing the height contact hole equal with SRAM contact hole height in test structure, make the first metal layer in test structure in the first metal layer and SRAM contour, expose form via hole image time indifference; On the other hand, by simulating the structural environment of SRAM, make the structure of test structure and SRAM more close, such test structure can reflect the via process situation of SRAM more.
So the present invention effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.
Claims (11)
1., for monitoring a formation method for the test structure of SRAM through hole open circuit, it is characterized in that, the formation method of described test structure at least comprises:
One substrate is provided, in described substrate, forms at least two shallow trench isolation regions;
On each shallow trench isolation regions, form contact hole, the height of described contact hole equals the height of contact hole in SRAM;
The first metal layer is formed on described each contact hole;
A through hole is respectively arranged with in the surperficial two ends of described each the first metal layer;
Two through holes laid respectively on two adjacent the first metal layers are connected by the second metal level, thus obtain the test structure of chain type.
2. the formation method of the test structure of monitoring SRAM through hole open circuit according to claim 1, is characterized in that: after forming described shallow trench isolation regions, the substrate between adjacent shallow trench isolation regions forms polysilicon gate.
3. the formation method of the test structure of monitoring SRAM through hole open circuit according to claim 1, is characterized in that: the step forming described contact hole comprises:
Deposit one insulating medium layer over the substrate, the consistency of thickness of the insulating medium layer of correspondence position in the thickness of described insulating medium layer and SRAM;
Etch described insulating medium layer until expose substrate, thus formed contact hole, and in contact hole filled conductive material, now, the contact hole height of making equals the height of contact hole in SRAM.
4. the formation method of the test structure of monitoring SRAM through hole open circuit according to claim 3, is characterized in that: the altitude range of described contact hole is 900 ~ 1800 dusts.
5. the formation method of the test structure of monitoring SRAM through hole open circuit according to claim 1, it is characterized in that: described the first metal layer is copper product, described second metal level is copper product.
6. the formation method of the test structure of monitoring SRAM through hole open circuit according to claim 1, is characterized in that: the concrete steps forming described the first metal layer, through hole and the second metal level comprise:
Form a bottom metal layers, the pattern of described bottom metal layers is identical with the pattern of the first metal layer in SRAM;
The described bottom metal layers of part arranges through hole, and the position of the through hole in described bottom metal layers is corresponding consistent with the position of through hole on the first metal layer in SRAM; Described bottom metal layers is arranged in the through hole of same row, often adjacent two through holes are divided into one group, and each through hole only belongs to a group, and often organize through hole all by described second metal level connection;
Often organize the disconnected place of bottom metal break outside through hole and add supplement metal wire being arranged in same row; Be arranged in same a line and often organize bottom metal layers outside through hole and described supplement metal wire forms described the first metal layer;
Remove the bottom metal layers of the part in the ranks that the supplement metal wire of adjacent lines is connected;
The head end of adjacent lines or tail end are connected by the ranks metal wire, form the test structure of described chain type.
7. monitor a test structure for SRAM through hole open circuit, it is characterized in that: described test structure at least comprises:
Substrate;
Shallow trench isolation regions, is formed in described substrate;
Contact hole, is formed on described shallow trench isolation regions, and the height of described contact hole equals the height of contact hole in SRAM;
The first metal layer, is formed on described contact hole;
Through hole, is formed at the surperficial two ends of described the first metal layer;
Second metal level, is connected between two through holes on two adjacent the first metal layers, thus forms the test structure of chain type.
8. the test structure of monitoring SRAM through hole open circuit according to claim 7, is characterized in that: the substrate between described shallow trench isolation regions is formed with polysilicon gate.
9. the test structure of the monitoring SRAM through hole open circuit according to claim 7 or 8, is characterized in that: the space outside substrate described in test structure, shallow trench isolation regions, the first metal layer, through hole, the second metal level and grid is filled with insulating medium layer.
10. the test structure of monitoring SRAM through hole open circuit according to claim 7, is characterized in that: also comprise in described test structure and to be in the first metal layer in same aspect and virtual bottom metal layers for simulating SRAM the first metal layer patterning.
The test structure of 11. monitoring SRAM through hole open circuits according to claim 7, it is characterized in that: described the first metal layer is copper product, described second metal level is copper product.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104091800A (en) * | 2014-07-25 | 2014-10-08 | 上海华力微电子有限公司 | Forming method for SRAM detection structure map |
| CN111816639A (en) * | 2020-07-17 | 2020-10-23 | 上海华虹宏力半导体制造有限公司 | Test structure for monitoring alignment failure of through holes in SRAM storage area |
| CN112928038A (en) * | 2021-01-25 | 2021-06-08 | 长江存储科技有限责任公司 | Detection method |
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| CN201017877Y (en) * | 2007-03-06 | 2008-02-06 | 中芯国际集成电路制造(上海)有限公司 | Staged thru hole chain structure easy to test reliability |
| CN102760726A (en) * | 2011-04-27 | 2012-10-31 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor detection structure, as well as forming method and detection method thereof |
| CN103094255A (en) * | 2013-02-27 | 2013-05-08 | 上海华力微电子有限公司 | Interconnection electromigration test structure |
| CN103839921A (en) * | 2012-11-26 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Through si via radio frequency test structure and parasitic extracting method thereof |
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2013
- 2013-08-26 CN CN201310376738.3A patent/CN104425293B/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030219588A1 (en) * | 2002-04-03 | 2003-11-27 | Makoto Ogawa | Dielectric film for printed wiring board, multilayer printed board, and semiconductor device |
| JP2004228510A (en) * | 2003-01-27 | 2004-08-12 | Fab Solution Kk | Semiconductor device and method of controlling semiconductor manufacturing process |
| CN201017877Y (en) * | 2007-03-06 | 2008-02-06 | 中芯国际集成电路制造(上海)有限公司 | Staged thru hole chain structure easy to test reliability |
| CN102760726A (en) * | 2011-04-27 | 2012-10-31 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor detection structure, as well as forming method and detection method thereof |
| CN103839921A (en) * | 2012-11-26 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Through si via radio frequency test structure and parasitic extracting method thereof |
| CN103094255A (en) * | 2013-02-27 | 2013-05-08 | 上海华力微电子有限公司 | Interconnection electromigration test structure |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104091800A (en) * | 2014-07-25 | 2014-10-08 | 上海华力微电子有限公司 | Forming method for SRAM detection structure map |
| CN111816639A (en) * | 2020-07-17 | 2020-10-23 | 上海华虹宏力半导体制造有限公司 | Test structure for monitoring alignment failure of through holes in SRAM storage area |
| CN112928038A (en) * | 2021-01-25 | 2021-06-08 | 长江存储科技有限责任公司 | Detection method |
| CN112928038B (en) * | 2021-01-25 | 2022-06-17 | 长江存储科技有限责任公司 | Detection method |
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