CN112928038B - Detection method - Google Patents
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- CN112928038B CN112928038B CN202110097612.7A CN202110097612A CN112928038B CN 112928038 B CN112928038 B CN 112928038B CN 202110097612 A CN202110097612 A CN 202110097612A CN 112928038 B CN112928038 B CN 112928038B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
Abstract
The invention provides a detection method, which comprises the steps of sequentially forming a first insulating layer, a first gate layer and a first covering layer on a substrate, wherein the height of the first covering layer is determined according to a second covering layer on a second gate layer of a preset layer of a wafer to be detected, the materials of the first covering layer and the second covering layer are the same, the materials of the first gate layer and the second gate layer of the preset layer are the same, and a first through hole in the first covering layer and a second through hole in the second covering layer are etched by using the same etching parameters; and the first through hole penetrates through the first gate layer to ensure that the second through hole penetrates through the second gate layer of the preset layer. The second gate layer of the preset layer of the wafer to be detected and the second covering layer on the second gate layer of the preset layer are simulated on the substrate, the etching condition of the second through hole in the second covering layer of the wafer to be detected is determined through the etching condition of the first through hole in the first covering layer, a stacking layer below the second gate layer of the preset layer of the wafer to be detected does not need to be formed on the substrate, the detection process is simplified, and the manufacturing period is shortened.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a detection method.
Background
In a 3D NAND memory, the memory array may include a core (core) region and a staircase (SS) region. The step region is used for leading out a contact part of a control gate in each layer of the memory array and is used as a word line connection region. These control gates are used as word lines of the memory array to perform programming, erasing, reading, etc.
In the manufacturing process of the 3D NAND memory, contact holes are formed on all levels of stepped structures in a stepped area in an etching mode, and then contact parts are filled, so that control gates are led out. In the actual production process, it is not easy to realize that the contact hole just falls on the step structure, and there may be a defect of Punch Through (Punch Through).
The existing method for detecting the defect of etching through is to detect the defect of etching through of the conductive capability of a contact hole through an electron beam scanning detection machine (e-beam) after the contact hole is filled with a conductive substance or after a chip is manufactured, but the method needs to consume a long time.
Disclosure of Invention
In view of the above, the present invention provides a detection method to shorten the time for detecting the etching punch-through of the contact hole.
In order to achieve the purpose, the invention has the following technical scheme:
a method of detection, comprising:
providing a substrate, wherein a first insulating layer, a first gate layer and a first covering layer are sequentially formed on the substrate, and a first through hole is formed in the first covering layer;
the height of the first covering layer is determined according to a second covering layer on a second grid layer of a preset layer of the wafer to be tested;
the first covering layer and the second covering layer are made of the same material, the first gate layer and the second gate layer of the preset layer are made of the same material, a second through hole is formed in the second covering layer, and the first through hole and the second through hole are obtained by etching through the same etching parameters;
and the first through hole penetrates through the first gate layer to ensure that the second through hole penetrates through the second gate layer of the preset layer.
Optionally, the determining that the second via penetrates through the second gate layer by the first via penetrating through the first gate layer includes:
determining that the first via penetrates through the first gate layer by damage of the first insulating layer to determine that the second via penetrates through the second gate layer.
Optionally, the first insulating layer and the first cover layer are made of the same material;
said determining that said first via penetrates said first gate layer by damage to said first insulating layer comprises:
carrying out wet etching treatment on the first covering layer to remove the first covering layer;
the first via is determined to penetrate the first gate layer by damage of the first insulating layer.
Optionally, the first cover layer is made of silicon oxide;
the wet etching treatment of the first cover layer to remove the first cover layer comprises:
and carrying out wet etching treatment on the first covering layer by using a hydrofluoric acid solution to remove the first covering layer.
Optionally, the material of the first gate layer and the second gate layer is metal tungsten.
Optionally, the determining that the first via penetrates through the first gate layer by the damage of the first insulating layer includes:
removing the first gate layer;
the first via is determined to penetrate the first gate layer by damage of the first insulating layer.
Optionally, a first isolation layer is formed between the first insulating layer and the first gate layer, and a second isolation layer is formed between the first gate layer and the first capping layer;
then, after the wet etching process is performed on the first capping layer to remove the first capping layer, the method further includes:
removing the second isolation layer on the first gate layer;
after the removing the first gate layer, further comprising:
and removing the first isolation layer on the first insulating layer.
Optionally, the first isolation layer and the second isolation layer are made of aluminum oxide.
Optionally, a first adhesion layer is formed between the first isolation layer and the first gate layer, and a second adhesion layer is formed between the second isolation layer and the first capping layer;
then, before removing the second isolation layer on the first gate layer, further comprising;
removing the second adhesive layer on the second release layer;
before removing the first isolation layer on the first insulating layer, the method further includes:
and removing the first adhesive layer on the first insulating layer.
Optionally, the material of the first adhesion layer and the second adhesion layer is titanium nitride.
The detection method provided by the embodiment of the invention comprises the following steps: providing a substrate, wherein a first insulating layer, a first gate layer and a first covering layer are sequentially formed on the substrate, and a first through hole is formed in the first covering layer; the height of the first covering layer is determined according to the height of a second covering layer on a second grid layer of a preset layer of the wafer to be tested, the first covering layer and the second covering layer are made of the same material, the first grid layer and the second grid layer of the preset layer are made of the same material, a second through hole is formed in the second covering layer, and the first through hole and the second through hole are obtained by etching with the same etching parameters; and the first through hole penetrates through the first gate layer to ensure that the second through hole penetrates through the second gate layer of the preset layer. Therefore, the second gate layer of the preset layer of the wafer to be detected and the second covering layer on the second gate layer of the preset layer are simulated on the substrate, the etching condition of the second through hole in the second covering layer of the wafer to be detected is determined through the etching condition of the first through hole in the first covering layer on the substrate, a stacking layer below the second gate layer of the preset layer of the wafer to be detected does not need to be formed on the substrate, the detection process is simplified, and the manufacturing period is shortened.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 shows a schematic diagram of a 3D NAND memory device;
fig. 2-5 show schematic structural diagrams of a detection structure according to an embodiment of the invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described and will be readily apparent to those of ordinary skill in the art without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.
As described in the background art, the conventional method for detecting the etch through defect is to detect the conductivity of the contact hole through an electron beam scanning inspection machine (e-beam) after the contact hole is filled with a conductive material or after the chip is manufactured, but the method takes a long time.
Therefore, the embodiment of the present application provides a detection method, in which a second gate layer of a preset layer of a wafer to be detected and a second cover layer on the second gate layer of the preset layer are simulated on a substrate, and an etching condition of a second through hole in the second cover layer of the wafer to be detected is determined according to an etching condition of a first through hole in the first cover layer on the substrate, so that a stacked layer under the second gate layer of the preset layer of the wafer to be detected does not need to be formed on the substrate, the detection process is simplified, and the manufacturing cycle is shortened.
In order to better understand the detection method provided by the embodiment of the present application, a description is first made of a manufacturing process of a related 3D NAND memory.
In forming the 3D NAND memory, first, a stack layer in which insulating layers and sacrificial layers are alternately stacked is formed on a substrate, the insulating layers may be, for example, silicon oxide, and the sacrificial layers may be silicon nitride. The stack is then etched to form a channel hole in the stack, the channel hole being used to form a memory structure. Specifically, an epitaxial structure may be formed at the bottom of the channel hole by Selective Epitaxial Growth (SEG), and then a memory structure may be formed on the epitaxial structure. The epitaxial structure plays a role in connecting the storage structure and supporting the storage structure. The storage structure comprises a storage function layer and a channel layer, wherein the storage function layer comprises a blocking layer, a charge capturing layer and a tunneling layer which are sequentially stacked, the blocking layer, the charge capturing layer and the tunneling layer can be specifically ONO stacked layers, namely stacked layers of silicon oxide-silicon nitride-silicon oxide, and the channel layer can be a polysilicon layer. A fill layer of insulating material, such as silicon oxide, may also be formed between the channel layers. And after a channel structure is formed in the channel holes, etching the stacked layer between the channel holes to form a grid line gap, and removing the sacrificial layer in the stacked structure by using the grid line gap to form a hollow structure. And filling metal in the hollow structure to form a gate layer, thereby forming a stack layer in which the insulating layer and the gate layer are alternately stacked. The stack layer comprises a core storage area and a step area, the core storage area is generally arranged in the middle area of the stack layer, the step area is generally arranged on the periphery of the core storage area, and the step areas on two sides of the core storage area are used for forming contact of the grid layer in the extending direction of the core storage area. Specifically, after a stacked layer in which an insulating layer and a gate electrode layer are alternately stacked is formed, a capping layer covering the step region is formed, and then the capping layer is etched to form a contact of the gate electrode layer in the capping layer. The step area is formed with the subregion step, and the subregion step all is formed with the step along the direction that the core storage area extends and the direction of perpendicular to core storage area extending direction to, can reduce step area, improve the device integrated level. Of course, a contact of the gate layer is formed on the step in the extending direction of the core storage area, a contact of the gate layer is also formed on the step in the direction perpendicular to the extending direction of the core storage area, and a corresponding contact is formed on each step.
In order to detect the existence of etching through in the contact of the gate layer, the embodiment of the present application provides a detection method, which is shown in fig. 2 to fig. 5 and includes:
providing a substrate, wherein a first insulating layer, a first gate layer and a first covering layer are sequentially formed on the substrate, and a first through hole is formed in the first covering layer;
the height of the first covering layer is determined according to a second covering layer on a second grid layer of a preset layer of the wafer to be tested;
the first covering layer and the second covering layer are made of the same material, the first gate layer and the second gate layer are made of the same material, a second through hole is formed in the second covering layer, and the first through hole and the second through hole are obtained by etching through the same etching parameters;
the second via is defined through the second gate layer by the first via penetrating the first gate layer.
In the embodiment of the present application, referring to fig. 2 and fig. 3, a substrate 100 is provided, a first insulating layer 102, a first gate layer 108 and a first capping layer 114 are sequentially formed on the substrate 100, and a first via 116 is formed in the first capping layer 114.
The substrate 100 is a semiconductor substrate, and may be, for example, a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator) or a GOI (Germanium On Insulator) substrate. In other embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, such as GaAs, InP, SiC, or the like, may also be a stacked structure, such as Si/SiGe, or the like, and may also be another epitaxial structure, such as SGOI (silicon germanium on insulator), or the like. In the present embodiment, the substrate 100 is a silicon substrate.
In order to improve the accuracy of the detection result, the material of the first insulating layer 102 is the same as that of the insulating layers of the stacked layers in the 3D NAND memory, and the process of forming the first insulating layer 102 on the substrate 100 is the same as that of forming the insulating layers of the stacked layers in the 3D NAND memory, for example, a chemical vapor deposition process may be used to deposit an insulating material on the substrate 100 to form the first insulating layer 102.
For convenience of description, the device structure to be tested is referred to as a wafer to be tested, and referring to fig. 1, a contact hole to be tested in the wafer to be tested is referred to as a second via hole 216, a gate layer corresponding to the contact hole to be tested in the wafer to be tested is referred to as a second gate layer 208 of a predetermined layer, a covering layer on the second gate layer 208 of the predetermined layer is referred to as a second covering layer 214, and an insulating layer under the second gate layer 208 of the predetermined layer is referred to as a second insulating layer 206. The material of the first insulating layer 102 is the same as that of the second insulating layer 206, and is, for example, silicon oxide.
Subsequently, a first gate layer 108 is formed on the first insulating layer 102, and similarly, the material of the first gate layer 108 is the same as the height and the material of the gate layer in the stacked structure of the wafer to be tested, that is, the material of the first gate layer 108 is the same as the height and the material of the second gate layer 208 of the predetermined layer, for example, metal tungsten, and the process for forming the first gate layer 108 may be the same as the process for forming the second gate layer 208 of the predetermined layer, so as to improve the consistency between the simulation structure and the wafer structure to be tested, and further improve the test result. The simulated structure at this point includes the substrate 100, and the first insulating layer 102, the first gate layer 108, and the first capping layer 114 on the substrate 100.
After forming the first gate layer 108, a first capping layer 114 is formed on the first gate layer 108. The material and height of the first capping layer 114 are the same as those of the capping layer on the gate layer corresponding to the contact hole to be tested of the wafer to be tested, i.e., the height and material of the first capping layer 114 are the same as those of the second capping layer 214 on the second gate layer 208 of the predetermined layer of the wafer to be tested. The height of the first capping layer 114 is determined according to the height of the second capping layer 214 on the second gate layer 208 of the predetermined layer of the wafer to be tested, so that the same process as that for forming the contact hole of the second gate layer 214 of the predetermined layer can be maintained when the first capping layer 114 is etched to form the first via hole 116 in the first capping layer 114, and specifically, since the height of the first capping layer 114 is the same as that of the second capping layer 214 and the material of the first capping layer 114 is the same as that of the second capping layer 214, the same etching parameters as those for forming the contact hole on the wafer to be tested, i.e., the second via hole 216 in the second capping layer 214, are used when the first capping layer 114 is etched, so that the first via hole 116 formed in the first capping layer 114 and the second via hole 216 in the second capping layer 214 have the same or similar topography.
The process of forming the first through hole 116 may be to spin a photoresist layer on the first cover layer 102, and transfer a pattern on the mask to the photoresist layer through processes such as exposure and development, where the pattern is a pattern of the second through hole, so as to obtain a patterned photoresist layer. Then, an etching process, for example, reactive ion etching, is performed to etch the first capping layer 102, so as to form a first via 116 in the first capping layer 102. Subsequently, the photoresist layer is removed.
Since the process, height, material, and the like of the first gate layer 108 formed on the substrate 100 are the same as those of the second gate layer 208 of the preset layer of the wafer to be tested, and the process, height, material, and the like of the first cover layer 114 on the first gate layer 108 are the same as those of the second cover layer 214 on the second gate layer 208 of the preset layer, the topography of the first through hole 116 in the first cover layer 114 is the same as or similar to that of the contact hole to be tested of the wafer to be tested, so that it can be determined that the second through hole 216 penetrates through the second gate layer 208 of the preset layer through the first through hole 116, that is, it is determined that the contact hole to be tested in the wafer to be tested has the defect of etching through the through hole in the simulation structure.
In this embodiment, the first via 116 may be determined to penetrate through the first gate layer 108 by damage of the first insulating layer 102 to determine the second via 216 to penetrate through the second gate layer 208. It is clear that when the first insulating layer 102 is damaged, the first via 116 penetrates through the first gate layer 108 into the first insulating layer 102 or onto the first insulating layer 102, thereby defining a second via 216 penetrating through the second gate layer 208 of the predetermined layer into the second insulating layer 206 or onto the second insulating layer 206. Specifically, the material of the first insulating layer 102 and the first capping layer 114 may be selected to be the same material, wet etching is performed on the first capping layer 114 to remove the first capping layer 114, as shown in fig. 4, and then whether the first insulating layer 102 is damaged or not is detected. Since the material of the first insulating layer 102 is the same as the material of the first capping layer 114, if the first via 116 penetrates through the first gate layer 108 into or on the first insulating layer 102, the first insulating layer 102 may be damaged during the removal of the first capping layer 114, and if the first via 116 does not penetrate through the first gate layer 108, the first insulating layer 102 may not be damaged during the removal of the first capping layer 114, so that it may be determined that the first via 116 penetrates through the first gate layer 108 into or on the first insulating layer 102 due to the damage of the first insulating layer 102. For example, the material of the first insulating layer 102 and the material of the first cover layer 114 are silicon oxide, and the first cover layer 114 may be wet-etched by using a hydrofluoric acid solution to remove the first cover layer 114.
To facilitate checking the damage of the first insulating layer 102, the first gate layer 108 may be removed after removing the first capping layer 114, as shown in fig. 5, and then the first via 116 is determined to penetrate through the first gate layer 108 by the damage of the first insulating layer 102. After the first gate layer 108 is removed, the surface of the first insulating layer 102 can be directly inspected, so that the inspection result is more intuitive. If the first insulating layer 102 is damaged in the process of removing the first capping layer 114, the surface of the first insulating layer 102 has defects, and the etching condition of the first via 116 can be obtained by inspecting the surface of the first insulating layer 102.
Usually, an isolation layer is disposed between an insulating layer and a gate layer in a stack of a wafer to be tested, so as to prevent a metal in the gate layer from diffusing into the insulating layer. Therefore, the first isolation layer 104 is formed between the first insulating layer 102 and the first gate layer 108, and the second isolation layer 110 is formed between the first gate layer 108 and the first capping layer 114, so that the simulation structure is closer to the structure of the wafer to be tested, and the accuracy of determining the etching condition of the contact hole in the wafer to be tested through the etching condition of the through hole in the simulation structure is improved. The materials of the first isolation layer 104 and the second isolation layer 110 are the same as those of the isolation layer between the gate layer and the insulation layer in the stack layer of the wafer to be tested, the first isolation layer 104 and the second isolation layer 110 may be high-k dielectric layers, such as aluminum oxide, and the processes for forming the first isolation layer 104 and the second isolation layer 110 are the same as those of the isolation layer in the wafer to be tested. Then, the first via 116 may be determined to penetrate through the first gate layer 108 and the first isolation layer 104 into or on the first insulating layer 102 by the damage of the first insulating layer 102. Thus, after the wet etching process is performed on the first capping layer 114 to remove the first capping layer 114, the second isolation layer 110 on the first gate layer 108 is removed, and after the first gate layer 108 is removed, the first isolation layer 104 under the first gate layer 108 is removed to expose the first insulating layer 102. Subsequently, the surface of the first insulating layer 102 is inspected, and when the first insulating layer 102 is damaged, a first via 116 is determined to penetrate through the first gate layer 108 and the first isolation layer 104 into or on the first insulating layer 102.
In a specific application, after the sacrificial layer in the stack layer of the wafer to be tested is removed to form the hollow structure, after the isolation layer is formed in the hollow structure, before the gate layer is formed by filling metal tungsten, an adhesive layer is formed on the isolation layer, so that the stability of the device is improved. Thus, the first adhesion layer 106 may be formed between the first isolation layer 104 and the first gate layer 108, and the second adhesion layer 112 may be formed between the second isolation layer 110 and the first capping layer 114. The first adhesion layer 106 and the second adhesion layer 112 are made of the same material as the adhesion layer in the wafer to be tested, such as titanium nitride, and the process of forming the first adhesion layer 106 and the second adhesion layer 112 is the same as the process of forming the adhesion layer in the wafer to be tested. Then, the first via 116 may be determined to penetrate through the first gate layer 108, the first adhesion layer 106, and the first isolation layer 104 into or on the first insulating layer 102 by the damage of the first insulating layer 102. Thus, after the wet etching process is performed on the first capping layer 114 to remove the first capping layer 114, and before the second isolation layer 110 on the first gate layer 108 is removed, the second adhesion layer 112 on the second isolation layer 110 may also be removed. The first adhesive layer 106 on the first insulating layer 102 is removed before the first isolation layer 104 on the first insulating layer 102 is removed.
The above detailed description is provided for a detection method provided in the embodiment of the present application, and the method includes: providing a substrate, wherein a first insulating layer, a first gate layer and a first covering layer are sequentially formed on the substrate, and a first through hole is formed in the first covering layer; the height of the first covering layer is determined according to a second covering layer on a second grid layer of a preset layer of the wafer to be tested, the first covering layer and the second covering layer are made of the same material, the first grid layer and the second grid layer of the preset layer are made of the same material, a second through hole is formed in the second covering layer, and the first through hole and the second through hole are obtained by etching with the same etching parameters; and the first through hole penetrates through the first gate layer to ensure that the second through hole penetrates through the second gate layer of the preset layer. Therefore, the second gate layer of the preset layer of the wafer to be detected and the second covering layer on the second gate layer of the preset layer are simulated on the substrate, the etching condition of the second through hole in the second covering layer of the wafer to be detected is determined through the etching condition of the first through hole in the first covering layer on the substrate, a stacking layer below the second gate layer of the preset layer of the wafer to be detected does not need to be formed on the substrate, the detection process is simplified, and the manufacturing period is shortened.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments.
The foregoing is only a preferred embodiment of the present invention, and although the present invention has been disclosed in the preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make numerous possible variations and modifications to the present teachings, or modify equivalent embodiments to equivalent variations, without departing from the scope of the present teachings, using the methods and techniques disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
Claims (9)
1. A method of detection, comprising:
providing a substrate, wherein a first insulating layer, a first gate layer and a first covering layer are sequentially formed on the substrate, and a first through hole is formed in the first covering layer;
the height of the first covering layer is determined according to a second covering layer on a second grid layer of a preset layer of the wafer to be tested;
the first covering layer and the second covering layer are made of the same material, the first gate layer and the second gate layer of the preset layer are made of the same material, a second through hole is formed in the second covering layer, and the first through hole and the second through hole are obtained by etching through the same etching parameters;
determining that the second through hole penetrates through the second gate layer of the preset layer by penetrating through the first gate layer through the first through hole;
the determining that the second via penetrates through the second gate layer by the first via penetrating through the first gate layer comprises:
determining that the first via penetrates through the first gate layer by damage of the first insulating layer to determine that the second via penetrates through the second gate layer.
2. The method of claim 1, wherein the first insulating layer and the first capping layer are the same material;
said determining that said first via penetrates said first gate layer by damage to said first insulating layer comprises:
carrying out wet etching treatment on the first covering layer to remove the first covering layer;
the first via is determined to penetrate the first gate layer by damage of the first insulating layer.
3. The method of claim 2, wherein the material of the first capping layer is silicon oxide;
the wet etching the first cover layer to remove the first cover layer comprises:
and carrying out wet etching treatment on the first covering layer by using hydrofluoric acid solution to remove the first covering layer.
4. The method according to any of claims 1 to 3, wherein the material of the first gate layer and the second gate layer is tungsten metal.
5. The method of claim 2 or 3, wherein the determining that the first via penetrates the first gate layer through damage to the first insulating layer comprises:
removing the first gate layer;
the first via is determined to penetrate the first gate layer by damage of the first insulating layer.
6. The method according to claim 5, wherein a first isolation layer is formed between the first insulating layer and the first gate layer, and a second isolation layer is formed between the first gate layer and the first capping layer;
then, after the wet etching process is performed on the first capping layer to remove the first capping layer, the method further includes:
removing the second isolation layer on the first gate layer;
after the removing the first gate layer, further comprising:
and removing the first isolation layer on the first insulating layer.
7. The method of claim 6, wherein the material of the first and second isolation layers is aluminum oxide.
8. The method of claim 6, wherein a first adhesion layer is formed between the first isolation layer and the first gate layer, and a second adhesion layer is formed between the second isolation layer and the first capping layer;
then, before removing the second isolation layer on the first gate layer, further comprising;
removing the second adhesive layer on the second release layer;
before removing the first isolation layer on the first insulating layer, the method further includes:
and removing the first adhesive layer on the first insulating layer.
9. The method of claim 8, wherein a material of the first adhesion layer and the second adhesion layer is titanium nitride.
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| CN104051427A (en) * | 2013-03-13 | 2014-09-17 | 中芯国际集成电路制造(上海)有限公司 | Contact hole resistance test structure and method |
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| CN104143519A (en) * | 2014-08-01 | 2014-11-12 | 上海华力微电子有限公司 | Product through hole etching defect detection method |
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