CN110767659A - Memory and forming method thereof - Google Patents
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- CN110767659A CN110767659A CN201910916123.2A CN201910916123A CN110767659A CN 110767659 A CN110767659 A CN 110767659A CN 201910916123 A CN201910916123 A CN 201910916123A CN 110767659 A CN110767659 A CN 110767659A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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Abstract
The invention relates to a memory and a forming method thereof, wherein the forming method of the memory comprises the following steps: providing a substrate, wherein a stacking structure is formed on the substrate; forming a channel hole penetrating through the stacked structure to the surface of the substrate; forming a channel hole structure in the channel hole, wherein the channel hole structure comprises an epitaxial semiconductor layer positioned on the surface of the substrate at the bottom of the channel hole, a functional side wall covering the side wall of the channel hole, a channel layer covering the functional side wall and connected with the epitaxial semiconductor layer, and a channel medium layer filling the channel hole; etching the channel medium layer to a set height by adopting an isotropic etching process to expose part of the channel layer; and forming an electric contact part on the top of the etched back channel medium layer, wherein the electric contact part is electrically connected with the channel layer. The performance of the memory is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a memory and a forming method thereof.
Background
In recent years, Flash Memory (Flash Memory) memories have been developed particularly rapidly. The main characteristic of flash memory is that it can keep the stored information for a long time without power-up, and it has the advantages of high integration level, fast access speed, easy erasing and rewriting, so it is widely used in microcomputer, automation control and other fields. In order to further improve the Bit Density (Bit Density) of the flash memory and simultaneously reduce the Bit Cost (Bit Cost), the three-dimensional flash memory (3DNAND) technology has been rapidly developed.
In the 3D NAND forming process, after a stacking structure is required to be formed on the surface of a substrate, etching the stacking structure to form a channel hole, and forming a channel hole structure in the channel hole, wherein the channel hole structure comprises a functional side wall covering the side wall of the channel hole, a channel layer and a channel medium layer filled in the channel hole; and then etching the channel medium layer again to expose the channel layer on the side wall of the top of the channel hole, and filling the top of the channel medium layer with a polysilicon layer to serve as a contact part connected with the channel layer.
In the prior art, in the process of etching back a channel medium layer to form a contact part, poor contact between the contact part and a channel layer is easily caused, and the electrical performance defect of a memory is caused.
Therefore, the performance of the prior art memory is yet to be further improved.
Disclosure of Invention
The invention aims to provide a memory and a forming method thereof, which can improve the performance of the memory.
The invention provides a forming method of a memory, which comprises the following steps: providing a substrate, wherein a stacking structure is formed on the substrate; forming a channel hole penetrating through the stacked structure to the surface of the substrate; forming a channel hole structure in the channel hole, wherein the channel hole structure comprises an epitaxial semiconductor layer positioned on the surface of the substrate at the bottom of the channel hole, a functional side wall covering the side wall of the channel hole, a channel layer covering the functional side wall and connected with the epitaxial semiconductor layer, and a channel medium layer filling the channel hole; etching the channel medium layer to a set height by adopting an isotropic etching process to expose part of the channel layer; and forming an electric contact part on the top of the etched back channel medium layer, and forming electric connection between the electric contact part and the channel layer.
Optionally, an air gap is formed in the tunnel dielectric layer, and the air gap is located below the set height.
Optionally, a height difference between the top of the air gap and the set height is greater than or equal to 90 nm.
Optionally, the channel dielectric layer is formed by an atomic layer deposition process.
Optionally, the isotropic etching process at least includes a wet etching process.
Optionally, the method for performing back etching on the channel dielectric layer includes: etching the channel dielectric layer by adopting a wet etching process; and continuing to adopt a gas etching process, and further etching the channel dielectric layer back to the set height by utilizing the reaction of gas molecules and the channel dielectric layer.
Optionally, the method for performing back etching on the channel dielectric layer includes: and etching the channel dielectric layer to the set height by only adopting a wet etching process.
Optionally, the method further includes: and cleaning the exposed channel layer.
Optionally, the middle of the side wall of the channel hole protrudes outwards.
The technical solution of the present invention also provides a memory, including: the structure comprises a substrate, wherein a stacking structure and a channel hole structure penetrating through the stacking structure to the surface of the substrate are formed on the substrate, the channel hole structure comprises an epitaxial semiconductor layer positioned on the surface of the substrate at the bottom of a channel hole, a functional side wall covering the side wall of the channel hole, a channel layer covering the functional side wall and connected with the epitaxial semiconductor layer, and a channel medium layer filling the channel hole, the top of the channel medium layer is lower than the top of the channel layer, part of the channel layer is exposed, and the channel medium layer is provided with a top surface etched by an anisotropic etching process; a contact located on top of the channel dielectric layer, the contact forming an electrical connection with the channel layer.
Optionally, an air gap is formed in the channel dielectric layer, and the air gap is located in the channel dielectric layer.
Optionally, a height difference between the top of the air gap and the top of the tunnel dielectric layer is greater than or equal to 90 nm.
Optionally, the channel dielectric layer is an atomic layer deposition layer.
Optionally, the anisotropic etching process at least includes a wet etching process.
Optionally, the anisotropic etching process includes a wet etching process and a gas etching process after the wet etching process.
Optionally, the middle part of the side wall of the channel structure protrudes outwards.
According to the forming method of the memory, the channel medium layer is etched back through the isotropic etching process, so that etching damage to the exposed channel layer is reduced, the surface appearance quality of the channel layer is improved, the interface quality of the contact part formed on the channel medium layer and the channel layer is improved, the electrical contact performance of the electrical contact part and the channel layer is improved, and the performance of the memory is further improved.
Furthermore, in the process of forming the channel dielectric layer, the air gap in the channel dielectric layer is controlled to be positioned below the set height, so that the air gap is prevented from being exposed in the process of back etching the channel dielectric layer, and the electrical property defect caused by the fact that the electrical contact part is formed in the air gap is avoided.
Drawings
Fig. 1a to 4 are schematic structural diagrams illustrating a memory formation process according to an embodiment of the invention.
Detailed Description
As described in the background, the contact electrical performance between the channel layer and the top contact of the channel hole structure of the prior art formed memory devices is prone to defects. The inventor finds that the reason is that the channel medium layer is usually etched back by adopting a dry etching process at present, and the channel layer is easily damaged in the back etching process, so that the channel layer is too thin, and when a contact part is formed, the interface quality of the contact part and the channel layer is poor, and finally, the electrical property defect is caused. And the dry etching process is adopted to etch back the channel dielectric layer, matched subsequent equipment is also needed, a plurality of equipment is needed during large-scale mass production, and the production cost is higher.
Accordingly, the applicant proposes a new memory and a method of forming the same to overcome the above-mentioned problems.
The following detailed description of embodiments of the memory and the method for forming the same according to the present invention will be made with reference to the accompanying drawings.
Please refer to fig. 1a to fig. 4, which are schematic structural diagrams illustrating a memory formation process according to an embodiment of the invention.
Referring to fig. 1a, a substrate 100 is provided, wherein a stacked structure 110 is formed on the substrate 100; a channel hole 130 is formed through the stacked structure 110 to the surface of the substrate 100.
The substrate 100 may be a single crystal silicon substrate, a Ge substrate, a SiGe substrate, an SOI, a GOI, or the like; according to the actual requirements of the device, a suitable semiconductor material may be selected as the substrate 100, which is not limited herein. In this embodiment, the substrate 100 is a single crystal silicon wafer.
The stack structure 110 includes an insulating layer 111 and a sacrificial layer 112 stacked on each other in a direction perpendicular to the surface of the substrate 100. In one embodiment, the material of the insulating layer 111 is silicon oxide, and the material of the sacrificial layer 112 is silicon nitride; in other embodiments, other suitable materials for the insulating layer 111 and the sacrificial layer 112 may be used. In another embodiment, the stacked structure 110 includes conductive layers and insulating layers stacked alternately, for example, the conductive layers may be control gates.
The stack structure 110 may be etched to the surface of the semiconductor substrate 100 using a reactive ion etching process. In this embodiment, in the process of etching the stacked structure, the etching selection ratio of the adopted etching process to the stacked structure to the substrate is greater than 100, so that the etching can be stopped in time after the stacked structure 110 is etched to the surface of the semiconductor substrate 100, and excessive etching to the substrate 100 is avoided.
During the etching process, the parameters of the etching process may be adjusted to avoid etching the substrate 100. Firstly, a gas with high etching selectivity on the material layers in the stacked structure 100, especially on the insulating layer 111, is selected to etch the stacked structure 100, so that when the insulating layer 111 at the bottom layer is etched, the etching on the substrate 100 can be reduced. In addition, the etching rate can also be reduced when the last insulating layer or layers 111 and the sacrificial layer 112 on the surface of the substrate 100 are etched, so that the etching can be stopped quickly when the first surface 11 of the substrate 100 is etched.
In one embodiment, C is used4F8As an etching gas, and by adjusting parameters such as flow rate of the gas, pressure temperature, etc., the insulating layer 111 and the sacrificial layer 112 have a high etching selectivity with respect to the substrate 100 during etching. Those skilled in the art can adjust the etching gas and the etching parameters in each direction according to the performance of the adopted etching base station and the characteristic size of the channel hole, so as to realize higher etching selectivity to the stacked structure 110.
In the embodiment shown in fig. 1, the top dimension of the channel hole 130 is larger than the bottom dimension, the overall cross-section is trapezoidal, the sidewalls are sloped, and the Critical Dimension (CD) of the channel hole 130 gradually decreases from the top to the bottom along the trapezoidal proportion. In other embodiments, the sidewalls of the channel hole 130 may also be perpendicular to the surface of the substrate 100, so that the critical dimensions at each position of the channel hole are the same.
In other specific embodiments, referring to fig. 1b, the middle of the sidewall of the formed channel hole 130a may be protruded outward by controlling etching parameters such as gas concentration, flow rate, and temperature during the etching process, and factors such as distortion and inclination of the mask pattern during the etching process, so that the Critical Dimension (CD) of the channel hole 130a may not change uniformly from the top to the bottom.
Referring to fig. 2, a channel hole structure is formed in the channel hole 130 (see fig. 1a), and the channel hole structure includes an epitaxial semiconductor layer 200 on the surface of the substrate 100 at the bottom of the channel hole, a functional sidewall covering the sidewall of the channel hole, a channel layer 204 covering the functional sidewall and connected to the epitaxial semiconductor layer 200, and a channel dielectric layer 205 filling the channel hole.
An epitaxial semiconductor layer 131 may be formed on the surface of the substrate 100 at the bottom of the channel hole using a selective epitaxial process. The top of the epitaxial semiconductor layer 131 is higher than the first sacrificial layer 112 from the surface of the substrate 100 and lower than the second sacrificial layer 112.
The functional side wall comprises a charge blocking layer 201 covering the surface of the side wall of the channel hole, a charge trapping layer 202 covering the charge blocking layer 201, and a tunneling layer 203 covering the charge trapping layer 202. In one embodiment, the charge blocking layer 201 is made of silicon oxide, the charge trapping layer 202 is made of silicon nitride, and the tunneling layer 203 is made of silicon oxide.
In this embodiment, the bottom of the channel layer 204 is connected to the epitaxial semiconductor layer 200 and covers the surface of the stacked structure 110. In other embodiments, the channel layer 204 may also cover the surface of the epitaxial semiconductor layer 200. The material of the channel layer 204 may be polysilicon.
The functional sidewall spacer, the channel layer, and the channel dielectric layer 205 may be formed by a chemical vapor deposition process or an atomic layer deposition process.
The tunnel dielectric layer 205 fills the channel hole and covers the surface of the pair of stacked structures 110. The tunnel dielectric layer 205 may be formed using a chemical vapor deposition process or an atomic layer deposition process. Because the size of the channel hole is small, preferably, an atomic layer deposition process is selected to form the channel dielectric layer 205. In this embodiment, the tunnel dielectric layer 205 is made of silicon oxide. In other embodiments, other insulating dielectric materials may be used for the tunnel dielectric layer 205.
In the process of depositing the trench dielectric layer 205, since the gas pressure and the flow rate on the surface of the wafer are both greater than those in the trench hole, the deposition rate at the opening at the top of the trench hole is higher, the deposition of the material of the trench dielectric layer is easier, and the top of the trench hole is easily closed when the trench hole is not completely filled with the material of the trench dielectric, so that an air gap is formed in the trench dielectric layer 205 in the trench hole. Based on this, the embodiments of the present invention can control the deposition process by controlling the process parameters such as the gas flow rate and pressure of the deposition process, so as to form the air gap 210 in the tunnel dielectric layer 205, and can also control the deposition process by the process
In another embodiment (please refer to fig. 1b), the side of the trench hole 130a protrudes outward, so that the critical dimension at this position is large, and the gap is not easily filled during the process of filling the trench dielectric layer, and is easily formed. Therefore, in the process of etching the stack structure 110 to form the channel hole 130a, by controlling the position of the sidewall protrusion, the position of the formed gas 210 can also be controlled.
In an embodiment of the present invention, one or more air gaps 210 may be formed in the tunnel dielectric layer 205, and the height of the air gaps 210 is limited to a predetermined height. Preferably, the height difference between the top of the air gap 210 and the set height is greater than or equal to 90 nm.
Referring to fig. 3, an isotropic etching process is performed to etch back the channel dielectric layer 205 (see fig. 2) to a predetermined height, exposing a portion of the channel layer 204.
The surface of the tunnel dielectric layer 205a after back etching is lower than the top of the stacked structure 110, exposing a portion of the channel layer 204 at the sidewall of the top of the channel hole.
The isotropic etching process at least comprises a wet etching process, and the wet etching process has high etching selectivity, so that an etching stop layer does not need to be formed at the top of the stacked structure 110, and the etching stop position can be well controlled through etching time.
In this embodiment, the method for performing back etching on the tunnel dielectric layer includes: and etching the channel dielectric layer 205 by adopting a wet etching process until the height is set. The top surface of the etched tunnel dielectric layer 205 is higher than the air gap 210. Electrical contacts are subsequently formed on the tunnel dielectric layer 205, and the air gaps 210 do not affect the topography of the electrical contacts.
In the specific embodiment, the etching solution adopted by the wet etching process is an etching solution diluted by 100-200 times with 49% HF solution. The concentration of the etching solution is small, so that the over-etching caused by too fast etching speed is avoided. If over-etching occurs, the air gap 210 is easily exposed, so that a subsequently formed electrical contact part enters the gas 210 to form a sharp-angled morphology, which causes problems of point discharge and the like, and adverse effects on electrical performance.
After the etched-back channel dielectric layer 205a is formed, the exposed channel layer 204 may be further cleaned to remove a native oxide layer formed on the surface of the channel layer 204, so as to improve the electrical connection performance between the subsequently formed electrical contact and the channel layer 204. The cleaning process may be performed by using a solution obtained by diluting 49% HF solution 10000 times.
In another embodiment, the method for performing back etching on the tunnel dielectric layer may include: etching the channel dielectric layer 205 by adopting a wet etching process; and continuing to adopt a gas etching process, reacting gas molecules with the channel dielectric layer 205, and further etching the channel dielectric layer 205 back to the set height. Under the condition that the distance between the air gap 210 and the set height is short, in order to avoid over-etching caused by a wet etching process and expose the air gap 210, the wet etching process may be used to etch a part of the thickness of the channel dielectric layer 205, and then the gas etching process is used to continuously etch the channel dielectric layer 205. The gas etching process etches the channel dielectric layer 205 only by utilizing chemical reaction between gas molecules and the material of the channel dielectric layer 205, and has higher isotropy and etching selectivity. Preferably, the etching gas adopted by the gas etching process isFluorine-containing gases, e.g. CF4、C2F8And the etching rate can be adjusted by controlling the parameters of the problems, the gas concentration and the like in the etching process, and when the etching is carried out to the set height, the etching is stopped in time, so that the etching process is easier to control accurately. In this way, the requirement for the position of the air gap 210 can be reduced, and even if the position of the air gap 210 is closer to the set height, the air gap 210 can be prevented from being exposed in the back etching process.
After the etch back is completed, the exposed native oxide layer on the surface of the channel layer 204 and the reactant residues caused by the gas phase etching may be further removed by a cleaning step.
Referring to fig. 4, an electrical contact 400 is formed on top of the etched back channel dielectric layer 205a, and an electrical connection is formed between the electrical contact 400 and the channel layer 204.
The material of the electrical contact 300 may be polysilicon, tungsten, aluminum, or copper. In this embodiment, the material of the electrical contact 300 is polysilicon, and an electrical contact material may be deposited on the top of the stacked structure 110 and the tunnel dielectric layer 205a by a chemical vapor deposition process, an atomic layer deposition process, or the like, and planarized to form the electrical contact 400. In this embodiment, the surface of the electrical contact 400 is flush with the surface of the channel layer 204 located on the surface of the stacked structure 110.
In other embodiments, the electrical contact 400 and the channel layer 204 may be planarized with the top of the stacked structure 110 as a stop surface, exposing the insulating layer 111 on the top of the stacked structure 110.
In the above specific embodiment, the channel medium layer is etched back by the isotropic etching process, so that etching damage to the exposed channel layer is reduced, the surface morphology quality of the channel layer is improved, the interface quality of the contact between the electrical contact portion formed on the channel medium layer and the channel layer is improved, the electrical contact performance between the electrical contact portion and the channel layer is improved, and the performance of the memory is further improved.
Furthermore, in the process of forming the channel dielectric layer, the air gap in the channel dielectric layer is controlled to be positioned below the set height, so that the air gap is prevented from being exposed in the process of back etching the channel dielectric layer, and the electrical property defect caused by the fact that the electrical contact part is formed in the air gap is avoided.
The embodiment of the invention also provides a memory.
Fig. 4 is a schematic structural diagram of a memory according to an embodiment of the invention.
The memory includes: the substrate structure comprises a substrate 100, wherein a stack structure 110 and a channel hole structure penetrating through the stack structure to the surface of the substrate 100 are formed on the substrate 100.
The channel hole structure comprises an epitaxial semiconductor layer 200 located on the surface of a substrate 100 at the bottom of a channel hole, a functional side wall covering the side wall of the channel hole and a channel medium layer 205a covering the functional side wall, the channel layer 204 of the epitaxial semiconductor layer is connected with the functional side wall and is filled in the channel hole 204, the top of the channel medium layer 205a is lower than the top of the channel layer 204, part of the channel layer 204 is exposed, and the channel medium layer 205a is provided with a top surface etched by an anisotropic etching process.
The memory device also includes a contact 400 on top of the tunnel dielectric layer 205a, the contact 400 forming an electrical connection with the channel layer 204.
The substrate 100 may be a single crystal silicon substrate, a Ge substrate, a SiGe substrate, an SOI, a GOI, or the like; according to the actual requirements of the device, a suitable semiconductor material may be selected as the substrate 100, which is not limited herein. In this embodiment, the substrate 100 is a single crystal silicon wafer.
The stack structure 110 includes an insulating layer 111 and a sacrificial layer 112 stacked on each other in a direction perpendicular to the surface of the substrate 100. In one embodiment, the material of the insulating layer 111 is silicon oxide, and the material of the sacrificial layer 112 is silicon nitride; in other embodiments, other suitable materials for the insulating layer 111 and the sacrificial layer 112 may be used. In another embodiment, the stacked structure 110 includes conductive layers and insulating layers stacked alternately, for example, the conductive layers may be control gates.
The channel hole structure is formed in a channel hole penetrating the stack structure 110. In the embodiment shown in fig. 4, the top dimension of the channel hole is larger than the bottom dimension, the overall cross section is trapezoidal, the sidewalls are inclined, and the Critical Dimension (CD) of the channel hole gradually decreases from the top to the bottom along the trapezoidal proportion (see fig. 1 a).
In other embodiments, the sidewalls of the channel hole may also be perpendicular to the surface of the substrate 100, so that the critical dimension at each position of the channel hole is the same, i.e., the critical dimension at each position of the channel hole structure is the same.
In other embodiments, the etching parameters such as gas concentration, flow rate, and temperature used in the etching process to form the channel hole, and the distortion and inclination of the mask pattern during the etching process cause the middle portion of the sidewall of the formed channel hole to protrude outward, so that the Critical Dimension (CD) of the channel hole varies unevenly from the top to the bottom (see fig. 1 b).
The functional side wall of the channel hole structure comprises a charge blocking layer 201 covering the surface of the side wall of the channel hole, a charge trapping layer 202 covering the charge blocking layer 201, and a tunneling layer 203 covering the charge trapping layer 202. In one embodiment, the charge blocking layer 201 is made of silicon oxide, the charge trapping layer 202 is made of silicon nitride, and the tunneling layer 203 is made of silicon oxide.
The bottom of the channel layer 204 is connected to the epitaxial semiconductor layer 200 and covers the surface of the stack structure 110. In other embodiments, the channel layer 204 may also cover the surface of the epitaxial semiconductor layer 200. The material of the channel layer 204 may be polysilicon.
The tunnel dielectric layer 205a may be made of an insulating dielectric material such as silicon oxide. The top of the channel dielectric layer 205a is at a set height to expose a sufficient height of the channel layer 204 to enable the channel layer 204 to make sufficient electrical contact with the electrical contact 400. The trench dielectric layer 205a is an atomic layer deposition layer, which is easy to fill a trench hole with a small size.
An air gap 210 is formed in the tunnel dielectric layer 205 a. Because the gas pressure and the flow rate on the surface of the wafer are both greater than those in the trench hole, the deposition rate at the opening at the top of the trench hole is higher, the deposition of the trench dielectric layer material is easier, the top of the trench hole is easily closed when the trench hole is not completely filled with the trench dielectric material, and an air gap is formed in the trench dielectric layer 205a in the trench hole. In this particular embodiment, the air gap 210 is located below the top of the tunnel dielectric layer 205a, and the air gap 210 is prevented from contacting the electrical contact 400, thereby preventing the air gap 210 from affecting the electrical performance of the electrical contact 400.
In other embodiments, the sidewall of the trench hole structure protrudes outward, so that the critical dimension of the protruding position of the sidewall is larger, and the trench dielectric layer 205a is not easily filled, so that the air gap 210 is located at the height of the protruding sidewall of the trench hole. By controlling the location of the sidewall protrusion, the position of the air gap 210 can be adjusted so that the air gap 210 is below the top of the tunnel dielectric layer 205 a.
Preferably, the height difference between the top of the air gap 210 and the top surface of the tunnel dielectric layer 205a is greater than or equal to 90 nm.
The tunnel dielectric layer 205a has a top surface that is etched by an anisotropic etching process. The anisotropic etching process at least comprises a wet etching process. In one embodiment, the channel dielectric layer 205a is formed by etching back the channel dielectric material to a predetermined height by a wet etching process. The wet etching process can use a less-concentrated etching solution to avoid over-etching due to too fast etching rate and to avoid exposing the air gap 210.
In another embodiment, the anisotropic etching process includes a wet etching process and a gas etching process after the wet etching process. Under the condition that the distance between the air gap 210 and the set height is relatively short, in order to avoid over-etching caused by a wet etching process, the air gap 210 is exposed, a part of the thickness of the channel dielectric layer material can be etched by the wet etching process, and then the channel dielectric layer material is continuously etched by a gas etching process. The gas etching process only utilizes the chemical reaction between gas molecules and the channel dielectric layer material to etch the channel dielectric material, and has higher isotropy and etching selectivity.
The material of the electrical contact 300 may be polysilicon, tungsten, aluminum, or copper. In this embodiment, the surface of the electrical contact 400 is flush with the surface of the channel layer 204 located on the surface of the stacked structure 110. In another embodiment, the tops of the electrical contact 400 and the channel layer 204 are flush with the top of the stacked structure 110, exposing the insulating layer 111 on the top of the stacked structure 110.
The top of the channel medium layer of the memory is provided with an isotropic etching surface, so that the surface of the exposed channel layer is less damaged, the surface of the exposed channel layer has higher interface quality with the electric contact part, the electric contact performance of the electric contact part and the channel layer is improved, and the performance of the memory is further improved.
Further, an air gap in the channel dielectric layer is ensured to be positioned below the top surface of the channel dielectric layer, and electrical performance defects caused by the fact that an electrical contact part is formed in the air gap are avoided.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (16)
1. A method for forming a memory, comprising:
providing a substrate, wherein a stacking structure is formed on the substrate;
forming a channel hole penetrating through the stacked structure to the surface of the substrate;
forming a channel hole structure in the channel hole, wherein the channel hole structure comprises an epitaxial semiconductor layer positioned on the surface of the substrate at the bottom of the channel hole, a functional side wall covering the side wall of the channel hole, a channel layer covering the functional side wall and connected with the epitaxial semiconductor layer, and a channel medium layer filling the channel hole;
etching the channel medium layer to a set height by adopting an isotropic etching process to expose part of the channel layer;
and forming an electric contact part on the top of the etched back channel medium layer, wherein the electric contact part is electrically connected with the channel layer.
2. The method of claim 1, wherein an air gap is formed in the tunnel dielectric layer, and the air gap is located below the set height.
3. The method of claim 2, wherein a height difference between the top of the air gap and the set height is greater than or equal to 90 nm.
4. The method of claim 1, wherein the tunnel dielectric layer is formed by an atomic layer deposition process.
5. The method of claim 1, wherein the isotropic etching process comprises at least a wet etching process.
6. The method for forming a memory according to claim 5, wherein the step of etching back the tunnel dielectric layer comprises: etching the channel dielectric layer by adopting a wet etching process; and continuing to adopt a gas etching process, and further etching the channel medium layer back to the set height by utilizing the reaction of gas molecules and the channel medium layer.
7. The method for forming a memory according to claim 5, wherein the step of etching back the tunnel dielectric layer comprises: and etching the channel dielectric layer to the set height by only adopting a wet etching process.
8. The method of claim 1, further comprising: and cleaning the exposed channel layer.
9. The method of claim 1, wherein a middle portion of a sidewall of the channel hole protrudes outward.
10. A memory, comprising:
the structure comprises a substrate, wherein a stacking structure and a channel hole structure penetrating through the stacking structure to the surface of the substrate are formed on the substrate, the channel hole structure comprises an epitaxial semiconductor layer positioned on the surface of the substrate at the bottom of a channel hole, a functional side wall covering the side wall of the channel hole, a channel layer covering the functional side wall and connected with the epitaxial semiconductor layer, and a channel medium layer filling the channel hole, the top of the channel medium layer is lower than the top of the channel layer, part of the channel layer is exposed, and the channel medium layer is provided with a top surface etched by an anisotropic etching process;
and the contact part is positioned at the top of the channel medium layer, and the contact part is electrically connected with the channel layer.
11. The memory of claim 10, wherein an air gap is formed within the tunnel dielectric layer, the air gap being located within the tunnel dielectric layer.
12. The memory of claim 11, wherein a height difference between a top of the air gap and a top of the tunnel dielectric layer is greater than or equal to 90 nm.
13. The memory of claim 10, wherein the tunnel dielectric layer is an atomic layer deposition layer.
14. The memory of claim 10, wherein the anisotropic etch process comprises at least a wet etch process.
15. The memory of claim 14, wherein the anisotropic etch process comprises a wet etch process and a gas etch process after the wet etch process.
16. The memory of claim 10, wherein the channel structure has a sidewall that protrudes outward from a middle portion of the sidewall.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112216703A (en) * | 2020-10-10 | 2021-01-12 | 长江存储科技有限责任公司 | Manufacturing method of semiconductor structure and semiconductor structure |
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