CN108538848B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN108538848B CN108538848B CN201810642249.0A CN201810642249A CN108538848B CN 108538848 B CN108538848 B CN 108538848B CN 201810642249 A CN201810642249 A CN 201810642249A CN 108538848 B CN108538848 B CN 108538848B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 157
- 238000000034 method Methods 0.000 title claims abstract description 37
- 239000010410 layer Substances 0.000 claims abstract description 309
- 239000002346 layers by function Substances 0.000 claims abstract description 59
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 230000000149 penetrating effect Effects 0.000 claims abstract description 20
- 230000001590 oxidative effect Effects 0.000 claims abstract description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 19
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 19
- 230000003647 oxidation Effects 0.000 claims description 18
- 238000007254 oxidation reaction Methods 0.000 claims description 18
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 7
- 239000001301 oxygen Substances 0.000 claims description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- 238000001312 dry etching Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 description 41
- 230000007547 defect Effects 0.000 description 15
- 230000005540 biological transmission Effects 0.000 description 11
- 230000000903 blocking effect Effects 0.000 description 10
- 230000005641 tunneling Effects 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- 230000015654 memory Effects 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 238000010586 diagram Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The invention relates to a semiconductor structure and a forming method thereof, wherein the forming method of the semiconductor structure comprises the following steps: providing a substrate, wherein the substrate comprises a first stacking structure and a first channel hole structure penetrating through the first stacking structure, and a semiconductor layer is further formed on the top of the first channel hole structure; forming a second stacking structure on the surface of the substrate; forming a second channel hole penetrating through the second stacked structure and the semiconductor layer with partial depth; oxidizing the surface of the semiconductor layer at the bottom of the second channel hole to form an oxide layer; forming a functional layer covering the inner wall of the second channel hole; removing the functional layer and the oxide layer which are positioned at the bottom of the second channel hole to form a second functional layer, and exposing the semiconductor layer below the oxide layer; and forming a second channel layer on the surface of the second functional layer and the surface of the exposed semiconductor layer. The method can improve the quality of the semiconductor layer, thereby improving the performance of the semiconductor structure.
Description
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same.
Background
In recent years, flash (Memory) memories have been developed particularly rapidly. The flash memory has the main characteristics of long-term storage of stored information without power up, and has the advantages of high integration level, high access speed, easy erasing and rewriting, and the like, thereby being widely applied to various fields such as microcomputers, automatic control, and the like. In order to further increase the Bit Density (Bit Density) of the flash memory while reducing the Bit Cost (Bit Cost), three-dimensional flash memory (3D NAND) technology has been rapidly developed.
In order to further improve the bit density of the 3D NAND flash memory structure, a double-layer or multi-layer channel hole structure is used, current transmission is performed between the multi-layer channel hole structures through a semiconductor layer, such as a polysilicon layer, located between the upper and lower layer channel hole structures, and the surface of the semiconductor layer is easy to generate defects when the upper layer channel hole is etched, so that the current transmission effect on the surface of the semiconductor layer is influenced, thereby influencing the yield of products and reducing the reliability of the products.
How to improve the performance of a 3D NAND flash memory structure with a multi-layer channel hole structure is a problem to be solved at present.
Disclosure of Invention
The invention aims to provide a semiconductor structure and a forming method thereof, so as to improve the performance of a 3D NAND flash memory structure.
The invention provides a method for forming a semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a first stacking structure and a first channel hole structure penetrating through the first stacking structure, and a semiconductor layer is further formed on the top of the first channel hole structure; forming a second stacking structure on the surface of the substrate; forming a second channel hole penetrating through the second stacked structure and the semiconductor layer with partial depth; oxidizing the surface of the semiconductor layer at the bottom of the second channel hole to form an oxide layer; forming a functional layer covering the inner wall of the second channel hole; removing the functional layer and the oxide layer which are positioned at the bottom of the second channel hole to form a second functional layer, and exposing the semiconductor layer below the oxide layer; and forming a second channel layer on the surface of the second functional layer and the surface of the exposed semiconductor layer.
Optionally, a dry oxygen oxidation or wet oxygen oxidation process is adopted to oxidize the surface of the semiconductor layer at the bottom of the second channel hole.
Optionally, the thickness of the oxide layer is 2 nm-10 nm.
Optionally, the material of the oxide layer is silicon oxide.
Optionally, the depth of the second channel hole penetrating through the semiconductor layer is 20 nm-40 nm.
Optionally, after removing the functional layer and the oxide layer at the bottom of the second channel hole to form the second functional layer and expose the semiconductor layer under the oxide layer, and before forming the second channel layer, the method further includes: oxidizing the surface of the exposed semiconductor layer to form a repair layer; and removing the second functional layer, the oxide layer and the repair layer which cover the semiconductor layer.
Optionally, a dry etching process is used to remove the second functional layer, the oxide layer and the repair layer covering the semiconductor layer.
Optionally, the first channel hole structure includes a first channel hole, a first functional layer located on a surface of a sidewall of the first channel hole, a first channel layer located on a surface of the first functional layer and a bottom surface of the first channel hole, and a first channel dielectric layer located on a surface of the first channel layer and filling the first channel hole; the second channel hole width is smaller than the first channel hole width.
Optionally, the method further comprises: and forming a second channel dielectric layer filling the second channel hole on the surface of the second channel layer.
In order to solve the above problems, the technical solution of the present invention further provides a semiconductor structure, including: the semiconductor device comprises a substrate, a first substrate and a second substrate, wherein the substrate comprises a first stacking structure and a first channel hole structure penetrating through the first stacking structure, and a semiconductor layer is formed on the top of the first channel hole structure; a second stacked structure located on the surface of the substrate; a second channel hole penetrating the second stack structure and the semiconductor layer with partial depth, wherein the width of the second channel hole in the semiconductor layer is larger than that of the second channel hole in the second stack structure; a second functional layer located on a surface of a sidewall of the second channel hole in the second stacked structure; and the channel layer is positioned on the surface of the second functional layer and the inner wall of the second channel hole in the semiconductor layer.
Optionally, the second functional layer further covers a second channel hole sidewall in the semiconductor layer, an oxide layer is further provided between the second functional layer and the second channel hole sidewall in the semiconductor layer, and the channel layer is located on the surface of the second functional layer and at the bottom of the second channel hole.
Optionally, the oxide layer is a dry oxide layer or a wet oxide layer.
Optionally, the thickness of the oxide layer is 2 nm-10 nm.
Optionally, the material of the oxide layer is silicon oxide.
Optionally, the depth of the second channel hole penetrating through the semiconductor layer is 20 nm-40 nm.
Optionally, the first channel hole structure includes a first channel hole, a first functional layer located on a surface of a sidewall of the first channel hole, and a first channel layer located on a surface of the first functional layer and a bottom surface of the first channel hole; the second channel hole width is smaller than the first channel hole width.
Optionally, the method further comprises: and the second channel medium layer is positioned on the surface of the second channel layer and fills the second channel hole.
In the method for forming the semiconductor structure, after the second channel hole is formed, the surface of the semiconductor layer at the bottom of the second channel hole is subjected to oxidation treatment to form the oxide layer, so that the defect of the surface of the semiconductor layer is eliminated, the quality of the semiconductor layer is improved, the quality of the interface between the semiconductor layer and the second channel layer is improved, the current transmission performance of the semiconductor layer is improved, and the reliability and the yield of products are further improved.
Drawings
Fig. 1 to 8 are schematic structural views illustrating a process of forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
The following describes in detail the semiconductor structure and the method for forming the same provided by the present invention with reference to the accompanying drawings.
Referring to fig. 1 to 8, schematic structural diagrams of a semiconductor structure forming process according to an embodiment of the invention are shown.
Referring to fig. 1, a substrate 100 is provided, the substrate 100 includes a first stack structure 110, a first channel hole structure 120 penetrating through the first stack structure 110, and a semiconductor layer 130 is further formed on top of the first channel hole structure 120.
The base 100 includes a substrate (not shown in the drawings) and a first stack structure 110 stacked with the surface of the substrate in a direction perpendicular to the surface of the substrate is formed, and the first stack structure 110 includes a first insulating layer 111 and a first sacrificial layer 112 stacked with each other. In one embodiment, the material of the first insulating layer 111 is silicon oxide, and the material of the first sacrificial layer 112 is silicon nitride; in other embodiments, other suitable materials may be used for the first insulating layer 111 and the first sacrificial layer 112. In fig. 1, only a top partial schematic view of the first stack 110 is shown.
The first channel hole structure 120 penetrating the first stack structure 110 includes: the first channel dielectric layer 125 is filled in the first channel hole, and the first channel dielectric layer 124 is formed on the surface of the first functional layer and the bottom surface of the first channel hole. The first functional layer includes a first blocking layer 121, a first charge trapping layer 122, and a first tunneling layer 123 sequentially disposed from outside to inside. In this embodiment, the material of the first blocking layer 121 is silicon oxide, the material of the first charge trapping layer 122 is silicon nitride, the material of the first tunneling layer 123 is silicon oxide, the material of the first channel layer 124 is polysilicon, and the material of the first channel dielectric layer 125 is silicon oxide.
The first channel hole structure 120 has a semiconductor layer 130 on top, and the surface of the semiconductor layer 130 is flush with the surface of the first stack structure 110. In this embodiment, the semiconductor layer 130 is a polysilicon layer; in other embodiments, the semiconductor layer 130 may also be made of other semiconductor materials, such as single crystal silicon, polycrystalline germanium, and the like.
The base 100 further includes an interlayer dielectric layer (not shown) on the surface of the substrate, where the interlayer dielectric layer at least covers the sidewalls of the first stack structure 110.
Referring to fig. 2, a second stacked structure 210 is formed on the surface of the substrate 100.
The second stacked structure 210 includes a second insulating layer 211 and a second sacrificial layer 212 stacked on each other. In fig. 2, only a two-layer stack structure is taken as an example of the second stack structure 210, and the actual second stack structure is not represented. In one embodiment, the material of the second insulating layer 211 is silicon oxide, and the material of the second sacrificial layer 212 is silicon nitride; in other embodiments, other suitable materials may be used for the second insulating layer 211 and the second sacrificial layer 212.
Referring to fig. 3, a second channel hole 301 is formed through the second stacked structure 210 above the first channel hole structure 120 and the semiconductor layer 130 with a partial depth.
The second stack structure 210 and the semiconductor layer 130 may be etched using an anisotropic etching process to form the second channel hole 301 such that the bottom of the second channel hole 301 is located within the semiconductor layer 130.
In this embodiment, the width of the second channel hole 301 is smaller than the width of the first channel hole structure 120, and charges between the second channel layer and the first channel layer 124 in the second channel hole structure formed later can be transferred through the surface of the semiconductor layer 130.
The depth of the second channel hole 301 penetrating the semiconductor layer 130 is 20 nm-40 nm, and the depth of the second channel hole 301 in the semiconductor layer 130 can be adjusted according to the current transmission performance requirement.
Referring to fig. 4, an oxide layer 401 is formed by performing an oxidation treatment on the surface of the semiconductor layer 130 at the bottom of the second channel hole 301.
The surface of the semiconductor layer 130 at the bottom of the second channel hole 301 may be oxidized by a dry oxygen oxidation or a wet oxygen oxidation process to form the oxide layer 401.
In this embodiment, a wet oxygen oxidation process is used to oxidize the surface of the semiconductor layer 130, where the semiconductor layer 130 is a polysilicon layer, and the surface of the semiconductor layer 130 is oxidized to form a silicon oxide layer. In this embodiment, H is used 2 O steam is used as oxidizing gas, the oxidizing temperature is 650-950 ℃ and the oxidizing time is 40-100 min.
The semiconductor layer 130 is etched during the process of forming the second channel hole 301, so that many lattice defects may be generated on the surface of the semiconductor layer 130, and the surface defects of the semiconductor layer 130 may affect the transmission of current due to the charge being transmitted on the surface of the semiconductor layer 130 in the subsequent semiconductor structure. By oxidizing the polysilicon having the defect on the surface of the semiconductor layer 130 to form the oxide layer 401 through the oxidation treatment, the defect on the surface of the semiconductor layer 130 can be eliminated, thereby improving the current transmission performance of the surface of the semiconductor layer 130.
In order to remove the defects on the surface of the semiconductor layer 130 to the maximum extent, the oxidation depth of the surface of the semiconductor layer 130 may be adjusted by adjusting the time, temperature, and other process parameters of the oxidation treatment to remove the defects on the surface of the semiconductor layer 130 to the maximum extent. In the embodiment of the present invention, the thickness of the oxide layer 401 may range from 2nm to 10nm.
Referring to fig. 5, a functional layer is formed to cover the inside of the second channel hole 301, and the functional layer and the oxide layer 401 at the bottom of the second channel hole 301 are removed to form a second functional layer 510, and the semiconductor layer 130 under the oxide layer 401 is exposed.
The second functional layer 510 includes a second blocking layer 511, a second charge trapping layer 512, and a second tunneling layer 513. In this embodiment, the material of the second blocking layer 511 is silicon oxide, the material of the second charge trapping layer 512 is silicon nitride, and the material of the second tunneling layer 513 is silicon oxide.
After the second blocking material layer, the second charge trapping material layer and the second tunneling material layer are sequentially formed on the inner wall surface of the second channel hole 301, an anisotropic dry etching process is adopted to etch and remove the second blocking material layer, the second charge trapping material layer and the second tunneling material layer and the partial oxide layer 401 at the bottom of the second channel hole 301, so as to form the second functional layer 510 and expose the surface of the semiconductor layer 130.
A second channel layer may be formed directly on the surface of the second functional layer 510 in the second channel hole 301 and the exposed surface of the second semiconductor layer 130, and the second channel dielectric layer of the second channel hole 301 may be filled, so as to form a second channel hole structure in the second channel hole 301. Since the current between the second channel hole structure and the first channel hole structure is transferred on the surface of the semiconductor layer 130, but since the semiconductor layer 130 has the upward protruding portions at both sides of the second channel hole 301 in the structure shown in fig. 5, the current transfer path increases, and the second functional layer 510 is blocked between the second channel layer and the semiconductor layer 130, resulting in a reduced current.
In order to solve the above problems, embodiments of the present invention further include further processes.
Referring to fig. 6, the exposed surface of the semiconductor layer 130 is oxidized.
Since the exposed surface of the semiconductor layer 130 is damaged by the dry etching process during the formation of the second functional layer 510 and the removal of the oxide layer 401, the surface defect of the semiconductor layer 130 may be repaired by further oxidizing, and the repair layer 601 is formed on the exposed surface of the semiconductor layer 130. The oxidation treatment may be a dry or wet oxidation process.
Referring to fig. 7, a portion of the second functional layer 510, the oxide layer 401 and the repair layer 601 covering the semiconductor layer 130 is removed to completely expose the surface of the semiconductor layer 130.
In a specific embodiment, a dry etching process may be used to remove the second functional layer 510, the oxide layer 401 and the repair layer 601 on the surface of the semiconductor layer 130, so as to expose the surface of the semiconductor layer 130.
Referring to fig. 8, a second channel layer 801 is formed on the surface of the second functional layer 510 and the exposed surface of the semiconductor layer 130.
The material of the second channel layer 801 may be polysilicon or other semiconductor material. In the structure shown in fig. 8, no other material layer is blocked between the second channel layer 801 and the semiconductor layer 130, and after the current in the second channel layer 801 contacts the semiconductor layer 130, the current can be directly transferred to the first channel layer 124 in the first channel hole structure 120 along the surface of the semiconductor layer 130, so that the transfer current is larger. In addition, since the surface quality of the semiconductor layer 130 is high, the deposition quality of the second channel layer 801 can be improved, the quality of the contact interface between the second channel layer 801 and the semiconductor layer 130 can be improved, and the current transmission efficiency can be improved.
In the above embodiment, after the second stacked structure is etched until the semiconductor layer forms the second channel hole, the surface of the semiconductor layer is subjected to oxidation treatment, so that lattice defects on the surface of the semiconductor layer are eliminated, the current transmission efficiency on the surface of the semiconductor layer is improved, and further the reliability and yield of the product are improved.
The embodiment of the invention also provides a semiconductor structure.
Please refer to fig. 8, which is a schematic diagram of a structure of the semiconductor structure.
The semiconductor structure includes: a substrate, wherein the substrate comprises a first stack structure 110 and a first channel hole structure 120 penetrating through the first stack structure 110, a semiconductor layer 130 is further formed on top of the first channel hole structure 120, and the semiconductor layer 130 has a surface subjected to oxidation treatment and oxide layer removal; a second stacked structure 210 located on the surface of the substrate; a second channel hole 301 penetrating the second stacked structure 210 and the semiconductor layer 130 with a partial depth, wherein a width of the second channel hole 301 in the semiconductor layer 130 is greater than a width of the second channel hole 301 in the second stacked structure 210; a second functional layer 510 located on a sidewall surface of the second channel hole 301 in the second stacked structure 210; and a second channel layer 801 located on the surface of the second functional layer 510 and on the inner wall of the second channel hole 301 in the semiconductor layer 130.
The base 100 includes a substrate (not shown), a first stack structure 110 formed on a surface of the substrate and stacked in a direction perpendicular to the surface of the substrate, the first stack structure 110 including a first insulating layer 111 and a first sacrificial layer 112 stacked on each other. In one embodiment, the material of the first insulating layer 111 is silicon oxide, and the material of the first sacrificial layer 112 is silicon nitride; in other embodiments, other suitable materials may be used for the first insulating layer 111 and the first sacrificial layer 112. In fig. 8, only a top partial schematic view of the first stack structure 110 is shown. In another embodiment, the first stack structure 110 may further include a first insulating layer 111 and a first control gate 112 stacked on each other.
The first channel hole structure 120 penetrating the first stack structure 110 includes: the first channel dielectric layer 125 is filled in the first channel hole, and the first channel dielectric layer 124 is formed on the surface of the first functional layer and the bottom surface of the first channel hole. The first functional layer includes a first blocking layer 121, a first charge trapping layer 122, and a first tunneling layer 123 sequentially disposed from outside to inside. In this embodiment, the material of the first blocking layer 121 is silicon oxide, the material of the first charge trapping layer 122 is silicon nitride, the material of the first tunneling layer 123 is silicon oxide, the material of the first channel layer 124 is polysilicon, and the material of the first channel dielectric layer 125 is silicon oxide.
The top of the first channel hole structure 120 has a semiconductor layer 130, and in this embodiment, the semiconductor layer 130 is a polysilicon layer; in other embodiments, other semiconductor materials may be used for the semiconductor layer 130. The semiconductor layer 130 has a surface subjected to oxidation treatment and the oxide layer is removed, and the oxidation treatment can eliminate defects on the surface of the semiconductor layer 130 and improve the quality of the semiconductor layer 130.
The second stacked structure 210 includes a second insulating layer 211 and a second sacrificial layer 212 stacked on each other. In fig. 8, only a two-layer stack structure is taken as an example of the second stack structure 210, and the actual second stack structure is not represented. In one embodiment, the material of the second insulating layer 211 is silicon oxide, and the material of the second sacrificial layer 212 is silicon nitride; in other embodiments, other suitable materials may be used for the second insulating layer 211 and the second sacrificial layer 212. In another embodiment, the second stacked structure 210 includes a second insulating layer 211 and a second control gate 212 stacked on each other.
The depth of the second channel hole 301 penetrating the semiconductor layer 130 is 20 nm-40 nm, and the depth of the second channel hole 301 in the semiconductor layer 130 can be adjusted according to the current transmission performance requirement.
The width of the second channel hole 301 in the semiconductor layer 130 is greater than the width of the second channel hole 301 in the second stacked structure 210, because the oxide layer is removed after the surface of the semiconductor layer 130 is oxidized to form an oxide layer, so that the width of the second channel hole 301 in the semiconductor layer 130 is greater than the width of the second channel hole 301 in the second stacked structure 210. The oxidation treatment can eliminate the defects on the surface of the semiconductor layer 130, so that the defects on the surface of the remaining semiconductor layer 130 are lower, which is beneficial to current transmission.
The second functional layer 510 includes a second blocking layer 511, a second charge trapping layer 512, and a second tunneling layer 513. In this embodiment, the material of the second blocking layer 511 is silicon oxide, the material of the second charge trapping layer 512 is silicon nitride, and the material of the second tunneling layer 513 is silicon oxide.
In other embodiments, the second functional layer 510 further covers the side wall of the second channel hole 301 in the semiconductor layer 130, and an oxide layer is further disposed between the second functional layer 510 and the side wall of the second channel hole 301 in the semiconductor layer 130, and the second channel layer 801 is located on the surface of the second functional layer 510 and at the bottom of the second channel hole 301. The oxide layer is a dry oxide layer or a wet oxide layer, and can eliminate defects on the surface of the semiconductor layer 130. The thickness of the oxide layer is 2 nm-10 nm.
The width of the second channel hole 301 is smaller than the width of the first channel hole structure 120 to ensure that charges between the second channel layer 801 and the first channel layer 124 can be transferred through the surface of the semiconductor layer 130.
The semiconductor layer of the semiconductor structure has fewer surface defects and higher quality, and can improve the current transmission efficiency of the surface of the semiconductor layer, thereby improving the reliability and yield of products.
The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.
Claims (16)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first stacking structure and a first channel hole structure penetrating through the first stacking structure, and a semiconductor layer is further formed on the top of the first channel hole structure;
forming a second stacking structure on the surface of the substrate;
forming a second channel hole penetrating through the second stacked structure and the semiconductor layer with partial depth;
oxidizing the surface of the semiconductor layer at the bottom of the second channel hole to form an oxide layer;
forming a functional layer covering the inner wall of the second channel hole;
removing the functional layer and the oxide layer which are positioned at the bottom of the second channel hole to form a second functional layer, and exposing the semiconductor layer below the oxide layer;
and forming a second channel layer on the surface of the second functional layer and the exposed surface of the semiconductor layer.
2. The method of claim 1, wherein the surface of the semiconductor layer at the bottom of the second trench hole is oxidized by dry oxygen oxidation or wet oxygen oxidation.
3. The method of claim 1, wherein the oxide layer has a thickness of 2nm to 10nm.
4. The method of claim 1, wherein the oxide layer is silicon oxide.
5. The method of claim 1, wherein the depth of the second channel hole penetrating through the semiconductor layer is 20 nm-40 nm.
6. The method of claim 1, wherein removing the functional layer and the oxide layer at the bottom of the second channel hole to form a second functional layer and exposing the semiconductor layer under the oxide layer, and before forming the second channel layer, further comprises: oxidizing the surface of the exposed semiconductor layer to form a repair layer; and removing the second functional layer, the oxide layer and the repair layer which cover the semiconductor layer.
7. The method of claim 6, wherein the second functional layer, the oxide layer, and the repair layer are removed by a dry etching process.
8. The method of claim 1, wherein the first channel hole structure comprises a first channel hole, a first functional layer on a surface of a sidewall of the first channel hole, a first channel layer on a surface of the first functional layer, a bottom surface of the first channel hole, and a first channel dielectric layer on a surface of the first channel layer filling the first channel hole; the second channel hole width is smaller than the first channel hole width.
9. The method of forming a semiconductor structure of claim 1, further comprising: and forming a second channel dielectric layer filling the second channel hole on the surface of the second channel layer.
10. A semiconductor structure, comprising:
the semiconductor device comprises a substrate and a semiconductor layer, wherein the substrate comprises a first stacking structure and a first channel hole structure penetrating through the first stacking structure, the first stacking structure comprises a first insulating layer and a first control grid which are mutually stacked, and the top of the first channel hole structure is also provided with the semiconductor layer;
a second stacked structure located on the surface of the substrate;
a second channel hole penetrating the second stack structure and the semiconductor layer with partial depth, wherein the width of the second channel hole in the semiconductor layer is larger than that of the second channel hole in the second stack structure;
a second functional layer located on a surface of a sidewall of the second channel hole in the second stacked structure;
a second channel layer located on a surface of the second functional layer and an inner wall of a second channel hole in the semiconductor layer;
the second functional layer also covers the side wall of the second channel hole in the semiconductor layer, an oxide layer is arranged between the second functional layer and the side wall of the second channel hole in the semiconductor layer, and the second channel layer is positioned on the surface of the second functional layer and at the bottom of the second channel hole.
11. The semiconductor structure of claim 10, wherein the oxide layer is a dry oxide layer or a wet oxide layer.
12. The semiconductor structure of claim 10, wherein the oxide layer has a thickness of 2nm to 10nm.
13. The semiconductor structure of claim 10, wherein the oxide layer is silicon oxide.
14. The semiconductor structure of claim 10, wherein the depth of the second channel hole through the semiconductor layer is 20 nm-40 nm.
15. The semiconductor structure of claim 10, wherein the first channel hole structure comprises a first channel hole, a first functional layer on a surface of a sidewall of the first channel hole, and a first channel layer on a surface of the first functional layer and a bottom surface of the first channel hole; the second channel hole width is smaller than the first channel hole width.
16. The semiconductor structure of claim 10, further comprising: and the second channel medium layer is positioned on the surface of the second channel layer and fills the second channel hole.
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| WO2020061892A1 (en) | 2018-09-27 | 2020-04-02 | Yangtze Memory Technologies Co., Ltd. | Semiconductor device and method of fabrication thereof |
| WO2020073184A1 (en) | 2018-10-09 | 2020-04-16 | Yangtze Memory Technologies Co., Ltd. | Inter-deck plug in three-dimensional memory device and method for forming same |
| CN109524410B (en) * | 2018-11-23 | 2020-07-28 | 长江存储科技有限责任公司 | Method for forming three-dimensional memory |
| CN109524409B (en) * | 2018-11-23 | 2020-04-10 | 长江存储科技有限责任公司 | Method for forming three-dimensional memory |
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