CN109638016B - Flash memory and forming method thereof - Google Patents
Flash memory and forming method thereof Download PDFInfo
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- CN109638016B CN109638016B CN201910001910.4A CN201910001910A CN109638016B CN 109638016 B CN109638016 B CN 109638016B CN 201910001910 A CN201910001910 A CN 201910001910A CN 109638016 B CN109638016 B CN 109638016B
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
Abstract
A flash memory and forming method thereof, the flash memory includes: the semiconductor substrate comprises a source line floating gate region and a plurality of word line bit line regions, wherein the source line floating gate region is positioned between the adjacent word line bit line regions, each word line bit line region comprises a first word line bit line region and a second word line bit line region, and the first word line bit line region is positioned between the second word line bit line region and the source line floating gate region; a floating gate structure on the semiconductor substrate of the source line floating gate region; a first side wall located on the floating gate structure; a source line layer located between the floating gate structure and the first sidewall; a first word line structure on the first word line bit line region, the first word line structure including a first word line oxide layer; and the second word line structure is positioned on the second word line bit line region and comprises a second word line oxide layer, and the second word line oxide layer covers the side wall of the first word line structure and the second word line oxide layer on the surface of the semiconductor substrate in the second word line bit line region. The performance of the flash memory is improved.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a flash memory and a method for forming the same.
Background
Flash memory is an important device in integrated circuit products. The main feature of flash memory is that it can retain stored information for a long time without applying a voltage. The flash memory has the advantages of high integration level, fast access speed, easy source line and the like, thereby being widely applied.
Flash memories are divided into two types: stacked gate flash memory and split gate flash memory. The stacked gate flash memory has a floating gate and a control gate over the floating gate. The stacked gate flash memory has the problem of source line passing. Unlike the stacked gate flash memory, the split gate flash memory forms a word line as a source line gate at one side of a floating gate. The split-gate flash memory can effectively avoid the source line effect.
However, the performance of the conventional split-gate flash memory is poor.
Disclosure of Invention
The invention provides a flash memory and a forming method thereof, which are used for improving the performance of the flash memory.
To solve the above technical problem, the present invention provides a flash memory, including: the semiconductor substrate comprises a source line floating gate region and a plurality of word line bit line regions, wherein the source line floating gate region is positioned between adjacent word line bit line regions, each word line bit line region comprises a first word line bit line region and a second word line bit line region, and the first word line bit line region is positioned between the second word line bit line region and the source line floating gate region; the floating gate structure is positioned on the semiconductor substrate of the source line floating gate region; a first side wall located on the floating gate structure; an opening located between the floating gate structure and the first sidewall, the opening exposing a portion of the surface of the source line floating gate region semiconductor substrate; a source line layer located within the opening; the first word line structure is positioned on the semiconductor substrate in the first word line bit line area, covers the first side wall and the side wall of the floating gate structure, and comprises a first word line oxide layer covering the surface of the semiconductor substrate in the first word line bit line area; and the second word line structure is positioned on the semiconductor substrate of the second word line bit line region and comprises a second word line oxide layer, and the second word line oxide layer covers the side wall of the first word line structure and the second word line oxide layer on the surface of the semiconductor substrate of the second word line bit line region.
Optionally, the thickness of the first word line oxide layer is 120 to 180 angstroms.
Optionally, the thickness of the second word line oxide layer is greater than the thickness of the first word line oxide layer.
Optionally, the thickness of the second word line oxide layer is 180 to 240 angstroms.
Optionally, the thickness of the second word line oxide layer is smaller than that of the first word line oxide layer.
Optionally, the thickness of the second word line oxide layer is 60 to 120 angstroms.
Optionally, the word line bit line region further includes a third word line bit line region, and the second word line bit line region is located between the first word line bit line region and the third word line bit line region; the flash memory further includes: a bit line located on the third word line bit line region.
Optionally, the method further includes: forming a first plug over the first word line structure; and forming a second plug on the second word line structure, wherein the first plug is electrically connected with the second plug.
Optionally, the first word line structure further includes: the first word line layer is positioned on the surface of the first word line oxide layer, and the first plug is connected with the first word line layer; the second word line structure further includes: the second word line layer is positioned on the surface of the second word line oxide layer; the second plug is connected to a second word line layer.
Optionally, the method further includes: and the source region is positioned in the semiconductor substrate at the bottom of the source line layer.
Correspondingly, the invention also provides a method for forming any flash memory, which comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises a source line floating gate region and a plurality of word line bit line regions, the source line floating gate region is positioned between adjacent word line bit line regions, each word line bit line region comprises a first word line bit line region and a second word line bit line region, and the first word line bit line region is positioned between the second word line bit line region and the source line floating gate region; forming a floating gate structure positioned on the source line floating gate region, a first side wall positioned on the floating gate structure and an opening positioned between the floating gate structure and the first side wall, wherein the opening exposes part of the surface of the semiconductor substrate of the source line floating gate region; forming a source line layer in the opening; after a source line layer is formed, forming a first word line structure on the semiconductor substrate in the first word line bit line region, wherein the first word line structure covers the first side wall and the side wall of the floating gate structure, and the first word line structure comprises a first word line oxide layer covering the surface of the semiconductor substrate in the first word line bit line region; and after the first word line structure is formed, forming a second word line structure on the semiconductor substrate in the second word line bit line region, wherein the second word line structure comprises a second word line oxide layer, and the second word line oxide layer covers the side wall of the first word line structure and the second word line oxide layer on the surface of the semiconductor substrate in the second word line bit line region.
Optionally, the method for forming the first word line structure includes: forming an initial first word line structure on the semiconductor substrate in the word line bit line region, wherein the initial first word line structure covers the floating gate structure and the side wall of the first side wall; and removing part of the initial first word line structure, exposing the surface of the semiconductor substrate in the second word line bit line region, and forming the first word line structure.
Optionally, the method for forming the initial first word line structure includes: forming an initial first word line oxide film on the semiconductor substrate of the word line bit line region, the source line layer and the first side wall; forming an initial first word line film on the surface of the initial first word line film; and etching back the initial first word line film and the initial first word line oxide film until the surface of the source line layer is exposed, and forming an initial first word line structure on the surface of the semiconductor substrate in the word line and bit line region.
Optionally, the word line bit line region further includes a third word line bit line region, and the second word line bit line region is located between the first word line bit line region and the third word line bit line region; after forming the second word line structure, forming a bit line on the third word line bit line region.
Optionally, the method for forming the second word line structure includes: forming an initial second word line structure on the second word line bit region and the third word line region semiconductor substrate, wherein the initial second word line structure covers a third side wall of the first word line structure; and removing part of the initial second word line structure, exposing the surface of the semiconductor substrate in the third word line bit line region, and forming a second word line structure.
Optionally, the method for forming the initial second word line structure includes: forming an initial second word line oxide film on the semiconductor substrate of the second word line bit line region and the third word line region, and on the source line layer and the first side wall; forming an initial second word line film on the surface of the initial second word line film; and etching back the initial second word line film and the initial second word line oxide film until the surface of the source line layer is exposed, and forming an initial second word line structure on the surfaces of the semiconductor substrates of the first word line bit line region and the third word line region.
Optionally, the source line floating gate region includes a source line region and a plurality of floating gate regions, the floating gate regions are adjacent to the source line region and located at two sides of the source line region, and the floating gate regions are located between the source line region and the first word line bit line region; the method for forming the source line layer, the floating gate structure and the first side wall comprises the following steps: forming a floating gate structure film on a semiconductor substrate; forming a dielectric layer on the floating gate structure film and the semiconductor substrate, wherein the dielectric layer is internally provided with a first opening which exposes the surface of the floating gate structure film on a part of the source line region; forming a first side wall on the side wall of the first opening; after the first side wall is formed, removing the floating gate structure film at the bottom of the first opening by taking the first side wall as a mask until the surface of the semiconductor substrate in the source line region is exposed to form a second opening; forming a second side wall on the side wall of the second opening, wherein the second side wall covers the side wall of the floating gate structure film; forming a source line layer in the first opening and the second opening after forming the second side wall; and after a source line layer is formed, etching and removing the dielectric layer and the floating gate structure film on the word line and bit line region until the surface of the semiconductor substrate in the word line and bit line region is exposed, and forming the floating gate structure.
Optionally, the method further includes: forming a source region in the semiconductor substrate at the bottom of the second opening before forming the source line layer; and after the source line layer is formed, the source region is positioned in the semiconductor substrate at the bottom of the source line layer.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the flash memory provided by the technical scheme of the invention, the word line structure consists of a first word line structure and a second word line structure, the first word line structure is positioned on the semiconductor substrate of the first word line bit line region, and the second word line structure is positioned on the semiconductor substrate of the second word line bit line region. The first word line structure comprises a first word line oxide layer covering the surface of the semiconductor substrate in the first word line bit line region, and the first word line oxide layer also covers the side wall of the floating gate structure; the second word line structure comprises a second word line oxide layer covering the side wall of the first word line structure and the surface of the semiconductor substrate in the second word line bit line area; the first word line oxide layer ensures the isolation between the floating gate structure and the first word line structure, and the performance of the flash memory is improved by adjusting the thickness of the second word line oxide layer.
Furthermore, the thickness of the second word line oxide layer is smaller than that of the first word line oxide layer, so that the channel resistance of the transistor can be reduced, the threshold voltage of the transistor is reduced, the read current of the flash memory after being erased is increased, the erasing efficiency is improved, and the performance of the flash memory is improved.
Furthermore, the thickness of the second word line oxide layer is higher than that of the first word line oxide layer, so that the influence on the threshold voltage below the second word line oxide layer can be reduced and the risk of programming crosstalk can be reduced when the word line structure needs to be etched and ions need to be implanted in the subsequent process, and the performance of the flash memory is improved. In conclusion, the performance of the flash memory is improved.
Drawings
FIG. 1 is a schematic diagram of a flash memory;
fig. 2 to 12 are schematic structural diagrams illustrating a flash memory forming process according to an embodiment of the invention.
Detailed Description
As mentioned in the background, the performance of the prior art flash memory is poor.
A schematic structural diagram of a flash memory, referring to fig. 1, comprising: the semiconductor device comprises a semiconductor substrate 100, wherein the semiconductor substrate 100 comprises a source line floating gate region I and a word line bit line region II, and the source line floating gate region I is positioned between adjacent word line bit line regions II and is adjacent to the word line bit line regions II; a floating gate structure 120 located on the source line floating gate region I, a first sidewall 130 located on the floating gate structure 120, and a source line layer 140 located between the floating gate structure 120 and the first sidewall 130; a source region 110 in the semiconductor substrate 100 at the bottom of the source line layer 140; a word line structure located on the word line bit line region II semiconductor substrate 100, the word line structure covering the floating gate structure 120 and the sidewall 130, the word line structure including a word line oxide layer 151 and a word line layer 152 located on the surface of the word line oxide layer 151; the second sidewall 160 is located on the sidewall of the word line structure, the bit line 170 is located in the semiconductor substrate 100 in the word line bit line region II, and the bit line 170 is located in the drain region 180 in the semiconductor substrate at the bottom of the bit line 170 and the bottom of the second sidewall 160.
In the above structure of the flash memory, the word line structure is composed of a word line oxide layer 151 and a word line layer 152. Word line oxide layer 151 covers the semiconductor substrate surface in word line bit region II and the sidewall of floating gate structure 120, and word line layer 152 is isolated from floating gate structure 220 through word line oxide layer 151, and in order to guarantee the isolation effect, then word line oxide layer 151 thickness is difficult to adjust to lead to the flash memory performance relatively poor.
The word line structure comprises a first word line structure and a second word line structure, wherein the first word line structure comprises a first word line oxide layer, the second word line structure comprises a second word line oxide layer, and the first word line oxide layer covers the side wall of the floating gate structure and the surface of the semiconductor substrate in the first word line bit line region; the second word line oxide layer covers the side wall of the first word line structure and the surface of the semiconductor substrate in the second word line bit line area. The thickness of the second word line oxide layer can be adjusted, and when the thickness of the second word line oxide layer is lower than that of the first word line oxide layer, the channel resistance of the transistor can be reduced, so that the threshold voltage of the transistor is reduced, the read current of the flash memory after being erased is increased, and the erasing efficiency is improved. When the thickness of the second word line oxide layer is higher than that of the first word line oxide layer, the influence on the threshold voltage below the second word line oxide layer can be reduced and the risk of programming crosstalk is reduced when the word line layer needs to be etched and ions need to be implanted in the subsequent process, so that the performance of the flash memory is improved. In conclusion, the performance of the flash memory is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 12 are schematic structural diagrams illustrating a flash memory forming process according to an embodiment of the invention.
Referring to fig. 2, a semiconductor substrate 200 is provided.
The semiconductor substrate 200 provides a process platform for forming flash memory.
The semiconductor substrate 200 is provided with a plurality of word line bit line regions a and source line floating gate regions B, the source line floating gate regions B are located between adjacent word line bit line regions a, the source line floating gate regions are adjacent to the word line bit line regions, the word line bit line regions include a first word line bit line region and a second word line bit line region, and the first word line bit line region is located between the second word line bit line region and the source line floating gate regions.
The source line floating gate region B comprises a source line region and a plurality of floating gate regions, the floating gate regions are adjacent to the source line region and located on two sides of the source line region, and the floating gate regions are located between the source line region and the first word line bit line region.
In this embodiment, the word line bit line region further includes a third word line bit line region, and the second word line bit line region is located between the first word line bit line region and the third word line bit line region.
The material of the semiconductor substrate 200 may be silicon, germanium or silicon germanium. The semiconductor substrate 200 may also be a silicon-on-insulator (SOI), germanium-on-insulator (GeOI), or silicon-germanium-on-insulator (SiGeOI). In this embodiment, the material of the semiconductor substrate 200 is monocrystalline silicon.
Then, forming a floating gate structure positioned on the source line floating gate region, a first side wall positioned on the floating gate structure and an opening positioned between the floating gate structure and the first side wall, wherein the opening exposes part of the surface of the semiconductor substrate of the source line floating gate region; a source line layer is formed within the opening.
With continued reference to fig. 2, a floating gate structure film 201 is formed on a semiconductor substrate 200; a dielectric layer 202 is formed on the floating gate structure film 201, the dielectric layer 202 has a first opening 203 therein, and the first opening 203 exposes a portion of the surface of the floating gate structure film 210 on the source line region.
In this embodiment, the method further includes: a substrate isolation layer located in a portion of the semiconductor substrate 200 is also formed in the process of forming the floating gate structure film 201. The substrate isolation layer is made of silicon oxide.
The floating gate structure film 201 includes a floating gate oxide film and a floating gate film on the floating gate oxide film.
The floating gate structure film 201 corresponds to the position of the active region.
The material of the dielectric layer 202 includes silicon nitride or silicon oxynitride.
The method for forming the dielectric layer 202 comprises the following steps: forming a dielectric film (not shown) on the floating gate structure film 201 and the substrate isolation layer; forming a first patterned mask layer on the dielectric film, wherein the first mask layer exposes a part of the dielectric film; etching the dielectric film by taking the first mask layer as a mask to form a dielectric layer 202 by the dielectric film; and removing the first mask layer.
The first opening 203 provides a space for subsequently forming a first sidewall and a source line layer.
Referring to fig. 3, a first sidewall 230 is formed at a sidewall of the first opening 203.
The first side wall 230 is made of silicon oxide or silicon oxynitride. The material of the first sidewall spacers 230 is different from the material of the dielectric layer 202.
The method for forming the first sidewall spacers 230 includes: forming a first sidewall film (not shown) in the first opening 203 and on the dielectric layer 202; the first sidewall film is etched back until the surface of the dielectric layer 202 is exposed, forming a first sidewall 230.
In this embodiment, the method further includes: before the first sidewall 230 is formed in the first opening 203, the floating gate structure film at the bottom of the first opening 203 is etched, so that the surface of the floating gate structure film 201 exposed by the first opening 203 is recessed.
In other embodiments, before forming the first sidewall spacers 230 in the first openings, the floating gate structure film at the bottom of the first openings is not etched, and accordingly, the surfaces of the floating gate structure film exposed by the first openings 203 are planar.
With reference to fig. 3, after the first sidewall 230 is formed, the first sidewall 230 is used as a mask to remove the floating gate structure film 201 at the bottom of the first opening 203 until the surface of the semiconductor substrate 200 is exposed to form a second opening 232; and forming a second side wall 231 on the side wall of the second opening 232, wherein the second side wall 231 covers the side wall of the floating gate structure film 201.
The bottom of the second opening 232 exposes the surface of the source line region semiconductor substrate 200.
The second sidewall 231 is used to isolate a source line layer and a floating gate structure formed subsequently.
The process of removing the floating gate structure film 201 at the bottom of the first opening 203 is an etching process, such as a dry etching process or a wet etching process.
In this embodiment, the method further includes: source regions 210 are formed in the semiconductor substrate 200 at the bottom of the second opening 232.
The process of forming the source region 210 is an ion implantation process.
Referring to fig. 4, a source line layer 240 is formed in the first opening 203 and the second opening 232.
The source regions 210 are located in the semiconductor substrate 200 at the bottom of the source line layer 240.
The forming method of the source line layer 240 includes: forming a source line film (not shown) in the first opening 203 and the second opening 232, and on the first sidewall 230 and the dielectric layer 202; the source line film is planarized until the surface of the dielectric layer 202 is exposed, and a source line layer 240 is formed in the first opening 203 and the second opening 232.
The source line film is made of polycrystalline silicon.
The process of forming the source line film is a deposition process such as a plasma chemical vapor deposition process, a low pressure chemical vapor deposition process, or a sub-atmospheric pressure chemical vapor deposition process.
With continued reference to fig. 4, after the source line layer 240 is formed, the dielectric layer and the floating gate structure film 201 on the word line bit line region a are etched and removed until the surface of the semiconductor substrate 200 in the word line bit line region a is exposed, so as to form the floating gate structure 220.
The process of removing the dielectric layer 202 and the floating gate structure film 201 on the word line bit line region a by etching is an anisotropic dry etching process or an anisotropic wet etching process.
In this embodiment, the process of removing the dielectric layer 202 and the floating gate structure film 201 on the word line bit line region a by etching is an anisotropic dry etching process.
The floating gate structure 220 includes a floating gate dielectric layer and a floating gate on the floating gate dielectric layer. The floating gate dielectric layer is formed by the floating gate oxide layer, and the floating gate is formed by the floating gate film.
In this embodiment, removing a portion of the first sidewall 230 on the floating gate structure 220 to expose a portion of the top surface of the floating gate structure 220 is further included.
The floating gate structure 220 has a first sidewall facing away from the source line layer 240 in the channel direction, the first sidewall 230 has a second sidewall facing away from the source line layer 240 in the channel direction, the first sidewall is planar, the first sidewall protrudes toward the source line layer 240 relative to the second sidewall, and the first sidewall and the second sidewall are discontinuous.
The floating gate structure 220 also has a fourth sidewall facing the source line layer 240.
In this embodiment, since the surface of the floating gate structure film 201 exposed by the first opening 203 is recessed, after the floating gate structure 220 is formed, the surface of the floating gate structure 220 facing the first sidewall 230 is recessed, and the thickness of the edge region of the floating gate structure 220 is greater than the thickness of the middle region of the floating gate structure 220, so that the top end of the fourth sidewall is sharp. Electrons are easy to gather at the sharp corner of the floating gate structure, and when the erasing operation is carried out, the electrons are easy to tunnel into the word line structure from the sharp corner, so that the erasing efficiency is improved.
In other embodiments, the top surface and the sidewall surface of the floating gate structure 220 are vertical, and the top end of the fourth sidewall has no sharp corner.
Next, a word line structure is formed on the word line bit line region a semiconductor substrate 200. In this embodiment, the word line structure includes a first word line structure and a second word line structure. The first word line structure is located on the first word line bit line region semiconductor substrate, and the second word line structure is located on the second word line bit line region semiconductor substrate.
The forming method of the first word line structure comprises the following steps: forming an initial first word line structure on the semiconductor substrate in the word line bit line region, wherein the initial first word line structure covers the floating gate structure and the side wall of the first side wall; and removing part of the initial first word line structure, exposing the surface of the semiconductor substrate in the second word line bit line region, and forming the first word line structure. Please refer to fig. 5 to 8.
Referring to fig. 5, a first word line oxide film 204 is formed on the source line layer 240, the first sidewall 230, and the word line bit line region a semiconductor substrate 200.
The material of the first word line oxide film 204 includes: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.
The process of forming the first word line oxide film 204 includes: chemical vapor deposition, physical vapor deposition, or atomic layer deposition processes.
The first word line oxide film 204 provides material for the subsequent formation of an initial first word line oxide layer.
The thickness of the first word line oxide film 204 determines the thickness of a subsequently formed first word line oxide layer that isolates the subsequently formed first word line layer from the floating gate structure.
Referring to fig. 6, a first word line film 205 is formed on the surface of the first word line oxide film 204.
The material of the first word line film 205 is polysilicon.
The first wordline film 205 provides material for the subsequent formation of an initial first wordline layer.
Referring to fig. 7, the first word line film 205 and the first word line oxide film 204 are etched back until the top surface of the source line layer 240 is exposed, forming an initial first word line oxide layer 251 and an initial first word line layer 252.
The initial first wordline oxide layer 251 provides material for the subsequent formation of a first wordline oxide layer.
The initial first word line layer 252 provides material for the subsequent formation of a first word line layer.
The initial first word line layer 252 is located on the surface of the initial first word line oxide layer 251, and the initial first word line oxide layer 251 covers the first sidewall and the second sidewall.
The initial first word line oxide layer 251 corresponds to the first word line oxide film 204, and the initial first word line layer 252 corresponds to the first word line film 205.
The initial first word line oxide layer 251 and the initial first word line layer 252 constitute an initial first word line structure.
The initial first word line structure covers the semiconductor substrate 200 surface of the word line bit line region a.
Referring to fig. 8, a portion of the initial first word line structure is removed to expose the surface of the semiconductor substrate 200 in the second word line bit line region, thereby forming a first word line structure.
The first word line structure covers the surface of the first word line bit line region semiconductor substrate 200.
In this embodiment, the word line bit line region a further includes a third word line bit line region; the method of forming the first word line structure includes: forming a patterned third mask layer on the source line layer 240 and the initial first word line structure, the third mask layer exposing a portion of the surface of the initial first word line layer 252; and etching the initial first word line oxide layer 251 and the initial first word line layer 252 by using the third mask layer as a mask until the surfaces of the semiconductor substrate 200 in the second word line bit line region and the third word line bit line region are exposed, so that the initial first word line oxide layer 251 is formed into a first word line oxide layer 253, the initial first word line layer 252 is formed into a first word line layer 254, and a first word line structure is formed.
The thickness of the first word line oxide layer 253 is 120 to 180 angstroms.
If the thickness of the first word line oxide layer 253 is too thin, the isolation effect between the floating gate structure and the first word line layer is poor, and the data retention capability is deteriorated; if the thickness of the first word line oxide layer 253 is too thick, the threshold voltage of the transistor formed by the first word line layer is large, and the erasing effect is not good during the erasing operation.
The first word line structure has a third sidewall that exposes a portion of the first word line oxide layer 253 and a portion of the first word line layer 254 surface.
And after the first word line structure is formed, forming a second word line structure on the semiconductor substrate in the second word line bit line region, wherein the second word line structure covers the third side wall, the second word line structure comprises a second word line oxide layer, and the thickness of the second word line oxide layer is smaller than that of the first word line oxide layer.
In this embodiment, the word line bit line regions further include a third word line bit line region, the third word line bit line region being adjacent to a second word line bit line region, the second word line bit line region being located between the first word line bit line region and the third word line bit line region; the forming method of the second word line structure comprises the following steps: forming an initial second word line structure on the second word line bit region and the third word line region semiconductor substrate, wherein the initial second word line structure covers a third side wall of the first word line structure; and removing part of the initial second word line structure, exposing the surface of the semiconductor substrate in the third word line bit line region, and forming a second word line structure. Please refer to fig. 9 to 11.
Referring to fig. 9, a second word line oxide film 206 is formed on the source line layer 240, the first sidewalls 230 and the first word line structure, and the second and third word line region semiconductor substrate 200.
In this embodiment, the second word line oxide film 206 also covers the surface of the third word line region semiconductor substrate 200.
The material of the second word line oxide film 206 includes: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.
The process of forming the second word line oxide film 206 includes: chemical vapor deposition, physical vapor deposition, or atomic layer deposition processes.
The second word line oxide film 206 provides a material for the subsequent formation of a second word line oxide layer.
The thickness of the second word line oxide film 206 is smaller than the thickness of the first word line oxide film 204.
The thickness of the second word line oxide film 206 determines the thickness of a second word line oxide layer to be formed later, and the thickness of the word line oxide film 204 determines the thickness of the first word line oxide layer 253; the first word line oxide layer 253 covers the surface of the first word line bit line region semiconductor substrate 200, and the second word line oxide layer 261 covers the surface of the second word line bit line region semiconductor substrate 200. The thickness of the second word line oxide layer 261 can be adjusted, and the thickness of the second word line oxide layer 261 is lower than that of the first word line oxide layer 253, so that the channel resistance of the transistor can be reduced, the threshold voltage of the transistor is reduced, the read current of the flash memory after being erased is increased, the erasing efficiency is improved, and the performance of the flash memory is improved.
Referring to fig. 10, a second word line film 207 is formed on the surface of the second word line oxide film 206.
The material of the second word line film 207 is polysilicon.
The second wordline film 207 provides material for the subsequent formation of a second wordline layer.
Referring to fig. 11, the second word line film 207 and the second word line oxide film 206 are etched back until the top surface of the source line layer 240 is exposed, forming an initial second word line oxide layer and an initial second word line layer.
The initial second word line oxide layer and the initial second word line layer constitute an initial second word line structure.
In this embodiment, the method further includes: and removing part of the initial second word line structure on the surface of the semiconductor substrate 200 of the third word line bit line region, exposing the surface of the semiconductor substrate 200 of the third word line bit line region, and forming a second word line structure, wherein the second word line structure covers the surface of the semiconductor substrate 200 of the second word line bit line region.
The second word line structure includes: a second word line oxide layer 261, and a second word line layer 262, the second word line oxide layer 261 corresponding to the second word line oxide film 206, and the second word line layer 262 corresponding to the second word line film 207.
The second word line oxide layer 261 covers the surface of the second word line bit line region semiconductor substrate 200 and the surface of the first word line structure sidewall. The second word line layer 262 is located on the surface of the second word line oxide layer 261.
In one embodiment, the second word line oxide layer 262 is less thick than the first word line oxide layer 254.
The thickness of the second word line oxide layer 261 is 60 to 120 angstroms.
The thickness of the second word line oxide layer is smaller than that of the first word line oxide layer, so that the channel resistance of the transistor can be reduced, the threshold voltage of the transistor is reduced, the read current of the flash memory after being erased is increased, the erasing efficiency is improved, and the performance of the flash memory is improved.
In another embodiment, the thickness of the second word line oxide layer 261 is greater than the thickness of the first word line oxide layer 253.
The thickness of the first word line oxide layer 253 is 120 to 180 angstroms.
The thickness of the second word line oxide layer 261 is 180 to 240 angstroms.
The thickness of the second word line oxide layer 261 is greater than that of the first word line oxide layer 253, and the thickness of the second word line oxide layer 261 is greater than that of the first word line oxide layer 253, so that the threshold voltage below the second word line oxide layer 261 is higher, and when a word line structure needs to be etched and ion implantation needs to be performed in subsequent processes, the influence on the threshold voltage below the second word line oxide layer is reduced, the risk of programming crosstalk is reduced, and the performance of the flash memory is improved.
The material of the second wordline layer 262 is polysilicon.
The first word line structure and the second word line structure together constitute a word line structure of the flash memory.
Referring to fig. 12, after forming the second word line structure, a bit line 290 is formed on the third word line bit line region.
Before forming the bit line 290, the method further includes: forming spacers 270 on sidewalls of the second word line layer 262; taking the first side wall 240, the source line layer 240, the spacer layer 270 and the word line structure as masks, performing drain ion implantation on the semiconductor substrate 200 at the side part of the spacer layer 270, and forming a drain doped region in the semiconductor substrate 200 at the side part of the spacer layer 270; the drain doped region is then subjected to a drain annealing process to form a drain region 280.
The drain region 280 is located between adjacent word line structures. The drain regions 281 are used to electrically connect bit lines.
After the drain region 280 is formed, the drain region 280 at the side of the spacer 270 is ion-doped using the spacer 270 and the word line structure as masks, thereby forming the bit line 290.
After forming the bit line 290, the method further includes: forming a first plug on the first word line structure; and forming a second plug on the second word line structure, wherein the first plug is electrically connected with the second plug.
Specifically, an interlayer dielectric layer is formed on the word line structure and the source line layer 240, and the interlayer dielectric layer covers the word line structure, the source line layer 240 and the bit line 290; respectively forming a first groove and a second groove in the interlayer dielectric layer, wherein the first groove exposes part of the first word line structure, and the second groove exposes part of the second word line structure; forming a first plug in the first trench, the first plug being connected to a first word line layer 254; forming a second plug in the second trench, the second plug being connected to a second wordline layer 262; a connection layer is formed between the first plug and the second plug.
When a voltage is applied across the first or second plugs, the voltage is applied across first and second word line layers 254 and 262.
Accordingly, the present invention provides a flash memory formed by any one of the above methods, comprising: the semiconductor substrate 200 comprises a source line floating gate region B and a plurality of word line bit line regions A, wherein the source line floating gate region B is positioned between the adjacent word line bit line regions A, the source line floating gate region B is adjacent to the word line bit line regions A, each word line bit line region A comprises a first word line bit line region and a second word line bit line region, and the first word line bit line region is positioned between the second word line bit line region and the source line floating gate region B; a floating gate structure 220 on the source line floating gate region B semiconductor substrate 200; a first sidewall 230 on the floating gate structure 220; an opening between the floating gate structure 220 and the first sidewall 230, the opening exposing a portion of the surface of the source line floating gate region B semiconductor substrate 200; a source line layer 240 located within the opening; a first word line structure located on the first word line bit line region semiconductor substrate 200, the first word line structure covering the first sidewall 230 and the floating gate structure 220 sidewall, the first word line structure including a first word line oxide layer 253 covering the surface of the first word line bit line region semiconductor substrate 200, the first word line oxide layer 253 covering the surface of the first word line bit line region semiconductor substrate; and the second word line structure is positioned on the second word line bit line region semiconductor substrate 200, covers the side wall of the first word line structure, and comprises a second word line oxide layer 261 covering the surface of the second word line bit line region semiconductor substrate 200.
The thickness of the first word line oxide layer 253 is 120 to 180 angstroms.
In one embodiment, the thickness of the second word line oxide layer 261 is greater than the thickness of the first word line oxide layer 253.
The thickness of the second word line oxide layer 261 is 180 to 240 angstroms.
In another embodiment, the thickness of the second word line oxide layer 261 is less than the thickness of the first word line oxide layer 253.
The thickness of the second word line oxide layer 261 is 60 to 120 angstroms.
The word line bit line region further comprises a third word line bit line region, the second word line bit line region being located between the first word line bit line region and the third word line bit line region; the flash memory further includes: a bit line 290 located in the third word line bit line region semiconductor substrate 200.
Further comprising: forming a first plug over the first word line structure; and forming a second plug on the second word line structure, wherein the first plug is electrically connected with the second plug.
The first word line structure further includes: a first word line layer 254 on the surface of the first word line oxide layer 253, the first plug being connected to the first word line layer 254; the second word line structure further includes: a second word line layer 262 on a surface of the second word line oxide layer 261; the second plug is connected to a second wordline layer 262.
Further comprising: source regions 210 in semiconductor substrate 200 at the bottom of source line layer 240.
The semiconductor substrate 200 refers to the content of the foregoing embodiments, and is not described in detail.
The structure, material and position of the first word line structure refer to the content of the foregoing embodiments, and are not described in detail.
The structure, material and position of the second word line structure refer to the content of the foregoing embodiments, and are not described in detail.
The word line structure is composed of a first word line structure and a second word line structure, the first word line structure is located on the first word line bit line region semiconductor substrate 200, and the second word line structure is located on the second word line bit line region semiconductor substrate 200. The first word line structure comprises a first word line oxide layer covering the surface of the semiconductor substrate 200 in the first word line bit line region, and the first word line oxide layer also covers the side wall of the floating gate structure; the second word line structure includes a second word line oxide layer 261 covering sidewalls of the first word line structure and a surface of the second word line bit line region semiconductor substrate 200; the first word line oxide layer 253 ensures isolation between the floating gate structure 220 and the first word line structure, and improves the performance of the flash memory by adjusting the thickness of the second word line oxide layer 261. The thickness of the second word line oxide layer 261 is lower than that of the first word line oxide layer 253, so that the channel resistance of the transistor can be reduced, the threshold voltage of the transistor can be reduced, the read current of the flash memory after being erased can be increased, the erasing efficiency can be improved, and the performance of the flash memory can be improved. The thickness of the second word line oxide layer 261 is higher than that of the first word line oxide layer 253, so that when a word line structure needs to be etched and ion implantation needs to be performed in subsequent processes, the influence on the threshold voltage below the second word line oxide layer 261 can be reduced, the risk of programming crosstalk is reduced, and the performance of the flash memory is improved. In conclusion, the performance of the flash memory is improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (18)
1. A flash memory, comprising:
the semiconductor substrate comprises a source line floating gate region and a plurality of word line bit line regions, wherein the source line floating gate region is positioned between adjacent word line bit line regions, the source line floating gate region is adjacent to the word line bit line regions, each word line bit line region comprises a first word line bit line region and a second word line bit line region, and the first word line bit line region is positioned between the second word line bit line region and the source line floating gate region;
the floating gate structure is positioned on the semiconductor substrate of the source line floating gate region;
a first side wall located on the floating gate structure;
the opening is positioned in the floating gate structure and the first side wall, and part of the surface of the semiconductor substrate of the source line floating gate region is exposed by the opening;
a source line layer located within the opening;
the first word line structure is positioned on the semiconductor substrate in the first word line bit line area, covers the first side wall and the side wall of the floating gate structure, and comprises a first word line oxide layer covering the surface of the semiconductor substrate in the first word line bit line area;
and the second word line structure is positioned on the semiconductor substrate of the second word line bit line region and comprises a second word line oxide layer, and the second word line oxide layer covers the side wall of the first word line structure and the second word line oxide layer on the surface of the semiconductor substrate of the second word line bit line region.
2. The flash memory of claim 1 wherein the first word line oxide layer has a thickness of 120-180 angstroms.
3. The flash memory of claim 2 wherein the thickness of the second word line oxide layer is greater than the thickness of the first word line oxide layer.
4. The flash memory of claim 3 wherein the second word line oxide layer has a thickness of 180 to 240 angstroms.
5. The flash memory of claim 2 wherein the thickness of the second word line oxide layer is less than the thickness of the first word line oxide layer.
6. The flash memory of claim 5 wherein the second word line oxide layer has a thickness of 60 to 120 angstroms.
7. The flash memory of claim 1, wherein the word line bit line region further comprises a third word line bit line region, the second word line bit line region being located between the first word line bit line region and the third word line bit line region; the flash memory further includes: and bit lines in the semiconductor substrate of the third word line bit line region.
8. The flash memory according to claim 1, further comprising: forming a first plug over the first word line structure; a second plug on the second word line structure, the first plug electrically connected to the second plug.
9. The flash memory of claim 8, wherein the first word line structure further comprises: the first word line layer is positioned on the surface of the first word line oxide layer, and the first plug is connected with the first word line layer; the second word line structure further includes: the second word line layer is positioned on the surface of the second word line oxide layer; the second plug is connected to a second word line layer.
10. The flash memory according to claim 1, further comprising: and the source region is positioned in the semiconductor substrate at the bottom of the source line layer.
11. A method of forming a flash memory device according to any one of claims 1 to 10, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a source line floating gate region and a plurality of word line bit line regions, the source line floating gate region is positioned between adjacent word line bit line regions, the source line floating gate region is adjacent to the word line bit line regions, each word line bit line region comprises a first word line bit line region and a second word line bit line region, and the first word line bit line region is positioned between the second word line bit line region and the source line floating gate region;
forming a floating gate structure positioned on the source line floating gate region, a first side wall positioned on the floating gate structure and an opening positioned in the floating gate structure and the first side wall, wherein the opening exposes part of the surface of the semiconductor substrate of the source line floating gate region;
forming a source line layer in the opening;
after a source line layer is formed, forming a first word line structure on the semiconductor substrate in the first word line bit line region, wherein the first word line structure covers the first side wall and the side wall of the floating gate structure, and the first word line structure comprises a first word line oxide layer covering the surface of the semiconductor substrate in the first word line bit line region;
and after the first word line structure is formed, forming a second word line structure on the semiconductor substrate in the second word line bit line region, wherein the second word line structure comprises a second word line oxide layer, and the second word line oxide layer covers the side wall of the first word line structure and the second word line oxide layer on the surface of the semiconductor substrate in the second word line bit line region.
12. The method of claim 11, wherein the method of forming the first word line structure comprises: forming an initial first word line structure on the semiconductor substrate in the word line bit line region, wherein the initial first word line structure covers the floating gate structure and the side wall of the first side wall; and removing part of the initial first word line structure, exposing the surface of the semiconductor substrate in the second word line bit line region, and forming the first word line structure.
13. The method of forming a flash memory device according to claim 12, wherein the method of forming the initial first word line structure comprises: forming an initial first word line oxide film on the semiconductor substrate of the word line bit line region, the source line layer and the first side wall; forming an initial first word line film on the surface of the initial first word line film; and etching back the initial first word line film and the initial first word line oxide film until the surface of the source line layer is exposed, and forming an initial first word line structure on the surface of the semiconductor substrate in the word line and bit line region.
14. The method of claim 11, wherein the word line bit line region further comprises a third word line bit line region, the second word line bit line region being located between the first word line bit line region and the third word line bit line region; after forming the second word line structure, forming a bit line on the third word line bit line region.
15. The method of claim 12, wherein the second word line structure comprises: forming an initial second word line structure on the second word line bit region and the third word line region semiconductor substrate, wherein the initial second word line structure covers a third side wall of the first word line structure; and removing part of the initial second word line structure, exposing the surface of the semiconductor substrate in the third word line bit line region, and forming a second word line structure.
16. The method of claim 12, wherein the method of forming the initial second word line structure comprises: forming an initial second word line oxide film on the semiconductor substrate of the second word line bit line region and the third word line region, and on the source line layer and the first side wall; forming an initial second word line film on the surface of the initial second word line film; and etching back the initial second word line film and the initial second word line oxide film until the surface of the source line layer is exposed, and forming an initial second word line structure on the surfaces of the semiconductor substrates of the first word line bit line region and the third word line region.
17. The method for forming the flash memory according to claim 11, wherein the source line floating gate region includes a source line region and a plurality of floating gate regions, the floating gate regions are adjacent to and located at two sides of the source line region, and the floating gate regions are located between the source line region and the first word line bit line region;
the method for forming the source line layer, the floating gate structure and the first side wall comprises the following steps:
forming a floating gate structure film on a semiconductor substrate; forming a dielectric layer on the floating gate structure film and the semiconductor substrate, wherein the dielectric layer is internally provided with a first opening which exposes the surface of the floating gate structure film on a part of the source line region; forming a first side wall on the side wall of the first opening; after the first side wall is formed, removing the floating gate structure film at the bottom of the first opening by taking the first side wall as a mask until the surface of the semiconductor substrate in the source line region is exposed to form a second opening; forming a second side wall on the side wall of the second opening, wherein the second side wall covers the side wall of the floating gate structure film; forming a source line layer in the first opening and the second opening after forming the second side wall; and after a source line layer is formed, etching and removing the dielectric layer and the floating gate structure film on the word line and bit line region until the surface of the semiconductor substrate in the word line and bit line region is exposed, and forming the floating gate structure.
18. The method of claim 17, further comprising: forming a source region in the semiconductor substrate at the bottom of the second opening before forming the source line layer; and after the source line layer is formed, the source region is positioned in the semiconductor substrate at the bottom of the source line layer.
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