CN1503351A - Method for mfg of self-aligned three-division grid non-vilatile storage element - Google Patents
Method for mfg of self-aligned three-division grid non-vilatile storage element Download PDFInfo
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- CN1503351A CN1503351A CNA021490619A CN02149061A CN1503351A CN 1503351 A CN1503351 A CN 1503351A CN A021490619 A CNA021490619 A CN A021490619A CN 02149061 A CN02149061 A CN 02149061A CN 1503351 A CN1503351 A CN 1503351A
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- 238000000034 method Methods 0.000 title claims description 55
- 238000003860 storage Methods 0.000 title abstract description 3
- 238000004519 manufacturing process Methods 0.000 claims abstract description 65
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 45
- 229920005591 polysilicon Polymers 0.000 claims abstract description 44
- 238000002955 isolation Methods 0.000 claims abstract description 24
- 238000000151 deposition Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims description 31
- 150000002500 ions Chemical class 0.000 claims description 22
- 230000008021 deposition Effects 0.000 claims description 14
- 239000007943 implant Substances 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 12
- 229910017052 cobalt Inorganic materials 0.000 claims description 8
- 239000010941 cobalt Substances 0.000 claims description 8
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 8
- -1 phosphonium ion Chemical class 0.000 claims description 8
- 238000006396 nitration reaction Methods 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 5
- 238000001020 plasma etching Methods 0.000 claims description 4
- 229910021332 silicide Inorganic materials 0.000 claims description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 2
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 claims 3
- 230000003647 oxidation Effects 0.000 abstract description 8
- 238000007254 oxidation reaction Methods 0.000 abstract description 8
- 238000009413 insulation Methods 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 8
- 230000001936 parietal effect Effects 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- AIOWANYIHSOXQY-UHFFFAOYSA-N cobalt silicon Chemical compound [Si].[Co] AIOWANYIHSOXQY-UHFFFAOYSA-N 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
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Abstract
A manufacturing method for a self-aligned three-division grid no-vilatile storage element includes forming an insulation oxidation layer on a basis, depositing and self-aligning a first polysilicon layer to an isolation oxidation layer to form several floating grids and then to define a source zone on the basis among the floating grids, deposit a second polysilicon layer on it to be self-aligned to the isolation oxidation layer, depositing a third polysilicon layer adjacent to the floating grid to be aligned to the isolation layer to form several selected grids and defining a drain zone on the basis.
Description
Technical field
The invention relates to the manufacture method of a kind of non-volatile memory element (Non-volatile MemoryDevice), and particularly relevant for a kind of manufacture method of aiming at triplasy grid (TripleSelf-aligned Split-gate) non-volatile memory element voluntarily.
Background technology
Electrically programmable erasable read-only memory (Electrically Erasable ProgrammableMemory is called for short EEPROM) unit (Cell) is the non-volatile memory cell that writes and erase of the very low operating currents of a kind of need (OperationCurrent).The unit cell of one electrically programmable erasable read-only memory can select transistor (Select Transistor) to form by connecting a memory transistor (Memory Transistor) and.Some electrically programmable erasable read-only memory design is integrated to merge two kinds of transistorized features.Flash memory (FLASH Memory) is a kind of one-transistor unit of similar electrically programmable erasable read-only memory.The size of flash cell approximately is half of electrically programmable erasable read-only memory of two transistor.
The design of flash memory is different from other according to required and have one or several transistorized memory cell structures in every memory cell.Though separable grid flash memory cell is equal to the two transistor structure, only need the space (Real Estate) of Duoing slightly than the shared semiconductor of one-transistor.Flash memory is floated between selection grid (SelSelect Gate) and as one between the silicon base zone of memory cell transistor channel (Channel) and is stored grid (Floating Storage Gate).Erasing, write or reading of this memory cell needs the injection electronics extremely to remove electronics to the floating boom utmost point or from floating boom.And in the combination that different voltages are used in its control grid, source electrode, drain electrode and substrate, erasing, writing and reading with the control store unit.
For the separable grid flash memory is suitably operated, select grid to need to cover the distance of drain electrode (or source electrode) and floating boom interpolar at least.If this segment distance is not fixed, select the length of grid perhaps can need overcompensation because of the difference of distance, can suitably be operated with guarantee separable grid flash memory.And, because the overcompensation (Overcompensation) of selectivity grid length, non-ly aim at the typing (Scaling) that separable grid (Non-self-aligned Split Gate) manufacture craft will hinder the memory cell size size voluntarily.In addition, component characteristic such as program usefulness and memory cell current also will be betided non-alignment error (Misalignment) of aiming at voluntarily in the gate fabrication process and be had a strong impact on.
Summary of the invention
One aspect of the present invention is to describe a kind of manufacture method of aiming at triplasy grid non-volatile memory element voluntarily, is included in and forms an insulating oxide in the substrate.By depositing and aiming at one first polysilicon layer voluntarily on insulating oxide, to form several floating boom utmost points.In the substrate of floating boom interpolar, define the one source pole zone then.Deposition one second polysilicon layer on the source region, and be aligned to relevant insulating oxide voluntarily.In extremely other deposition one the 3rd polysilicon layer of floating boom.Aim at the 3rd polysilicon layer then voluntarily on insulating oxide, select grid to form several.In addition, in substrate, define a drain region at least.
On the other hand, the present invention describes a kind of triplasy grid non-volatile memory element of aiming at voluntarily, comprises an insulating oxide, several floating boom utmost points, one source pole district, several selection grid and contact holes.The floating boom utmost point that wherein has a polysilicon layer is aligned to insulating oxide voluntarily.Be formed with one second polysilicon layer at the source area top of floating boom interpolar.Second polysilicon layer also is aligned to insulating oxide voluntarily.Select grid system in abutting connection with the floating boom utmost point.In addition, select grid also to aim at insulating oxide voluntarily.One contact hole is provided with being connected to a drain region.
For above and other objects of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. elaborate.
Description of drawings
Fig. 1 is the plane graph of known a kind of separable grid flash memory element;
Fig. 2 is the profile of known a kind of separable grid flash memory element;
Fig. 3 to Figure 13 is according to a kind of manufacturing process schematic diagram of aiming at triplasy grid fast-flash memory element voluntarily of a preferred embodiment of the present invention;
Fig. 3 is shown in the other substrate of shallow slot isolation structure, to form the embodiment of an oxide layer in the base top surface;
Fig. 4 is shown in deposition one sacrifice polycrystal layer (Sacrificial PolycrystallineLayer) on the oxide layer;
Fig. 5 is shown in the polysilicon of implementing a control and is etched with definition floating boom polar region;
The source area that Fig. 6 is shown in substrate defines a photoresistance cover curtain layer;
Fig. 7 is shown in and forms the one source pole polysilicon lines on the source area;
Fig. 8 demonstration utilizes a top oxide layer as hard cover screen, to remove an amorphous polysilicon layer (Amorphous Polycrystalline Layer) and a floating boom utmost point polycrystal layer (Floating GatePoly);
Fig. 9 is shown in floating boom utmost point either side and forms polycrystalline selection grid;
Figure 10 shows that mobile entire chip is to prepare to make external equipment (Peripheral Device) unit:
Figure 11 is shown in and forms a thin oxide layer and a drain region in the substrate;
The structural top that Figure 12 is shown in Figure 11 deposits a cobalt layer, aims at silicon cobalt substrate (Cobalt Salicide) voluntarily to form;
Figure 13 is the plane graph according to a kind of flash memory array of a preferred embodiment of the present invention (FLASHMemory Array).
Label declaration
100,200: the separable grid flash memory element
102,1304: shallow-channel isolation region
104,212,214: the floating boom utmost point
106,224,226: select grid
108: the lap position
110,1310: contact hole
112,230,232,1106: the drain region
114,234,604: source area
202,204: memory cell
206,208: tunnel oxide
210,300: substrate
216,218: floating boom utmost point oxide layer
220,222: insulating barrier
240: the gas aggradation manufacture craft
250: distance
302,306,402,504,506,704,706,900,904: oxide layer
304,1000: polycrystal layer
400: sacrifice polycrystal layer
404,502: the floating boom polar region
406: the flash memory cell channel region
408,1102: the nitrogenize clearance wall
600: the photoresistance cover curtain layer
602: ion is implanted manufacture craft
700,1100: the oxidation clearance wall
702: the source electrode polysilicon lines
500,800: structure
902: polycrystalline gap parietal layer
1104: exposed region
1202: aim at cobalt silicide voluntarily
1300: flash memory array
1302: floating boom utmost point polysilicon
1306: the source electrode polysilicon
1308: select grid polycrystalline silicon
Embodiment
Above-mentioned with non-difficulty of aiming at the separable grid manufacture craft voluntarily in order to represent, the present invention narrates an example of aiming at the triplasy gate fabrication process voluntarily.According to embodiments of the invention, the position and the length of the grid of floating/select, and other position in relevant insulating oxide zone (Field Isolation OxideRegion) (the aiming at automatically each other) of aiming at voluntarily.In addition, the source electrode polycrystal layer is also aimed at voluntarily.The position of aiming at voluntarily by identical light shield (Photomask) decision produces.In memory element automatically voluntarily to helping memory cell to dwindle.Therefore the present invention propose a preferred embodiment in order to explanation unrestricted method of the present invention, and be not limited only to this embodiment.
Yet, before embodiments of the invention, for emphasizing the shortcoming of known method, with Fig. 1 with Figure 2 shows that example, Fig. 1 and Fig. 2 are the sketches of known a kind of separable grid flash memory element 100,200.As shown in the figure, the plane graph (Fig. 1) and profile (Fig. 2) that comprise known a kind of separable grid flash memory element 100,200.Plane graph Fig. 1 shows an insulating oxide or shallow trench isolation (Shallow Trench Isolation is called for short STI) district 102.Shallow-channel isolation region 102 is separated an assembly district and another assembly district in driving component district (Active Device Region).Then, between shallow-channel isolation region 102, defined flash memory devices 100,200.And flash memory devices 100,200 comprises various piece (Feature), similarly is the floating boom utmost point (Floating Gate) 104 of definition and lap shallow-channel isolation region 102.The control of the definition and the cover part floating boom utmost point 104 (or selection) grid (Control Gate or Select Gate) 106.Grid 104 also cover part shallow-channel isolation region 102 in a position 108.Contact hole 110 112 also shows to the drain region.Regional definable one source pole district 114 104 of the floating boom utmost points.
Fig. 2 is the profile along known a kind of separable grid flash memory element 200 of the II-II line that is shown in Fig. 1.Memory element 200 comprises first and second memory cell 202 and 204.Memory element 200 can be created by known semiconductor fab manufacture craft.This manufacture craft is included in and forms tunnel oxide (Tunneling Oxide) 206,208 in the substrate 210, and forms first polysilicon layer on tunnel oxide 206,208.On part first polysilicon layer, form floating boom utmost point oxide layer 216,218.Serve as the cover curtain then, utilize etching process to remove part first polysilicon layer and tunnel oxide 206,208 with floating boom utmost point oxide layer 216,218.Therefore part substrate 210 will come out, and form first and second floating boom utmost point 212,214 by rest parts first polysilicon layer.On the substrate 210 that exposes, the floating boom utmost point 212,214 and floating boom utmost point oxide layer 216,218, form insulating barrier 220,222.On insulating barrier 220,222, deposit one deck conductor layer then.Implement a patterning and etching process to remove partial insulative layer 220,222 and segment conductor layer.This manufacture craft will expose part substrate 210, and form first and second selection grid 224,226 by the rest parts conductor layer.Then, implement a gas aggradation manufacture craft (Gas DepositionProcess) and form drain electrode 230,232 with doped portion substrate 210.
Utilize a gas aggradation manufacture craft 240 to form source area 234 then.This manufacture craft comprises the part substrate 210 that exposes that the deposition ion enters 212,214 of the floating boom utmost points.Normally the sedimentary phosphor ion is to form source area 234.During the deposition manufacture craft, ion can down diffuse in the substrate 210, and diffuses to the floating boom utmost point 212,214 residing basal regions by the part substrate 210 that exposes toward side.The side diffusion (Lateral Diffusion) of ion belongs to source side and goes into manufacture craft (Source Side Injection Process).The diffusion of such side can be the most about to the distance that side extends is 70% of diffusion depth (Diffusion Depth), and wherein diffusion depth is the distance that ion down diffuses to substrate.Because diffusion depth is restricted, the ion side diffusion at the floating boom utmost point 212,214 places also will be subject to distance shown among the figure 250.
Referring again to Fig. 1, will be overlapped in the part 108 of shallow-channel isolation region 102 by the known floating boom utmost point 104 that forms the patterning techniques manufacturing of floating boom electrode structure.Therefore, the known floating boom utmost point (poly-1) 104 is not to be aligned to shallow-channel isolation region 102 voluntarily, so produce alignment error for the first time in this easily.And known control (or selection) grid (poly-2) 106 neither be aligned to shallow-channel isolation region 102 voluntarily, so produce alignment error for the second time in this easily.What is more, known contact hole 110 is not to be aligned to shallow-channel isolation region 102 voluntarily yet, so cause alignment error for the third time.This alignment error of three times will cause bigger cell size.
Embodiment
Therefore, Fig. 3 to Figure 12 is according to a kind of manufacturing process schematic diagram of aiming at triplasy grid fast-flash memory element voluntarily of a preferred embodiment of the present invention.
Fig. 3 shows the substrate 300 through shallow trench isolation (Shallow Trench Isolation is called for short STI) manufacture craft, and forms an oxide layer 302 in substrate 300 top surfaces.The substrate of embodiment comprises semiconductor such as silicon.Substrate 300 can be p type or n N-type semiconductor N material.And the thickness of oxide layer 302 is about 60～120 dusts.And this oxide layer 302 can be to make a memory cell (Cell) carry out the thin oxide layer of sequencing (electronics is pushed the floating boom utmost point).Then, deposit the polycrystal layer (Polycrystalline Layer) 304 of a thickness, for example polysilicon layer (Polysilicon Layer) about 1000～3000 dusts.Polycrystal layer 304 impurity (Impurity) that also can mix is as phosphonium ion (Phosphorus Ions).In an embodiment, polycrystal layer 304 is included in concentration about 1 * 10
19/ cm
3Carrying out ion implants.Then, can increase the oxide layer 306 of another thickness in polycrystal layer 304 tops at 300～1000 dusts.So oxide layer 306 can be used as a cover curtain, need form the position of oxide in order to the control subsequent step.
Fig. 4 is shown in and deposits the sacrifice polycrystal layer (Sacrificial Polycrystalline Layer) 400 of a thickness about 1500～4000 dusts on the oxide layer 306.Another thickness of deposition is in the oxide layer 402 of 300～800 dusts on polycrystal layer 400.Then after accepting known plasma etching (PlasmaEtching),, carry out etching again and remove the oxide layer (Unmasked Oxide) 402 and polycrystal layer 400 of not covered by light shield with light shield definition (Photomasking) floating boom polar region 404.
Subsequently, implement an ion and implant (Ion Implant) to obtain the base concentration that needs as flash memory cell channel region (Channel Area) 406.In an embodiment, the ion of implantation for example is boron (Boron, B
+).This about 150～200KeV of energy dose (Energy Dose) that implants, doping density (Doping Density) is greatly about 1 * 10
12/ cm
2～5 * 10
12/ cm
2Then, deposit the nitration case of a thickness about 300～800 dusts.The deposition of nitration case is along with a plasma etching process, to carry out comprehensive etch-back (Blanket Etching Back).And in figure, show a nitrogenize gap parietal layer that stays (Nitride Spacer Layer) 408.
Please refer to Fig. 5, carry out a control polycrystalline etching process with definition floating boom polar region 502.Then at about 800 ℃～950 ℃ thermal oxide layers 504 of a thickness of growing up down of temperature about 60～120 dusts.Then, deposit the oxide layer 506 of a layer thickness about 4000～6000 dusts.Implement a smooth etch-back (Planar Etch Back) then to produce structure 500 as shown in Figure 5.
Please refer to Fig. 6, will remove, and serve as the cover curtain, with polycrystal layer between the floating boom polar region 502 304 and oxide layer 306 removals with the nitrogenize gap parietal layer 408 of the both sides that are removed the position at the sacrifice polycrystal layer between the floating boom polar region 502 400.Afterwards, on plane oxidation layer 506, form a photoresistance cover curtain layer (Photoresistive Masking Layer) 600.Cover curtain layer 600 is in order to the source area 604 of definition substrate.Then,, carry out an ion and implant manufacture craft 602 with ion implant source polar region 604 as a cover curtain with cover curtain layer 600.In an example, the kind of implantation comprises two kinds.First kind comprises arsenic (Arsenic, the As that implants with 50～100KeV energy
+) ion, implant dosage (ImplantDose) is about 2 * 10
15/ cm
2～8 * 10
15/ cm
2Between.Second kind comprises with 40～80KeV energy implantation phosphorus (Phosphorous, P
+) ion, implant dosage is about 1 * 10
15/ cm
2～6 * 10
15/ cm
2Between.After the implantation manufacture craft is finished, can use wet type to remove (Wet Stripping) or dry plasma cleaning (Dry Plasma Clean) removal photoresist layer 600.
In Fig. 7, use known wet type manufacture craft that the nitrogenize gap parietal layer 408 (seeing also Fig. 6) of source area is removed.Deposition and etch-back one layer thickness are in the oxide layer of 1500～3500 dusts then.Wherein etch-back for example is a known dry etching method.Therefore, etch-back stays the thin oxidation clearance wall 700 of one deck.Then, deposit the polycrystal layer of a layer thickness, and mix with boiler tube (Furnace) or ion implantation mode at 2000～4000 dusts.Then, utilize another smooth etch-back to form source electrode polysilicon lines 702.Then, implement a hot boiler tube manufacture craft, with in source electrode polycrystal layer 702 top growth oxide layers 704, equally in amorphous polysilicon layer (AmorphousPolycrystalline Layer) 400 top growth oxide layers 706.Because crystalline texture (CrystalStructure) is different with doping content (Doping Concentration), oxide layer 704 will be different with 706 thickness.
Then, implement being etched with of a control and remove oxide layer 706 (see figure 7)s, and the thicker oxide layer 704 of major part is still keeping.Then, implementing a succession of etching process, removing amorphous polycrystal layer 400, oxide layer 306 and floating boom utmost point polycrystal layer 304, and is as the hard cover screen (see figure 7) with oxide layer 704 when implementing etching process.Subsequently, for example remove nitrogenize gap parietal layer 408, and implement a polycrystalline edge and clean manufacture craft (Poly Edge Clean) to form as the structure among Fig. 8 800 with Wet-type etching method.
Please refer to Fig. 9, implement a hot boiler tube manufacture craft so that the growth of oxide layer 900 to be provided, wherein the thickness of oxide layer 900 is about 120～300 dusts.Deposit the polysilicon layer of a thickness then about 2000～4000 dusts.And the etch-back polysilicon layer is to form a polycrystalline gap parietal layer 902.In present embodiment, hot boiler tube manufacture craft growth thickness is about the oxide layer 904 of 100～300 dusts.And polycrystalline gap parietal layer 902 forms a selection grid (Select Gate).
In Figure 10, will move whole wafer to prepare the perimeter component unit.Multiple known cover curtain can be used for this preparation (Preparation) with manufacturing process steps.Then, deposit a thickness about the grid polycrystal layer 1000 of 1500～3500 dusts grid as the perimeter component unit.
Figure 11 shows the thin oxide layer of a thickness about 200～500 dusts.This thin oxide layer is deposited on previous oxide layer 900 tops.Then, this thin oxide layer of etch-back is to form a little oxidation clearance wall (Oxide Spacer) 1100.In addition, on the oxidation clearance wall 1100 of the relative exposed region (Open Area) 1104 of source area 604, deposit the nitration case of a thickness at 1200～2400 dusts.Then, this nitration case of etch-back is to form a thin nitrogenize clearance wall (Nitride Spacer) 1102.Then, with an impurity exposed region 1104 is carried out ion and implant manufacture craft, to form a drain region 1106.
Then,, expose drain region 1106, and the total top deposits the cobalt layer (Cobalt Layer) of a layer thickness about 400～2000 dusts, aim at cobalt silicide 1202 voluntarily to form in Figure 12.Therefore, the structure of Figure 12 is a kind of triplasy grid fast-flash memory element of aiming at voluntarily of preferred embodiment of the present invention.And Fig. 3 to Figure 12 shows technique of alignment voluntarily.
Figure 13 shows the plane graph of flash memory array 1300.The array 1300 floating boom utmost point polysilicons 1302 of present embodiment are voluntarily in alignment with shallow slot isolation structure district 1304.And source electrode polysilicon 1306 also is aligned to shallow-channel isolation region 1304 voluntarily.In addition, select grid polycrystalline silicon 1308 also to be aligned to shallow-channel isolation region 1304 voluntarily.At last, contact hole 1310 is aligned to shallow-channel isolation region 1304 too voluntarily.
Below openly make an embodiment who aims at triplasy grid fast-flash memory element voluntarily.This embodiment is presented at the technique of alignment voluntarily that this assembly forms grid and contact hole.This voluntarily technique of alignment will help to dwindle the memory element unit.In a word, three polycrystal layers 1302,1306,1308 are aimed at shallow-channel isolation region 1304 voluntarily.
Though the present invention with a preferred embodiment openly as above; right its is not in order to limiting the present invention, anyly is familiar with this operator, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims.
Claims (34)
1, a kind of manufacture method of aiming at triplasy grid non-volatile memory element voluntarily, this is aimed at triplasy grid non-volatile memory element voluntarily and is formed in the substrate, it is characterized in that: comprising:
Form an isolating oxide layer in this substrate;
By depositing and aiming at one first polysilicon layer voluntarily, to form a plurality of floating boom utmost points to this isolating oxide layer;
Definition one source pole district in this substrate of those floating boom interpolars;
Deposit one second polysilicon layer on this source area, and aim at this second polysilicon layer voluntarily to this isolating oxide layer;
Deposit one the 3rd polysilicon layer in abutting connection with those floating boom utmost points;
Aim at the 3rd polysilicon layer voluntarily to this isolating oxide layer, to form a plurality of selection grids;
At least one drain region of definition in this substrate.
2, manufacture method of aiming at triplasy grid non-volatile memory element voluntarily as claimed in claim 1, it is characterized in that: this substrate comprises silicon.
3, manufacture method of aiming at triplasy grid non-volatile memory element voluntarily as claimed in claim 1, it is characterized in that: this non-volatility memorizer comprises a flash memory devices.
4, manufacture method of aiming at triplasy grid non-volatile memory element voluntarily as claimed in claim 1 is characterized in that: this isolating oxide layer comprises a shallow trench isolation oxide layer.
5, manufacture method of aiming at triplasy grid non-volatile memory element voluntarily as claimed in claim 1, it is characterized in that: the thickness of this isolating oxide layer is between 60～120 dusts.
6, manufacture method of aiming at triplasy grid non-volatile memory element voluntarily as claimed in claim 1, it is characterized in that: the thickness of this first polysilicon layer is between 1000～3000 dusts.
7, manufacture method of aiming at triplasy grid non-volatile memory element voluntarily as claimed in claim 1 is characterized in that: form those floating boom utmost points and comprise with this first polysilicon layer of a doping impurity.
8, manufacture method of aiming at triplasy grid non-volatile memory element voluntarily as claimed in claim 7, it is characterized in that: this impurity comprises phosphonium ion.
9, manufacture method of aiming at triplasy grid non-volatile memory element voluntarily as claimed in claim 7 is characterized in that: this first polysilicon layer is about 1 * 10
19/ cm
3Concentration is carried out ion and is implanted with this impurity.
10, manufacture method of aiming at triplasy grid non-volatile memory element voluntarily as claimed in claim 1 is characterized in that: form this step of those floating boom utmost points, comprising:
Deposition one first oxide layer on this first polysilicon layer;
Deposition one is sacrificed polycrystal layer on this first oxide layer;
Deposit one second oxide layer in this sacrifice polycrystal layer top;
Define this second oxide layer with light shield;
This second oxide layer of etching and this are sacrificed polycrystal layer, to remove the zone that light shield of no use covers.
11, manufacture method of aiming at triplasy grid non-volatile memory element voluntarily as claimed in claim 10 is characterized in that: form this step of those floating boom utmost points, also comprise:
Extremely go up deposition one nitration case in those floating booms;
This nitration case of plasma etching is to form a clearance wall.
12, manufacture method of aiming at triplasy grid non-volatile memory element voluntarily as claimed in claim 11, it is characterized in that: the thickness of this nitration case is between 300～800 dusts.
13, manufacture method of aiming at triplasy grid non-volatile memory element voluntarily as claimed in claim 11 is characterized in that: form this step of those floating boom utmost points, also comprise:
This first polysilicon layer of etching is to define the zone of those floating boom utmost points;
Growth one thermal oxide layer on the zone of those floating boom utmost points that define;
Deposition one the 3rd oxide layer on this thermal oxide layer;
Smooth etching makes the 3rd oxide layer flush with this sacrifice polycrystal layer top surface.
14, manufacture method of aiming at triplasy grid non-volatile memory element voluntarily as claimed in claim 13, it is characterized in that: the thickness of this thermal oxide layer is between 60～120 dusts.
15, manufacture method of aiming at triplasy grid non-volatile memory element voluntarily as claimed in claim 1 is characterized in that: form those floating booms extremely after, also be included in a flash memory cell channel region and implant an ion.
16, manufacture method of aiming at triplasy grid non-volatile memory element voluntarily as claimed in claim 15, it is characterized in that: this ion comprises the boron ion.
17, manufacture method of aiming at triplasy grid non-volatile memory element voluntarily as claimed in claim 15 is characterized in that: implant this energy of ions dosage between 150～200KeV.
18, manufacture method of aiming at triplasy grid non-volatile memory element voluntarily as claimed in claim 15, it is characterized in that: the doping density of implanting this ion is 1 * 10
12/ cm
2～5 * 10
12/ cm
2Between.
19, manufacture method of aiming at triplasy grid non-volatile memory element voluntarily as claimed in claim 13 is characterized in that: also be included in and form a photoresistance cover curtain layer on the 3rd oxide layer and this sacrifice polycrystal layer.
20, manufacture method of aiming at triplasy grid non-volatile memory element voluntarily as claimed in claim 19 is characterized in that: comprise that also with this photoresistance cover curtain layer be the cover curtain, implant an implanting ions in this source area.
21, manufacture method of aiming at triplasy grid non-volatile memory element voluntarily as claimed in claim 20, it is characterized in that: this implanting ions comprises arsenic ion.
22, manufacture method of aiming at triplasy grid non-volatile memory element voluntarily as claimed in claim 21, it is characterized in that: the energy dose of implanting this arsenic ion is between 50～100KeV.
23, manufacture method of aiming at triplasy grid non-volatile memory element voluntarily as claimed in claim 21, it is characterized in that: the doping density of implanting this arsenic ion is 2 * 10
15/ cm
2～8 * 10
15/ cm
2Between.
24, manufacture method of aiming at triplasy grid non-volatile memory element voluntarily as claimed in claim 21 is characterized in that: also comprise the implantation phosphonium ion.
25, manufacture method of aiming at triplasy grid non-volatile memory element voluntarily as claimed in claim 24 is characterized in that: the energy dose of implanting phosphonium ion is between 40～80KeV.
26, manufacture method of aiming at triplasy grid non-volatile memory element voluntarily as claimed in claim 24 is characterized in that: the doping density of implanting phosphonium ion is 1 * 10
15/ cm
2～6 * 10
15/ cm
2Between.
27, manufacture method of aiming at triplasy grid non-volatile memory element voluntarily as claimed in claim 1, it is characterized in that: the thickness of the 3rd polysilicon layer is between 2000～4000 dusts.
28, manufacture method of aiming at triplasy grid non-volatile memory element voluntarily as claimed in claim 1 is characterized in that: also comprise this second polysilicon layer that mixes.
29, manufacture method of aiming at triplasy grid non-volatile memory element voluntarily as claimed in claim 28 is characterized in that: also comprise:
This second polysilicon layer of smooth etching;
In this second polysilicon layer top growth oxide layer.
30, manufacture method of aiming at triplasy grid non-volatile memory element voluntarily as claimed in claim 1 is characterized in that: form those and select this step of grid to comprise:
In one first oxide layer of in this substrate of those floating boom utmost points, growing up;
Deposition one polycrystal layer on this first oxide layer;
This polycrystal layer of etch-back is to form a polycrystalline clearance wall;
Deposition one second oxide layer on this polycrystalline clearance wall.
31, manufacture method of aiming at triplasy grid non-volatile memory element voluntarily as claimed in claim 30 is characterized in that: this first thickness of oxide layer is between 120～300 dusts.
32, manufacture method of aiming at triplasy grid non-volatile memory element voluntarily as claimed in claim 30, it is characterized in that: the thickness of this polycrystal layer is between 2000～4000 dusts.
33, manufacture method of aiming at triplasy grid non-volatile memory element voluntarily as claimed in claim 30 is characterized in that: also be included in this second oxide layer top and deposit a cobalt layer, aim at cobalt silicide voluntarily to form.
34, a kind of triplasy grid non-volatile memory element of aiming at voluntarily is characterized in that: comprising:
One isolating oxide layer is positioned in the substrate;
A plurality of floating boom utmost points, voluntarily in alignment with this isolating oxide layer, those floating boom utmost points comprise one first polysilicon layer;
One second polysilicon layer is formed at the top, one source pole district of this substrate of those floating boom interpolars;
A plurality of selection grids, in abutting connection with those floating boom utmost points, those select grid to be aligned to this isolating oxide layer voluntarily;
One contact hole forms and is connected to a drain region to provide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA021490619A CN1503351A (en) | 2002-11-20 | 2002-11-20 | Method for mfg of self-aligned three-division grid non-vilatile storage element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA021490619A CN1503351A (en) | 2002-11-20 | 2002-11-20 | Method for mfg of self-aligned three-division grid non-vilatile storage element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1503351A true CN1503351A (en) | 2004-06-09 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA021490619A Pending CN1503351A (en) | 2002-11-20 | 2002-11-20 | Method for mfg of self-aligned three-division grid non-vilatile storage element |
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| CN (1) | CN1503351A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109638016A (en) * | 2019-01-02 | 2019-04-16 | 上海华虹宏力半导体制造有限公司 | Flash memory and forming method thereof |
-
2002
- 2002-11-20 CN CNA021490619A patent/CN1503351A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109638016A (en) * | 2019-01-02 | 2019-04-16 | 上海华虹宏力半导体制造有限公司 | Flash memory and forming method thereof |
| CN109638016B (en) * | 2019-01-02 | 2020-07-14 | 上海华虹宏力半导体制造有限公司 | Flash memory and forming method thereof |
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