JP4109460B2 - Nonvolatile semiconductor memory device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device and a manufacturing method thereof, and more particularly, to a flash memory cell having a select gate and a manufacturing method thereof.
[0002]
[Prior art]
A flash memory device not only maintains information stored in its memory cells even when power is not supplied, but also can be electrically erased at high speed while being mounted on a circuit board. It is. Flash memory technology has improved cell structures in various forms. Examples of such various types of cells include a stacked gate cell, a split gate cell, a source side injection cell (SSI cell), and the like. Various such cells are described in detail in US Pat. No. 5,455,792 by YONG-WAN YI.
[0003]
The stack gate cell is a form in which a floating gate and a control gate are sequentially stacked. An example of such a stacked gate cell is disclosed in US Pat. No. 4,698,787 by MUKHERJEE et al. Referring to FIG. 1, a MUKHERJEE cell is formed on a substrate 101. A programming operation is performed on the drain 104 side using CHEI (channel hot electron injection), and an erasing operation is performed on the source 102 side using FN tunneling. Such a stack gate cell has a small size and has been most frequently used as a unit cell of a flash memory device. Another example of a stacked gate cell is H.264. WATANABE et al. (“Novel 0.44um2 Ti-salicide STI cell technology for for high-density NOR flash memories and 75 countries in the world. Explained in the issue.
[0004]
The disadvantage of such a stacked gate cell is the problem of over-erase. The over-erase problem occurs when the floating gate 110 of FIG. 1 is over-discharged during an erase operation with a stacked gate cell. The threshold voltage of an excessively discharged cell shows a negative value. Accordingly, there is a problem in that a current flows even when no cell is selected, that is, when a read voltage is not applied to the control gate 112.
[0005]
In order to solve the problem of over-erasing, cells having two types of structures have been introduced. One is a two-transistor cell disclosed in US Pat. No. 4,558,344 by PERIEGOS, and the other is disclosed in US Pat. No. 4,783,766 by SAMACHISA et al. Split gate cell. A selection transistor was adopted in the PERIEGOS cell. That is, when a cell is not selected, leakage current due to a floating gate in which the selection gate is excessively discharged is prevented. In the same way, in the split gate cell such as SAMACHISA, the problem of over-erasing is solved by using the selection gate channel located under the control gate. That is, the leakage current from the floating gate channel located under the excessively discharged floating gate is prevented by the selection gate region. At this time, the control gate is turned off.
[0006]
The main disadvantage of split gate cells is low programming efficiency. Most conventional split gate cells are programmed by the conventional CHEI scheme. Since the CHEI scheme has low programming efficiency, unnecessary power is consumed and the programming speed is reduced.
[0007]
In order to improve the programming efficiency to the floating gate by the CHEI system, the SSI cell was disclosed in US Pat. No. 4,794,565 by WU et al. And US Pat. No. 5,280,446 by MAR et al. Referring to FIG. 2, an SSI cell such as WU is formed on a substrate 201 having a source 202 and a drain 204. A selection gate 206, also called a side wall gate, is formed on the source side wall of the conventional stack gate structure. Therefore, when a high voltage is applied to the control gate 212, a HEI (hot electron injection) from the source 202 to the floating gate 210 occurs. The SEI cell HEI system is said to improve the programming efficiency by 1,000 to 10,000 times compared to the conventional CHEI system.
[0008]
On the other hand, a new nonvolatile memory cell having a MONOS (metal oxide nitride semiconductor) structure has been proposed in order to lower the program voltage. The MONOS cell includes a thin dielectric film composed of a lower silicon oxide film called a tunnel film, a silicon nitride film, and an upper silicon oxide film called a top oxide film. This thin dielectric film is interposed between the semiconductor substrate and the control gate. The MONOS cell has logic states of “0” and “1”. When electrons are trapped inside the thin dielectric silicon nitride film, it is in a logic “0” state. When electrons are not trapped inside the thin dielectric silicon nitride film, it is in a logic “1” state. is there. An example of a MONOS cell is disclosed in US Pat. No. 5,930,631 by CHIN-HSIEN WANG et al. In the CHIN-HSIEN WANG cell, as shown in FIG. 3, a channel located between a source 402, a drain 404, and a source / drain is formed on a substrate 401. A select gate 406 is formed on the substrate 401. An ONO (Oxide Nitride Oxide) layer 420 is formed on the selection gate 406 and the substrate 401. A control gate 408 is formed on the ONO layer 420. The drain adopts an LDD (lightly doped drain) structure to suppress the generation of hot carriers near the junction of the drain. During the program operation, hot carriers are tunneled to the ONO layer 420 and trapped in the nitride film layer. At this time, a positive bias is applied to the control gate 408, the selection gate 406, and the drain 404, and the source 406 is grounded. During the erase operation, a high voltage is applied to the drain 404 so that the select gate 406 is turned off. Since the erase operation is performed without current flow through the channel, the select gate 406 serves to reduce power consumption.
[0009]
[Problems to be solved by the invention]
Although the prior art has been described above, it is an object of the present invention to provide a non-volatile semiconductor memory device that can minimize the size of a cell and reduce power consumption during a program operation.
[0010]
It is another object of the present invention to provide a method for manufacturing a nonvolatile semiconductor memory device that can minimize the cell size and reduce power consumption during a program operation.
[0011]
[Means for Solving the Problems]
The nonvolatile semiconductor memory device of the present invention includes a charge storage region stacked on a substrate, a control gate stacked on the charge storage region, and a gate mask stacked on the control gate. The gate mask has a spacer shape.
[0012]
Another nonvolatile semiconductor memory device of the present invention includes a substrate having a source and a drain. The substrate has a channel formed between the source and the drain. A charge storage region is formed on the channel and a control gate is formed on the charge storage region. A select gate is formed on the channel between the charge storage region and the drain. The charge storage region, the channel, the source, the drain, the selection gate, and the control gate constitute a first unit cell.
[0013]
The method for manufacturing a nonvolatile semiconductor memory device of the present invention includes a step of forming a charge storage layer on a substrate and a step of forming a control gate layer on the charge storage layer. A gate mask having a spacer shape is formed on the control gate layer. The charge storage layer and the control gate layer are partially removed. At this time, the gate mask protects predetermined regions of the charge storage layer and the control gate layer so that the control gate and the charge storage region are formed.
[0014]
In a preferred embodiment of the present invention, a selection gate is formed on the upper portion of the substrate and the side wall of the charge storage region, and a conductive region is formed on the substrate adjacent to the other side wall of the charge storage region. The charge storage region, the control gate, the gate mask, and the selection gate constitute a first unit cell, and the second unit cell that maintains a symmetrical relationship with the first unit cell can share the conductive region.
[0015]
The first unit cell may include an LDD spacer on the side wall of the selection gate. A drain can be formed in the substrate adjacent to the select gate on the side opposite the conductive region, and the bit line electrode can be electrically connected to the drain. A source electrode electrically isolated from the control gate by a source sidewall spacer may be formed on the conductive region.
[0016]
The selection gate preferably has a spacer shape, and the charge storage region is formed by sequentially forming a floating gate dielectric film, a floating gate, and an interpoly dielectric film on the substrate. In addition, the charge storage region can be composed of an ONO layer.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0018]
FIG. 4 is a circuit diagram for explaining the arrangement of the flash memory cells of the present invention. The flash memory device of the present invention includes a plurality of flash memory cells arranged in a matrix form. That is, the cells are arranged in the vertical direction and the horizontal direction. The unit cell is located at each intersection formed by a plurality of word lines WL and a plurality of bit lines BL in the matrix. There are as many cells inside the matrix as 'm' multiplied by 'n'. 'm' is the number of cells in the horizontal direction, and 'n' is the number of cells in the vertical direction. The unit cell is composed of cells of the first embodiment and the second embodiment which will be described later. The bit lines are extended in the vertical direction, and the word lines are extended in the horizontal direction. The array includes a plurality of selection lines SL and a plurality of common source lines CS. The selection line and the common source line are extended in the horizontal direction. The word line and the selection line are symmetrically arranged in the vertical direction with respect to the corresponding common source line. This is because the two unit cells have one common source line and the structure of the two unit cells is symmetric.
[0019]
FIG. 5 is a schematic plan view for explaining the flash memory cell according to the first embodiment of the present invention. FIG. 6 is a schematic cross-sectional view according to II ′ of FIG. 5 and 6 include two unit cells that are symmetric with respect to the source electrode 530 and the source 502. That is, the two unit cells share the source electrode 530 and the source 502, and the components formed on the left side of the source electrode 530 and the source 502 constitute one unit cell, and are formed on the right side of the source electrode 530 and the source 502. The formed component constitutes another unit cell. The two unit cells of FIG. 5 are repeated in the horizontal and vertical directions on the plane to form an array.
[0020]
Referring to FIG. 6, the first conductive type substrate 501 includes conductive regions, that is, a source 502 and a drain. Source 502 and drain are separated by a channel. The conductive region consists of an impurity doping region. The drain is composed of an LDD region 534, a HALO region 536 and a high concentration region 538. Source 502 is a second conductivity type that is the opposite conductivity type of the first conductivity type. The LDD region 534 and the high concentration region 538 are of the second conductivity type. However, the LDD region 534 has a lower concentration than the high concentration region 538 and a shallow junction depth. The HALO region 536 is of the first conductivity type and is located under the LDD region 534. The charge storage region is located above the channel and adjacent to the source 502. The charge storage region includes a floating gate dielectric 514, a floating gate 510 ′, and an interpoly dielectric 516. A control gate 512 ′ and a gate mask 526 ′ are sequentially stacked on the charge storage region. As shown in the figure, the control gate 512 ′ has a spacer shape. The source side spacer 528 is located on the side wall of the charge storage region and the control gate 512 ′. Source electrode 530 is in electrical contact with source 502. The source electrode 530 is separated from the charge storage region and the control gate 512 ′ by a source-side spacer 528 and is electrically insulated. A selection gate dielectric layer 532 is formed on the charge storage region and the other side wall of the control gate 512 ′, on the control gate 512 ′, and on a channel in a predetermined region. A selection gate 506 having a spacer shape is formed on the selection gate dielectric film 532. An LDD spacer 540 is formed on the side wall of the select gate 506. A bit line contact 546 is formed in the insulating film 542. A bit line electrode 544 is formed on the insulating film 542 and inside the bit line contact 546. The bit line electrode 544 is in electrical contact with the drain.
[0021]
Referring to FIG. 5, the active region 548 is extended to adjacent cells in the vertical direction on the substrate 501. Although not shown, there is an isolation region between the active region 548 and another active region adjacent to the active region 548, and the two active regions are separated. The active region 548 includes a source 502, a drain and a channel. The floating gate 510 'is electrically isolated from the other components of the cell and does not extend to adjacent cells. The control gate 512 ′, the gate mask 526 ′, the source side spacer 528, the source electrode 530, the selection gate 506, and the LDD spacer 540 are extended to adjacent cells in the lateral direction. The word line WL is composed of a control gate 512 ′. The common source line CS is composed of the source electrode 530. The selection line SL is composed of a selection gate 506. The bit line BL is composed of a bit line electrode 544. Although not shown, the bit line electrode 544 is extended to adjacent cells in the vertical direction.
[0022]
In the second embodiment of the present invention, the charge storage region is composed of an ONO layer formed on a substrate. The ONO layer is extended to adjacent cells in the lateral direction. Other components are the same as those of the first embodiment of the present invention.
[0023]
In the example of the cell program operation described in the first and second embodiments, CHEI may be used. That is, a program voltage having a positive value of a predetermined condition is applied to the word line WL and the bit line BL so that electrons are trapped in the floating gate 510 ′ or the nitride film of the ONO layer. In addition, a selection voltage having a predetermined positive value is applied to the selection line SL to limit the current flowing between the source 502 and the drain. Therefore, an increase in power consumption can be prevented. The selection voltage also induces a strong lateral electric field in the channel adjacent to the boundary region between the selection gate 506 and the charge storage region, thereby increasing the program efficiency. The selection voltage must be high enough to cause inversion in the channel below the selection gate.
[0024]
In the example of the cell erasing operation, HHI (hot hole injection) can be used. That is, an erase voltage having a predetermined positive value is applied to the bit line BL so that the hot holes are captured by the floating gate 510 ′ or the nitride film of the ONO layer. The word line WL is grounded. In addition, by applying another selection voltage having a predetermined positive value to the selection gate 506 to accelerate hot holes, hot hole injection is enhanced.
[0025]
7 to 26 are schematic views for explaining a method of manufacturing a flash memory cell according to the first embodiment of the present invention. 7 to 16 are sectional views according to II-II ′ of FIGS. 17 to 26, and FIGS. 17 to 26 are plan views.
[0026]
7 and 17, although not shown in FIG. 17, the substrate 501 is preferably made of single crystal silicon. The substrate 501 is doped with an impurity of the first conductivity type. For example, the impurity is boron. Although not shown in FIG. 7, an active region 548 is formed on the substrate 501 using a normal LOCOS or trench method. The active region 548 is extended to adjacent cells in the vertical direction. Although not shown in FIG. 17, a floating gate dielectric 514 is formed on the substrate. The floating gate dielectric 514 is preferably made of silicon oxide formed by thermally oxidizing the substrate 501 or silicon oxynitride formed by a CVD (chemical vapor deposition) method. After the floating gate layer 510 is formed on the floating gate dielectric film 514, patterning is performed by a photo / etching method to extend to adjacent cells in the vertical direction. The floating gate layer 510 is preferably composed of doped polycrystalline silicon or polycide. Although not shown in FIG. 17, an interpoly dielectric film 516 is formed on the floating gate layer 510. The interpoly dielectric film 516 is preferably composed of a silicon oxide film or ONO layer formed by a CVD method. The floating gate dielectric film 514, the floating gate layer 510, and the interpoly dielectric film 516 constitute a charge storage layer. A control gate layer 512 is formed on the interpoly dielectric film 516. The control gate layer 512 is preferably composed of doped polycrystalline silicon or polycide.
[0027]
Referring to FIGS. 8 and 18, a removable layer is formed on the control gate layer 512. The removable layer is preferably composed of silicon nitride. The removable layer is patterned by a photo / etching method to form a removable pattern 524 on the control gate layer 512. The removable pattern 524 is spaced a predetermined distance from other removable patterns. This spacing is extended to adjacent cells in the lateral direction. An impurity such as arsenic or phosphorus can be implanted into the surface region of the substrate 501 using the removable pattern 524 as an ion implantation mask. Ion implantation reduces the boron concentration in the surface region and increases the programming efficiency in the channel region during the programming operation. Ion implantation is performed through the floating gate dielectric 514, the floating gate layer 510, the interpoly dielectric 516 and the control gate layer 512. Impurities such as arsenic or phosphorus can be implanted into the control gate layer 512 to increase the conductivity of the control gate layer 512. Also at this time, the removable pattern 524 is used as an ion implantation mask.
[0028]
Referring to FIGS. 9 and 19, a gate mask layer 526 is formed on the resultant structure. The gate mask layer 526 is preferably formed of silicon oxide having a predetermined thickness.
[0029]
Referring to FIGS. 10 and 20, the gate mask layer 526 is anisotropically etched to form a spacer-shaped gate mask 526 ′ on the control gate layer 512 and the sidewall of the removable pattern 524. The gate mask 526 ′ is extended to adjacent cells in the lateral direction. Subsequently, the floating gate dielectric film 514, the floating gate layer 510, the interpoly dielectric film 516, and the control gate layer 512 are etched. At this time, using the gate mask 526 ′ and the removable pattern 524 as an etching mask, the substrate 501 is exposed to form a source contact 550. Although not shown in FIG. 20, arsenic ions are implanted into the substrate 501 to form the source 502. At this time, the gate mask 526 ′ and the removable pattern 524 are used as an ion implantation mask. It is also possible to activate the impurities of the source 502 by performing a heat treatment.
[0030]
Referring to FIGS. 11 and 21, a source-side spacer layer is formed on the result. The source side spacer layer is preferably made of silicon oxide. The source side spacer layer is anisotropically etched to form the source side spacer 528 on the sidewalls of the floating gate dielectric film 514, the floating gate layer 510, the interpoly dielectric film 516 and the control gate layer 512. The source-side spacer 528 extends to adjacent cells in the lateral direction.
[0031]
Referring to FIGS. 12 and 22, a source electrode layer is formed on the resultant to fill the source contact 550. The source electrode layer is preferably composed of tungsten or doped polycrystalline silicon. The source electrode layer is polished by an etch back or CMP method, and the source electrode 530 is formed inside the source contact 550. The source electrode 530 is extended to adjacent cells in the lateral direction.
[0032]
Referring to FIGS. 13 and 23, the removable pattern 524 is removed using dry etching or wet etching.
[0033]
Referring to FIGS. 14 and 24, the floating gate dielectric layer 514, the floating gate layer 510, the interpoly dielectric layer 516, and the control gate layer 512 are etched again. At this time, using the gate mask 526 ′ and the source electrode 530 as an etching mask, a charge storage region having a floating gate 510 ′ and a control gate 512 ′ are formed, and a part of the substrate 510 is exposed. At this time, the source electrode 530 is also partially etched to reduce the height. The floating gate 510 ′ and the control gate 512 ′ are extended to adjacent cells in the lateral direction. Subsequently, a select gate dielectric film 532 is formed on the result. The select gate dielectric film is preferably a CVD silicon oxide film. Prior to forming the select gate dielectric 532, a thin thermal oxide film may be formed on the exposed substrate.
[0034]
Referring to FIGS. 15 and 25, a select gate layer is formed on the resultant structure. The select gate layer is preferably composed of doped polycrystalline silicon. The selection gate layer is anisotropically etched to form spacer-shaped selection gates 506 on the sidewalls of the floating gate 510 ′ and the control gate 512 ′. This selection gate 506 is extended to adjacent cells in the lateral direction. Subsequently, although not shown in FIG. 25, phosphorus is ion-implanted to form an LDD region 534 in the substrate 501, and boron is ion-implanted to form a HALO region 536 below the LDD region 534. At this time, the selection gate 506 is used as an ion implantation mask.
[0035]
Referring to FIGS. 16 and 26, an LDD spacer layer is formed on the resultant structure. The LDD spacer layer is preferably made of silicon oxide. The LDD spacer layer is anisotropically etched to form the LDD spacer 540 on the side wall of the selection gate 506. The LDD spacer 540 extends to adjacent cells in the lateral direction.
[0036]
Although not shown in FIG. 26, arsenic ions are implanted to form a high concentration region 538 in the substrate 501. The impurity concentration of the high concentration region 538 is sufficiently higher than the concentrations of the LDD region 534 and the HALO region 536. Therefore, as shown in the drawing, the high concentration region 538 is formed by canceling out part of the LDD region 534 and the HALO region 536. At this time, the LDD spacer 540 and the selection gate 506 are used as an ion implantation mask. The high concentration region 538, the LDD region 534, and the HALO region 536 constitute a drain.
[0037]
Subsequently, although not shown, a normal wiring process is performed. That is, an insulating film is formed on the resultant product. A bit line contact is formed by a photo / etching method to expose the drain, and a bit line metal composed of aluminum is formed on the resultant structure. The bit line metal is patterned by a photo / etching method to form a bit line electrode.
[0038]
27 to 36 are schematic cross-sectional views for explaining a manufacturing method of a flash memory cell according to the second embodiment of the present invention.
[0039]
Referring to FIG. 27, the substrate 801 is preferably made of single crystal silicon. The substrate 801 is doped with an impurity of the first conductivity type. For example, the impurity is boron. Although not shown, the active region is formed by the same method as in the first embodiment. A charge storage layer 820 is formed on the substrate 801. The charge storage layer 820 is preferably an ONO layer. The control gate layer 812 is formed by the same method as in the first embodiment. It is not necessary to pattern the ONO layer before forming the control gate layer 812.
[0040]
Referring to FIG. 28, a removable pattern 824 is formed by the same method as in the first embodiment. An impurity such as arsenic or phosphorus can be implanted into the surface region of the substrate 801 using the removable pattern 824 as an ion implantation mask. Ion implantation reduces the boron concentration in the surface region and increases the programming efficiency in the channel region during the programming operation. Ion implantation is performed through the charge storage layer 820 and the control gate layer 812. Impurities such as arsenic or phosphorus can be implanted into the control gate layer 812 to increase the conductivity of the control gate layer 812. Also at this time, the removable pattern 824 is used as an ion implantation mask.
[0041]
Referring to FIG. 29, the gate mask layer 826 is formed by the same method as that of the first embodiment.
[0042]
Referring to FIG. 30, the gate mask layer 826 is anisotropically etched to form a spacer-shaped gate mask 826 ′ on the control gate layer 812 and on the sidewalls of the removable pattern 824. The gate mask 826 ′ is extended to adjacent cells in the lateral direction. Subsequently, the charge storage layer 820 and the control gate layer 812 are etched. At this time, the substrate 801 is exposed and the source contact 850 is formed using the gate mask 826 ′ and the removable pattern 824 as an etching mask. The source 802 is formed by the same method as in the first embodiment. A heat treatment can be performed to activate the impurities in the source 802.
[0043]
Referring to FIG. 31, source-side spacers 828 are formed on the sidewalls of the charge storage layer 820 and the control gate layer 812 by the same method as in the first embodiment.
[0044]
Referring to FIG. 32, the source electrode 830 is formed in the source contact 850 by the same method as in the first embodiment.
[0045]
Referring to FIG. 33, the removable pattern 824 is removed using a wet etching method or a dry etching method.
[0046]
Referring to FIG. 34, the charge storage layer 820 and the control gate layer 812 are etched again. At this time, the charge storage region and the control gate 812 ′ are formed using the gate mask 826 ′ and the source electrode 830 as an etching mask, and a part of the substrate 810 is exposed. At this time, the source electrode 830 is also partially etched to reduce the height. The charge storage region and the control gate 812 ′ are extended to adjacent cells in the lateral direction. Subsequently, a select gate dielectric film 832 is formed on the result. The select gate dielectric 832 is preferably a CVD silicon oxide film. A thin thermal oxide film can also be formed on the exposed substrate before the select gate dielectric 832 is formed.
[0047]
Referring to FIG. 35, a spacer-shaped selection gate 806 is formed on the sidewalls of the charge storage layer 820 and the control gate 812 ′ by the same method as in the first embodiment. Subsequently, the LDD region 834 and the HALO region 836 are formed by the same method as in the first embodiment.
[0048]
Referring to FIG. 36, an LDD spacer 840 is formed on the side wall of the selection gate 806 by the same method as in the first embodiment. A high concentration region 838 is formed on the substrate 801 by the same method as in the first embodiment. The high concentration region 838, the LDD region 834, and the HALO region 836 constitute a drain.
[0049]
Subsequently, a normal wiring process is performed by the same method as in the first embodiment.
[0050]
In the first and second embodiments of the present invention, when the control gate layer and the charge storage layer are patterned, the spacer-shaped gate mask protects the control gate layer and the charge storage layer as an etching mask. Such a patterning method can also be applied to a method for manufacturing a nonvolatile memory cell having no select gate. That is, the selection gate forming step can be omitted after FIG. 14 of the first embodiment or FIG. 34 of the second embodiment. Subsequently, by performing ion implantation using the gate mask and the source electrode as a mask, a drain is formed in the substrate adjacent to the charge storage region. Thereafter, a normal wiring process can be performed to manufacture a nonvolatile memory cell having no selection gate.
[0051]
【The invention's effect】
In the present invention, the spacer forming method is used several times. As described in the embodiment, a general spacer forming method includes depositing a film on a structure having a step and anisotropically etching the film. The final width of the formed spacer is determined by the thickness of the deposited film. In other words, the greater the thickness of the film, the greater the width of the spacer. Therefore, if the thickness of the film is sufficiently reduced, the width of the spacer can be reduced below the photographic process limit. As a result, the size of the cell of the present invention manufactured using the spacer formation method (self-alignment) can be minimized.
[0052]
According to the second embodiment of the present invention, it is not necessary to pattern the ONO layer as the charge storage layer before the control gate layer forming step of FIG. On the other hand, in the first embodiment, the floating gate layer must be patterned before the interpoly dielectric film forming step and the control gate layer forming step shown in FIGS. Accordingly, the second embodiment of the present invention has a simpler process than the first embodiment. The reason that the ONO layer does not need to be patterned is that the trapped charge does not move from one cell to another because the ONO layer is a non-conductive material.
[0053]
Furthermore, according to the present invention, by having the selection gate, low power consumption can be achieved during the program operation.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view illustrating a stack gate cell of a flash memory device according to the prior art.
FIG. 2 is a schematic cross-sectional view for explaining a source side injection cell of a flash memory device according to the prior art.
FIG. 3 is a schematic cross-sectional view illustrating a MONOS cell of a flash memory device according to the prior art.
FIG. 4 is a circuit diagram for explaining an arrangement of flash memory cells according to the first and second embodiments of the present invention;
FIG. 5 is a schematic plan view illustrating a flash memory cell according to a first embodiment of the present invention.
FIG. 6 is a schematic cross-sectional view for explaining a flash memory cell according to a first embodiment of the present invention.
FIG. 7 is a schematic cross-sectional view for explaining the manufacturing method of the flash memory cell according to the first embodiment of the present invention.
FIG. 8 is a schematic cross-sectional view for explaining the manufacturing method of the flash memory cell according to the first embodiment of the present invention.
FIG. 9 is a schematic cross-sectional view for explaining the manufacturing method of the flash memory cell according to the first embodiment of the present invention.
FIG. 10 is a schematic cross-sectional view for explaining the manufacturing method of the flash memory cell according to the first embodiment of the present invention.
FIG. 11 is a schematic cross-sectional view for explaining the manufacturing method of the flash memory cell according to the first embodiment of the present invention.
FIG. 12 is a schematic cross-sectional view for explaining the manufacturing method of the flash memory cell according to the first embodiment of the present invention.
FIG. 13 is a schematic cross-sectional view for explaining the manufacturing method of the flash memory cell according to the first embodiment of the present invention.
FIG. 14 is a schematic cross-sectional view for explaining the manufacturing method of the flash memory cell according to the first embodiment of the present invention.
FIG. 15 is a schematic cross-sectional view for explaining the manufacturing method of the flash memory cell according to the first embodiment of the present invention.
FIG. 16 is a schematic cross-sectional view for explaining the manufacturing method of the flash memory cell according to the first embodiment of the present invention.
FIG. 17 is a schematic plan view illustrating the method for manufacturing the flash memory cell according to the first embodiment of the invention.
FIG. 18 is a schematic plan view illustrating the method for manufacturing the flash memory cell according to the first embodiment of the invention.
FIG. 19 is a schematic plan view illustrating the method for manufacturing the flash memory cell according to the first embodiment of the invention.
FIG. 20 is a schematic plan view illustrating the method for manufacturing the flash memory cell according to the first embodiment of the invention.
FIG. 21 is a schematic plan view illustrating the method for manufacturing the flash memory cell according to the first embodiment of the invention.
FIG. 22 is a schematic plan view illustrating the method for manufacturing the flash memory cell according to the first embodiment of the present invention.
FIG. 23 is a schematic plan view illustrating the method for manufacturing the flash memory cell according to the first embodiment of the invention.
FIG. 24 is a schematic plan view illustrating the method for manufacturing the flash memory cell according to the first embodiment of the invention.
FIG. 25 is a schematic plan view illustrating the method for manufacturing the flash memory cell according to the first embodiment of the invention.
FIG. 26 is a schematic plan view illustrating the method for manufacturing the flash memory cell according to the first embodiment of the invention.
FIG. 27 is a schematic cross-sectional view for explaining a manufacturing method of a flash memory cell according to a second embodiment of the present invention.
FIG. 28 is a schematic cross-sectional view for explaining a manufacturing method of a flash memory cell according to a second embodiment of the present invention.
FIG. 29 is a schematic cross-sectional view for explaining a manufacturing method of a flash memory cell according to a second embodiment of the present invention.
FIG. 30 is a schematic cross-sectional view for explaining a manufacturing method of a flash memory cell according to a second embodiment of the present invention.
FIG. 31 is a schematic cross-sectional view for illustrating a manufacturing method of a flash memory cell according to a second embodiment of the present invention.
FIG. 32 is a schematic cross-sectional view for illustrating a manufacturing method of a flash memory cell according to a second embodiment of the present invention.
FIG. 33 is a schematic cross-sectional view for explaining a manufacturing method of a flash memory cell according to a second embodiment of the present invention.
FIG. 34 is a schematic cross-sectional view for explaining a manufacturing method of a flash memory cell according to a second embodiment of the present invention.
FIG. 35 is a schematic cross-sectional view for illustrating a manufacturing method of a flash memory cell according to a second embodiment of the present invention.
FIG. 36 is a schematic cross-sectional view for illustrating a manufacturing method of a flash memory cell according to a second embodiment of the present invention.
[Explanation of symbols]
501 and 801 substrates
502,802 source
506, 806 selection gate
510 Floating gate layer
510 'floating gate
512, 812 Control gate layer
512 ', 812' control gate
514 Floating gate dielectric film
516 Interpoly dielectric film
820 Charge storage layer
524,824 removable patterns
526,826 Gate mask layer
526 ', 826' gate mask
528,828 Source side spacer
530,830 Source electrode
532,832 Select gate dielectric film
534,834 LDD region
536,836 HALO region
538,838 High concentration region
540,840 LDD spacer
542 Insulating film
544 bit line electrode
546 bit line contact
548 Active region
BL bit line
CS common source line
WL word line
SL selection line

Claims (21)

A substrate ,
A charge storage region stacked on the substrate;
A control gate stacked on the charge storage region;
A sidewall-shaped gate mask laminated on the control gate ;
A select gate formed on an upper portion of the substrate and a side wall of the charge storage region;
A conductive region formed in the substrate adjacent to another side wall of the charge storage region;
The charge storage region, the control gate, the gate mask and the selection gate constitute a first unit cell,
The first unit cell includes an insulating spacer on a side wall of the selection gate . The nonvolatile semiconductor memory device according to claim 1 , further comprising a second unit cell that maintains a symmetric relationship with the first unit cell and shares the conductive region. A drain formed in the substrate adjacent to the select gate on the opposite side of the conductive region;
The nonvolatile semiconductor memory device according to claim 1 , further comprising a bit line electrode electrically connected to the drain. The nonvolatile semiconductor memory device according to claim 2 , further comprising a source electrode formed on the conductive region, wherein the source electrode is electrically insulated from the control gate by a source side spacer. The nonvolatile semiconductor memory device according to claim 1 , wherein the selection gate has a sidewall shape . The charge storage region is
A floating gate dielectric formed on the substrate;
A floating gate formed on the floating gate dielectric film;
2. The non-volatile semiconductor memory device according to claim 1, further comprising an interpoly dielectric film formed on the floating gate.   The nonvolatile semiconductor memory device according to claim 1, wherein the charge storage region includes an ONO layer. A substrate having a source and a drain;
A channel formed between the source and the drain;
A charge storage region formed on the channel;
A control gate formed on the charge storage region;
A select gate formed between the charge storage region and the drain;
Said charge storage region, said channel, said source and said drain, the control gate and the select gate constitutes the first unit cell,
A non-volatile semiconductor memory device comprising an insulating spacer formed on a side wall of the selection gate . The non-volatile device according to claim 8 , further comprising a second unit cell that maintains a symmetric relationship with respect to the first unit cell, wherein the first unit cell and the second unit cell share the source. Semiconductor memory device. 9. The nonvolatile semiconductor memory device according to claim 8 , wherein the selection gate has a sidewall shape . 9. The nonvolatile semiconductor memory device according to claim 8 , further comprising a sidewall-shaped gate mask formed on the control gate. A bit line electrode connected to the drain;
The nonvolatile semiconductor memory device according to claim 8 , further comprising a source electrode formed on the source and electrically insulated from the control gate by a source-side spacer. The charge storage region is
A floating gate dielectric formed on the substrate;
A floating gate formed on the floating gate dielectric film;
9. The nonvolatile semiconductor memory device according to claim 8 , further comprising an interpoly dielectric film formed on the floating gate. The nonvolatile semiconductor memory device of claim 8 , wherein the charge storage region includes an ONO layer. Forming a charge storage layer on the substrate;
Forming a control gate layer on the charge storage layer;
Forming a mask pattern on the control gate layer;
Forming a gate mask layer on the control gate layer and the mask pattern;
Removing a part of the gate mask layer and forming a sidewall-shaped gate mask on the sidewall of the mask pattern;
The charge storage layer and the control gate layer are etched using the gate mask and the mask pattern as an etching mask, and a part of the charge storage layer and the control gate layer is formed below the gate mask and the mask pattern. Leaving the stage,
Removing the mask pattern;
Nonvolatile said gate mask as an etching mask, by etching the control gate layer and the charge storage layer left, characterized in that it comprises a step of forming a control gate and a charge storage region below the gate mask For manufacturing a conductive semiconductor memory device Forming a source in the substrate adjacent to a sidewall of the control gate;
Forming source-side spacers on sidewalls of the control gate and the charge storage region;
The non-volatile semiconductor memory device according to claim 15 , further comprising: forming a source electrode electrically insulated from the control gate and the charge storage region on the source by the source side spacer. Manufacturing method. 16. The method of claim 15 , further comprising forming a selection gate on a side wall of the charge storage region. The method of claim 17 , wherein the selection gate has a sidewall shape . Forming an LDD region on the substrate using the selection gate as an ion implantation mask;
The method of claim 17 , further comprising: forming an insulating spacer on a side wall of the selection gate. Forming the charge storage layer comprises:
Forming a floating gate dielectric on the substrate;
Forming a floating gate layer on the floating gate dielectric layer;
The method of claim 15 , further comprising: forming an interpoly dielectric film on the floating gate layer. 16. The method of manufacturing a nonvolatile semiconductor memory device according to claim 15 , wherein the charge storage layer is an ONO layer.

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