JP2912120B2 - Nonvolatile semiconductor memory device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device used for a flash memory or the like and a method of manufacturing the same.

[0002]

2. Description of the Related Art As an electrically writable and removable nonvolatile semiconductor memory device, a flash memory which is advantageous in terms of high integration is known. One memory cell of such a nonvolatile semiconductor memory device generally includes one memory transistor including a floating gate and a control gate, which leaks an overerased current, and as a result, the control is not performed. There is a problem that it is difficult.

In order to solve the above-mentioned problem, there is a device in which a select transistor is connected in series to a control gate of a memory transistor (refer to Japanese Patent Laid-Open No. 2-5470).
No.). That is, as shown in FIG.
Floating gates FG ₁₁ and FG _{21 made} of a first conductive layer (for example, a polysilicon layer, hereinafter the same) and word lines WL ₁ and WL ₂ made of a _second conductive layer are formed thereon, and these are masked. The impurity is implanted by a self-alignment technique to form the common source region SC and the drain regions DR ₁₁ and DR ₂₁ in the substrate 1, and further, the bit line BL ₁ made of the third conductive layer is formed. In this case, the word line WL ₁ (WL
₂ ), the floating gate FG ₁₁ (FG ₂₁ ) and the drain region DR ₁₁ (DR ₂₁ )
₁₁ (MT ₂₁ ), and the word line WL ₁ (WL ₂ ) as the select gate and the source region SC form the select transistor ST ₁₁ (ST ₂₁ ). Therefore, the equivalent circuit of FIG. 8 is shown in FIG. It becomes like.

In order to write data into the memory transistor MT ₁₁ shown in FIG. 8, the bit line BL _1, that is, the drain region DR
₁₁ generates a hot carrier in the drain region by applying a high voltage to the floating gate FG.
Inject into ₁₁ . On the other hand, the erasing of the memory transistor MT _11, the floating gate FG by Fowler-Nordheim tunneling in a state where the word line WL ₁ and the ground potential by applying a high voltage to the drain region DR ₁₁ clogging the bit lines BL _{1 11} draw electrons to the drain region DR ₁₁ from. In this case, even when the memory transistor MT ₁₁ is regularly on too unplug the electron, select the transistor ST ₁₁ is present, there is no possibility that the drain region DR ₁₁ unnecessarily current leakage to the source region SC.
Further, to perform reading of the memory transistors MT _11, while the ground potential source region SC, the word line WL ₁
To apply a voltage in the, application of a voltage which is also the drain region DR ₁₁ clogging the bit line BL _1. As a result,
Source - it can confirm the data of the memory transistor MT ₁₁ depending on whether or not current flows between the drain.

[0005] However, in the nonvolatile semiconductor memory device of FIG. 8, the characteristics of the memory transistor and the select transistor vary. That is, ideally, the dimensions of the memory transistor and the select transistor adjacent to each other are as shown in FIG. 10A, but in reality, as shown in FIG. 10B, the word lines WL ₀ ,
In forming the WL _1, the floating gate FG _01,
A misalignment d occurs with respect to the FG ₁₁ . As a result,
Assuming that the dimensions of the memory transistor and the select transistor in FIG. 10A are DD and D, the dimensions of the adjacent memory transistors are DD + d and DD−d, and the dimensions of the adjacent select transistor are D and D.
+ D and D−d. Eventually, the dimensional deviation of the transistor between adjacent cells appears as a difference in the respective operating characteristics of writing, erasing, and reading, and therefore, the high integration and high speed of the nonvolatile semiconductor memory device shown in FIG. 8 cannot be achieved. become.

There is a nonvolatile semiconductor memory device in which a control gate of a memory transistor and a select gate of a select transistor are separately formed in order to prevent the dimensional deviation of the transistor due to the above-described alignment (see K. Naruke et al.). , "A NEWFLASH-ERASE EEPROM CELL
WITH A SIDEWALL SELECT-GATE ON ITS SOURCE SIDE ", I
EEE IEDM 1989, PP.603-606). That is, as shown in FIG. 11, the memory transistor MT ₁₁ (MT ₂₁ ) includes a floating gate FG ₁₁ (FG ₂₁ ), a word line WL ₁ (WL ₂ ) as a control gate, and a drain region D
R ₁₁ (DR ₂₁ ) and the select transistor ST
₁₁ (ST ₂₁ ) includes the select gate S ₁ (S ₂ ) and the common source area SC. Thereby, different voltages can be applied to the control gate of the memory transistor and the select gate of the select transistor. Therefore, the writing by the hot carrier effect in the device of FIG. 8 is injection of electrons from the drain region side to the floating gate, but in the device of FIG. 11, electrons can be injected from the source region side to the floating gate. At this time, the voltage applied to the drain region side can be reduced. In other words, when performing writing by the normal hot carrier effect, writing can be realized by setting the gate voltage of the select transistor connected to the source region side of the memory transistor low. As a result, the power supply voltage of the device can be reduced, and the device can be driven by a battery.

Next, a method of manufacturing the nonvolatile semiconductor memory device shown in FIG. 11 will be described with reference to FIGS.

First, a tunnel insulating layer 2 is formed on a semiconductor substrate 1, and a floating gate 3a, an insulating layer 4, a control gate 6a, and a side wall insulating layer 15 are formed.
Using the photoresist layer 16 as a mask, a diffusion layer 17 is formed in the drain region ( FIG. 12A ). Next, a polysilicon layer 10 containing phosphorus (P) is formed as a polysilicon layer by chemical vapor deposition (hereinafter referred to as CVD) at a temperature of 2,000 to 10 Å.
000 ° ( FIG. 12B ). Next, the entire surface is exposed to anisotropic etching, and the select layer 10a is formed by leaving the polysilicon layer 10a only on the side walls of the floating gate 3a and the control gate 6a via the side wall insulating layer 15 ( FIG. 12C )). Next, a diffusion layer 12 serving as a drain region and a source region is formed by using impurities of the opposite conductivity type to the semiconductor substrate 1 (FIG. 13D). Next, a contact hole is formed in the interlayer insulating film 13 (FIG. 13E). Next, a wiring 19 as a bit line is formed and connected to the drain region (FIG. 1).
3 (F)).

[0009]

However, FIG.
In the conventional nonvolatile semiconductor memory device shown in FIGS. 1, 12 and 13, when forming the select gates S ₁ and S ₂ (10a), anisotropic etching of the polysilicon layer 10 is used. Memory transistors MT ₁₁ and M
Select gate 10a is formed on both sides of the T _21. That is, since unnecessary select gates are also formed, there is a problem that high integration cannot be achieved. Moreover, in order to keep the unnecessary select gate transistor on at all times, in other words, the memory transistor MT ₁₁ ,
In order to secure the drain region of the MT ₂₁ , in addition to the diffusion layer 12 formed together with the source region, a diffusion layer 17 must be formed in advance, and the diffusion layer 17 is formed of a polysilicon self-alignment. Since it is formed without using a technique, there is a problem that the manufacturing cost is increased.

Accordingly, it is an object of the present invention to provide a nonvolatile semiconductor memory device which can achieve high integration and has low manufacturing cost. Another object is to provide a method for manufacturing the above-mentioned nonvolatile semiconductor memory device.

[0011]

According to a first aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising a select gate formed only on one side of a memory transistor including a floating gate and a control gate. Construct a select transistor.

As a method of manufacturing the above-described nonvolatile semiconductor memory device, side wall insulating layers are formed on both sides of each memory transistor by anisotropic etching.
A conductive layer as a select gate is formed on the entire surface, and the conductive layer is left only on one side of each memory transistor by isotropic etching.

[0013]

According to the above-described means, there is no unnecessary select gate, and therefore, the step of invalidating the unnecessary select gate is unnecessary.

[0014]

FIG. 1 is a sectional view and a plan view showing a first embodiment of a nonvolatile semiconductor memory device according to the present invention, and FIG. 2 is an equivalent circuit diagram thereof. Unlike the case of FIG. 11, the conductive layers as the select gates S ₁ and S ₂ are formed only on one side of the memory transistor MT ₁₁ (MT ₂₁ ). As a result, the drain region DR ₁₁ (DR ₂₁ ) is not shown. 11 is smaller. 7 is a select gate S
₁ , a mask insulating layer for insulating the conductive layer from the word line WL ₁ (WL ₂ ) as a control gate when forming S ₂ .

Next, a method of manufacturing the nonvolatile semiconductor memory device of FIG. 1 will be described with reference to FIGS.

First, referring to FIG. 3A, a tunnel insulating layer 2 is formed on a semiconductor substrate, for example, a P ⁻ type single crystal silicon substrate 1. This tunnel insulating layer 2 is obtained by thermally oxidizing the semiconductor substrate 1 at 700 to 900 ° C., and has a thickness of 50 to 200 °. Next, a phosphorus (P) -containing polysilicon layer 3 as a floating gate is formed by CVD.
It is formed to a thickness of 1000 to 3000 mm by the method. Next, for example, an insulating layer 4 composed of an oxide film ( SiO ₂ ) , a nitride film ( Si ₃ N ₄ ) , and an oxide film ( SiO ₂ ) is formed, and the photoresist layer 5 is used as a mask to become a source region. The insulating layer 4 in the region to be removed is removed. The removal of the insulating layer 4 is performed by using a floating gate 3a and a control gate 6a which will be described later.
Is to be selectively and continuously etched. afterwards,
The photoresist layer 5 is removed.

Next, referring to FIG. 3B, a phosphorus (P) -containing polysilicon layer 6 as a control gate is provided.
The thickness was 1000~3000Å formed by CVD, further for example, a thickness of 500~3000Å forming a mask insulating layer 7 made of oxide film (SiO ₂₎ by CVD.

Next, referring to FIG. 3C, using the photoresist layer 8 as a mask, the mask insulating layer 7, the polysilicon layer 6, the insulating layer 4, and the polysilicon layer 3 are sequentially etched and removed to obtain a memory transistor. MT ₀₁ , MT ₁₁ , MT
_21, to form a floating gate 3a and the control gate 6a in the region of the MT _31. At this time, the floating gate 3a and the control gate 6a are also formed in the source region SC, but in this case, as described above, there is no insulating layer between the floating gate 3a and the control gate 6a. Note that the distance between the memory transistor MT ₁₁ (MT ₂₁ ) and the source region SC is set to be the channel length of a select transistor described later.

Next, referring to FIG. 4D, in order to form a sidewall insulating layer, an insulating layer 9 made of a nitride film ( Si ₃ N ₄ ) having a thickness of 500 to 2000 is formed by, for example, a CVD method.
Å Form.

Next, referring to FIG. 4E, the entire surface of the insulating layer 9 is left only on the side wall by anisotropic etching.
The side wall insulating layer 9a is formed. Next, a sidewall polysilicon layer 10 containing phosphorus (P) is formed by a CVD method. In this case, the thickness of sidewall polysilicon layer 10 is larger than 1/2 of the channel length of the select transistor, for example, 200
0 to 5000 °. Next, referring to FIG. 4F, the entire surface is removed by isotropic etching, thereby forming the select gate 10a while leaving the sidewall polysilicon layer 10 only on the sidewall. In this case, the floating gate 3a and the control gate 6a are not etched because the mask insulating layer 7 and the side wall insulating layer 9a function as a mask for isotropic etching.

Next, referring to FIG. 5G, using the photoresist layer 11 as a mask, the mask insulating layer ( SiO ₂ ) 7 on the source region SC is removed by etching with a hydrofluoric acid solution. Upper control gate 6
a and the floating gate 3a are removed by etching with a mixed solution of hydrofluoric acid and nitric acid. In this case, the side wall insulating layer 9a
Is a mask for hydrofluoric acid and a mixture of hydrofluoric acid and nitric acid. Since the insulating layer 4 contains a nitride film as described above, the control gate 6a and the floating gate
If the insulating layer 4 is present between the gate insulating layer 4 and the gate 3a, the sidewall insulating layer 9a does not serve as a mask when the insulating layer 4 is removed by etching. For this reason, in FIG. 3A, the portion of the insulating layer 4 is removed by etching in advance. Therefore, the insulating layer 4
This does not require such an etching removal step if no nitride film is contained. After that, the photoresist layer 11 is removed.

Next, referring to FIG. 5H, phosphorus (P) or arsenic (A _S ) is ion-implanted to form the diffusion layer 12.
To form These diffusion layers 12 serve as drain regions D
R ₁₁ and DR ₂₁ function as the source area SC.

Next, referring to FIG. 5I, the interlayer insulating layer 13 is formed of, for example, an oxide film ( SiO ₂ ) containing phosphorus (P) or boron (B) by a CVD method. Then, a contact hole for wiring layer of the photoresist layer 14 as the bit lines BL ₁ in FIG. 1 with respect to the diffusion layer 12 of the drain region as a mask.

[0024] In this manner, after removing the photoresist layer 14 in (I) in FIG. 5, when a wiring layer 19 as the bit line BL _1, the nonvolatile semiconductor memory device shown in FIG. 1 is obtained become.

FIG. 6 is a sectional view showing a second embodiment of the nonvolatile semiconductor memory device according to the present invention. 6, a sidewall polysilicon layer 18a is added to the components of FIG. Thereby, the resistance of the diffusion layer in the source region SC can be substantially reduced, and as a result, the width of the source region SC can be reduced, which contributes to high integration.

Next, a method of manufacturing the nonvolatile semiconductor memory device of FIG. 6 will be described with reference to FIG. First, (A), (B), (C) of FIG. 3, (D), (E),
After the respective steps of (F) and (G) of FIG. 5, (A) of FIG.
The process shown in FIG.

Referring to FIG. 7A, the tunnel insulating layer 2 is further etched away with hydrofluoric acid using the photoresist layer 11 as a mask. Next, referring to FIG. 7B, the polysilicon layer 18 containing phosphorus (P) is formed by CVD.
3000 to 6000 ° is formed by the method.

Next, referring to FIG. 7C, the polysilicon layer 18 is isotropically etched to leave the polysilicon layer 18 only on the source region SC.
A sidewall polysilicon layer 18a is formed. Thereafter, an interlayer insulating layer 13 using the photoresist layer 14 as a mask, the formation of the wiring layer 19 as a removal and the bit lines BL ₁ of the photoresist layer 14 is performed in the same manner as (I) in FIG.

Here, the channel length of the memory transistor is 1 μm, and the channel length of the select transistor is 1 μm.
m, the width of the source region is 1 μm, the size of the contact hole is 0.5 μm, and the distance between the contact hole and the memory transistor is 0.5 μm, the conventional length per memory cell in FIG. 25 μm,
The length per memory cell of the present invention in FIG.
It is 75 μm, which is as small as 15%, which is clearly advantageous in terms of high integration. Further, when the source region is formed as shown in FIG. 6 and the width of the source region is, for example, 0.5 μm, the length per memory cell in the present invention in FIG.
% Also becomes smaller.

In the above-described embodiment, the reason why phosphorus is contained in the polysilicon layer is to increase the conductivity of the polysilicon layer, and other impurities such as arsenic may be contained.

[0031]

As described above, according to the present invention, since there is no unnecessary select gate, high integration can be achieved, and the unnecessary select gate is invalidated (always on). Is unnecessary, so that the manufacturing cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view and a plan view showing a first embodiment of a nonvolatile semiconductor memory device according to the present invention.

FIG. 2 is an equivalent circuit diagram of the nonvolatile semiconductor memory device of FIG.

FIG. 3 is a sectional view illustrating the method of manufacturing the nonvolatile semiconductor memory device in FIG.

FIG. 4 is a sectional view illustrating the method of manufacturing the nonvolatile semiconductor memory device in FIG. 1;

FIG. 5 is a sectional view illustrating the method of manufacturing the nonvolatile semiconductor memory device in FIG.

FIG. 6 is a sectional view showing a second embodiment of the nonvolatile semiconductor memory device according to the present invention.

FIG. 7 is a sectional view illustrating the method of manufacturing the nonvolatile semiconductor memory device in FIG.

FIG. 8 is a sectional view showing a conventional nonvolatile semiconductor memory device.

FIG. 9 is an equivalent circuit diagram of the nonvolatile semiconductor memory device of FIG. 8;

FIG. 10 is a sectional view illustrating a problem of the nonvolatile semiconductor memory device of FIG. 8;

FIG. 11 is a sectional view showing another conventional nonvolatile semiconductor memory device.

FIG. 12 is a sectional view illustrating the method of manufacturing the nonvolatile semiconductor memory device in FIG.

13 is a cross-sectional view for explaining the method for manufacturing the nonvolatile semiconductor memory device in FIG.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate 2 tunnel insulating layer 3 a floating gate 4 insulating layer 6 a control gate 7 mask insulating layer 9 insulating layer 9 a sidewall insulating layer 10 polysilicon layer 10 a sidewall polysilicon layer 11 photoresist Layer 12 Diffusion layer 13 Interlayer insulation layer 14 Photoresist layer 15 Sidewall insulation layer 16 Photoresist layer 17 Diffusion layer 18 Polysilicon layer 18a Sidewall polysilicon layer 19 Wiring layer (bit line) MT ₀₁ , MT ₁₁ , MT ₂₁ , MT ₃₁ ... memory transistors S ₁ , S ₂ ... select transistors SC ... source regions DR ₁₁ , DR ₂₁ ... drain regions WL ₁ , WL ₂ ... word lines (control gates) BL ₁ ... bit lines

Claims (6)

(57) [Claims] To 1. A semiconductor substrate, a first insulating layer serving as a gate insulating layer, a first conductive layer serving as a floating gate, a second insulating layer, a second conductive layer serving as a control gate, first 及 Beauty Forming a third insulating layer sequentially; patterning the first conductive layer, the second insulating layer, the second conductive layer, and the third insulating layer to form the semiconductor;
First shape of the first electrode region of the substrate, the memory Trang
Forming a second shape portion to be a gate region of the transistor ; forming a fourth insulating layer on the side walls of the first and second shape portions; Forming a third conductive layer of a predetermined thickness on the surface; and isotropically etching the third conductive layer to form the first shape.
A select gate is provided only between the portion and the second shape portion.
Leaving the third conductive layer, and leaving only the first insulating layer in the first shape portion.
And the first electrode region of the semiconductor substrate and the second electrode region.
A diffusion layer in a second electrode region of the semiconductor substrate between the shape portions;
Forming a non-volatile semiconductor storage device. 2. A method according to claim 1, wherein the predetermined thickness of the third conductive layer is equal to the first thickness .
Not less than の of the distance between the shaped part and the second shaped part.
2. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein: 3. A first insulating layer on a semiconductor substrate, the first insulating layer being a gate insulating layer .
An insulating layer, a first conductive layer serving as a floating gate ,
Sequentially forming a second insulating layer 及 beauty, removing the second insulating layer over the first region, said first region said first conductive layer and the second of Absolute
A second conductive layer serving as a control gate on the edge layer, sequentially forming a third insulating layer 及 beauty, the first conductive layer in the first region, the second
Patterning the conductive layer and the third insulating layer to form the semiconductor layer;
A first shape portion on the first electrode region of the conductive substrate;
The first conductive layer, the second insulating layer in a region of
Patterning the second conductive layer and the third insulating layer
Second shape that Do a gate region of the memory transistor and
Forming a portion, forming a fourth insulating layer on the entire surface after the patterning , and performing anisotropic etching to apply the fourth insulating layer only to the side walls of the first and second shape portions. A step of forming a third conductive layer having a predetermined thickness on the entire surface after the fourth insulating layer is left; and a step of isotropically etching the third conductive layer to form the third insulating layer. Shape of 1
A select gate is provided only between the portion and the second shape portion.
Leaving the third conductive layer, and leaving only the first insulating layer in the first shape portion.
And the first electrode region of the semiconductor substrate and the second electrode region.
A diffusion layer in a second electrode region of the semiconductor substrate between the shape portions;
Forming a non-volatile semiconductor storage device. 4. The method according to claim 1, wherein the predetermined thickness of the third conductive layer is equal to the first thickness .
以上 or more of the distance between the shaped part and the second shaped part
4. The method for manufacturing a nonvolatile semiconductor memory device according to claim 3, wherein: 5. A method according to claim 1, wherein a first gate insulating layer is formed on the semiconductor substrate.
An insulating layer, a first conductive layer serving as a floating gate ,
Sequentially forming a second insulating layer 及 beauty, removing the second insulating layer over the first region, said first region said first conductive layer and the second of Absolute
A second conductive layer serving as a control gate on the edge layer, sequentially forming a third insulating layer 及 beauty, the first conductive layer in the first region, the second
Patterning the conductive layer and the third insulating layer to form the semiconductor layer;
A first shape portion on the first electrode region of the conductive substrate;
The first conductive layer, the second insulating layer in a region of
Patterning the second conductive layer and the third insulating layer
To form a gate region of a memory transistor
Forming a portion, forming a fourth insulating layer on the entire surface after the patterning , and performing anisotropic etching to apply the fourth insulating layer only to the side walls of the first and second shape portions. A step of forming a third conductive layer having a predetermined thickness on the entire surface after the fourth insulating layer is left; and a step of isotropically etching the third conductive layer to form the third insulating layer. Shape of 1
A select gate is provided only between the portion and the second shape portion.
Leaving the third conductive layer, and leaving only the first insulating layer in the first shape portion.
And the first electrode region of the semiconductor substrate and the second electrode region.
A diffusion layer in a second electrode region of the semiconductor substrate between the shape portions;
Forming, and after removing the first insulating layer in the first shape portion,
Forming a fourth conductive layer on the surface; and performing isotropic etching on the fourth conductive layer to form the first conductive layer.
Leaving the fourth conductive layer only in the shape portion.
Manufacturing of nonvolatile semiconductor memory device characterized by having
Method. 6. A semiconductor substrate, a first insulating layer serving as a gate insulating film, a first polysilicon layer serving as a floating gate, a step of sequentially forming a second insulating layer 及 beauty, the first region Removing the second insulating layer on the polysilicon layer in the first region and the second insulating layer .
The second polysilicon layer serving as a control gate on an insulating layer, a step of sequentially forming a third insulating layer 及 beauty, the first
The first polysilicon layer in the first region, the second polysilicon layer,
Patterning the polysilicon layer and the third insulating layer
And a first shape on a first electrode region of the semiconductor substrate
Part and the first polysilicon in a second region
A layer, the second insulating layer, the second polysilicon layer, and
Patterning the third insulating layer to form a memory transistor;
Forming a second shape portion to be a gate region of the gate, and forming a fourth insulating layer on the entire surface after the patterning and performing anisotropic etching to form the first and second shape portions. Leaving the fourth insulating layer on the side wall;
Forming a third polysilicon layer on the entire surface after the insulating layer is left, and isotropically etching the third polysilicon layer to form the third polysilicon layer.
Only between the first shape portion and the second shape portion,
The third step of the polysilicon layer Ru are left to be over preparative
If, while leaving only the front Symbol said first insulating layer of the first shape portion
And the first electrode region of the semiconductor substrate and the second electrode region.
A diffusion layer in a second electrode region of the semiconductor substrate between the shape portions;
Forming a non-volatile semiconductor storage device.