JP3392547B2 - Nonvolatile semiconductor memory device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a flash memory in which writing is performed by channel hot electrons and erasing is performed by substrate hot holes.

[0002]

2. Description of the Related Art IEEE EDL issued in August 1993
Discloses a flash memory configured as shown in FIGS. 12 and 13. 12 is a perspective view showing a schematic structure, and FIG. 13 is a cross-sectional structure diagram of the memory cell shown in FIG. 12 and 13, 10 is a p-type silicon substrate, 11 is a columnar structure (hereinafter referred to as a column), 12
Is a word line, 13 is a bit line, 14 is a gate oxide film, 1
5 is a floating gate, 16 is an insulating film, 17 is a control gate (corresponding to the word line 12 in FIG. 12),
Reference numeral 18 is an n ⁺ type source region, 19 is an n ⁺ type drain region, and 20 is an interlayer insulating film.

The pillar 11 is formed by etching the main surface of a p-type silicon substrate 10 by an anisotropic etching method such as RIE, and an n ⁺ -type source region is formed in the substrate 10 around the base of the pillar 11. 18, n ⁺ type drain regions 19 are arranged on the pillars 11, respectively. And
The substrate 10 between the source region 18 and the drain region 19,
That is, the side surfaces of the pillars 11 all function as channel regions.
A floating gate 15 is formed on the side wall of the pillar 11 via a gate oxide film 14, and a control gate 17 is formed around the floating gate 15 via an insulating film 16. The pillar 11 is an interlayer insulating film 2
The bit line 13 filled with 0 and formed on the interlayer insulating film 20 is in contact with the drain region 19.

The writing and erasing of data in the memory cell having the above-mentioned structure are carried out by setting as follows when the drain potential is Vd, the control gate potential is Vcg, and the source potential is Vs. That is, for writing data, for example, by setting Vd = 6V and Vcg = 12V, channel hot electrons generated in the channel region near the drain region 19 are injected into the floating gate 15 through the gate oxide film 14. To do. On the other hand, erasing is performed by the Fowler-Nordheim current of electrons from the floating gate 15 to the source region 18 by setting Vcg = -12V and Vs = 6V.

By the way, in the memory cell having the above structure, since the erasing is performed by the Fowler-Nordheim current, a thin oxide film (gate oxide film 14) having a uniform thickness is formed.
Is essential. However, since the substrate 10 (side wall portion of the pillar 11) around the source region 18 to be erased is formed by anisotropic etching, the surface flatness is poor and a stable thin oxide film having a uniform film thickness is formed. Hard to form. For this reason, the variation in the erase characteristic of each memory cell becomes large, and a memory cell that is in an over-erased state is likely to occur, and erroneous reading occurs when data is read from a memory cell in the same column as the over-erased memory cell. There is a problem.

When the Fowler-Nordheim current is used for erasing, a high electric field is applied to the tunnel oxide film (gate oxide film 14), so that the deterioration of the oxide film progresses rapidly. This tendency becomes more remarkable as the tunnel oxide film becomes thinner with the miniaturization, and there arises a problem that the charge accumulated in the floating gate 15 cannot be sufficiently retained.

[0007]

As described above, the conventional nonvolatile semiconductor memory device is over-erased because there is a large variation in erase characteristics among memory cells and it is easy for some memory cells to be over-erased. There is a problem that erroneous reading occurs when reading data from the memory cell in the same column as the memory cell.

Further, there is a problem that it becomes difficult to hold the charges accumulated in the floating gate due to the thinning of the gate oxide film accompanying the miniaturization. The present invention has been made in view of the above circumstances, and an object thereof is to provide a nonvolatile semiconductor memory device capable of obtaining uniform erase characteristics and preventing erroneous reading of data. Another object of the present invention is to provide a non-volatile semiconductor memory device capable of improving charge retention characteristics.

[0009]

A non-volatile semiconductor memory device according to a first aspect of the present invention has a memory cell having a floating gate formed on a semiconductor substrate with a gate oxide film interposed therebetween. writing and erasing of data to, as performed by channel hot electron injection and hot hole injection into the floating gate
Channel channel to the floating gate
The above-mentioned electron injection from near the drain region.
To the floating gate
A hot hole injection of is provided adjacent to the source region,
It has the same conductivity type as the source region and has a higher impurity concentration than the source region.
From the low impurity diffusion region through the gate oxide film
It is characterized by performing.

As described in claim 2, channel hot electron injection and hot hole injection to the floating gate are performed in a region between the drain region and the source region formed in the semiconductor substrate.

[0011]

[0012] The nonvolatile semiconductor memory device according to claim 3, and the bar which is formed on the main surface of the semiconductor substrate, a floating gate formed via a gate oxide film so as to surround the pillar, the floating gate A control gate formed around an insulating film, a source region formed in a surface region of the semiconductor substrate below the control gate, a drain region formed on the pillar, and a source region. A channel region formed in the pillar between the drain region and a direction perpendicular to the main surface of the semiconductor substrate, and formed in the floating gate and the semiconductor substrate below the channel region, the same as the source region. A memory cell having an impurity diffusion region of a conductivity type and having an impurity concentration lower than that of the source region.

As described in claim 4 , in writing data to the memory cell, channel hot electrons are injected into the floating gate from the channel region near the drain region through the gate oxide film. The data in the memory cell is erased by injecting hot holes from the impurity diffusion region into the floating gate through the gate oxide film.

[0014]

[0015]

[0016]

[0017]

According to the structure of claims 1 to 4 , since hot carriers are used for both writing and erasing, a thin tunnel oxide film becomes unnecessary as a gate oxide film.
Further, the hot carrier injection is less susceptible to fluctuations such as variations in the oxide film thickness as compared with the FN tunnel current, so that the erase characteristics of each memory cell can be made equal and the occurrence of overerase can be suppressed. Therefore, uniform erasing characteristics can be obtained and erroneous reading of data can be prevented. In addition, since a gate oxide film thicker than the tunnel oxide film can be used,
The deterioration of the gate oxide film can be reduced, and the charge retention characteristics can be improved.

[0018]

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1 and 2 respectively show a configuration of a memory cell in a nonvolatile semiconductor memory device according to a first embodiment of the present invention. FIG. 1 is a sectional view showing the configuration of the memory cell, and FIG. In the pattern plan view of the memory cell shown in FIG. 2, the cross section along the line AA ′ in FIG. 2 corresponds to FIG. 1. However, in order to simplify the drawing, FIG. 2 shows a pattern plane in which the interlayer insulating film and the bit line are omitted.

1 and 2, 21 is a p-type silicon substrate, 22 is a columnar structure (abbreviated as a column) formed by selectively removing the surface of the substrate 21 by anisotropic etching such as RIE. , 23 is an n ⁺ type source region, 24 is an n ⁺ type drain region, 25 is a channel region, and 26 is n.
^{A −} type impurity diffusion region, 27 is a gate oxide film, 28 is a floating gate, 29 is an insulating film, 30 is a control gate, 31 is an interlayer insulating film, and 32 is a bit line.

As shown in FIGS. 1 and 2, a drain region 24 is formed on the pillar 22, and an n ⁻ -type impurity diffusion region 26 is formed on the surface of the silicon substrate 21 including the base of the pillar 22. ing. The inside of the pillar 22 between the drain region 24 and the impurity diffusion region 26 functions as a channel region 25. A floating gate 28 is provided on the side wall of the pillar 22 so as to surround the pillar 22 via a gate oxide film 27, and a control gate 30 is provided so as to surround the floating gate 28 via an insulating film 29. Has been. Then, the source region 23 is arranged in the surface region of the substrate 21 below the control gate 30. The source region 23 is provided in the impurity diffusion region 26, and these regions 23 and 26 are electrically continuous regions.

Next, the manufacturing process of the memory cell shown in FIGS. 1 and 2 will be described with reference to FIGS. First, in order to form the pillars 22 on the main surface of the p-type silicon substrate 21, a resist is applied to the surface of the substrate 21 and patterned to form a resist mask 33 as shown in FIG.

Next, the surface of the substrate 21 is etched to a depth of 1.0 μm by anisotropic etching such as RIE, the resist mask 33 is removed, and the surface of the substrate 21 is heated to a thickness of 200 by thermal oxidation. An oxide film 34 having a thickness of about angstrom is formed. Then, as shown in FIG.
8 × 10 boron was obliquely provided to the main surface of the substrate 21.
Ion implantation is performed at about ¹² atoms / cm ² . Continuing,
Phosphorus was added to the main surface of the substrate 21 perpendicularly to 5 × 10 ¹³ a.
Ions are implanted at about toms / cm ² .

After removing the oxide film 34 with NH ₄ F, the surface of the substrate 21 is oxidized by thermal oxidation to form a gate oxide film 27 having a thickness of about 200 Å. After that, a polysilicon layer having a thickness of 1000 angstrom is deposited and formed on the entire surface, and then POCl ₃ is deposited in the polysilicon layer.
Introduce phosphorus by thermal diffusion. Then, as shown in FIG. 5, the floating gate 28 is formed by performing anisotropic etching to leave polysilicon on the side wall of the pillar 22.

An oxide film having a thickness of 100 Å, a silicon nitride film having a thickness of 150 Å, and an oxide film having a thickness of 70 Å are sequentially laminated by the CVD method to form an insulating film 28 having a three-layer structure. next,
As is ion-implanted into the entire surface at about 5 × 10 ¹⁵ atoms / cm ² to simultaneously form the source region 23 and the drain region 24. After that, a phosphorus-doped polysilicon layer having a thickness of 4000 angstroms is deposited and formed on the entire surface, and anisotropic etching is performed to leave this polysilicon layer on the side wall of the pillar 22, resulting in a structure shown in FIG. can get. The remaining polysilicon layer 30 functions as a control gate (word line).

After that, a CVD oxide film (interlayer insulating film 31)
By filling the recesses between the memory cells with each other and forming the wiring (bit line 32) made of Al, the memory cell as shown in FIG. 1 is completed.

In the memory cell shown in FIGS. 1 and 2, the source region 23 is arranged immediately below the control gate 30, and the n ^-- type impurity diffusion region 26 is arranged between the source regions 23. Further, as the gate oxide film 27, a thin tunnel oxide film is not used.

Writing and erasing data in the memory cells shown in FIGS. 1 and 2 are performed as follows. That is, the drain potential is Vd, the control gate 30 potential is Vcg, the source potential is Vs, and the substrate potential is Vsub.
Further, assuming that the channel potential is Vch, when writing, the channel region 2 near the drain region 24 is set by setting Vd = 6V and Vcg = 12V as in the conventional case.
Channel hot electrons are generated at 5 and injected into the floating gate 28 through the gate oxide film 27. On the other hand, for erasing, for example, Vs = Vsub = 5V, Vc
By setting h = 0 V and Vcg = −5 V, substrate hot holes are injected from the n ⁻ type impurity diffusion region 26 to the floating gate 28 through the gate oxide film 27.

According to the above structure, since hot carriers are used for both writing and erasing, a thin tunnel oxide film is unnecessary. Also, hot carrier injection is
Compared to the FN tunnel current, it is less susceptible to fluctuations such as variations in oxide film thickness, so that the erase characteristics of each memory cell can be made equal, and the occurrence of overerase can be suppressed. Therefore, uniform erasing characteristics can be obtained and erroneous reading of data can be prevented. Further, since an oxide film thicker than the tunnel oxide film can be used as the gate oxide film 27, the oxide film is less deteriorated when an electric field is applied, and the charge retention characteristic can be improved.

In the first embodiment, the source region 2
3 is provided in the impurity diffusion region 26, the impurity diffusion region 26 is formed to be shallower than the source region 23.
An impurity diffusion region 26 may be provided between the three regions in contact with these regions to form an electrically continuous region.

FIG. 7 is for explaining a nonvolatile semiconductor memory device according to the second embodiment of the present invention.
FIG. 3 is a cross-sectional configuration diagram showing two adjacent memory cell parts by extraction. 7, the same components as those in FIGS. 1 to 6 are designated by the same reference numerals. In the second embodiment, the word line (control gate 3
0) is shared. This enables further miniaturization as compared with the first embodiment described above. In order to adopt this configuration, it is necessary to have selectivity with the adjacent bit sharing the word line, and as one means therefor, as shown in FIG. 8, it is oblique to the matrix arrangement of the memory cells. The bit line 32 is arranged, and the contact 35 between the bit line 32 and the drain region 24 is located at a position apart from the contact of any memory cell by one adjacent contact in the row direction and two in the column direction. It is possible to place it in

FIG. 9 is a sectional view of a memory cell in a nonvolatile semiconductor memory device according to the third embodiment of the present invention. This memory cell corresponds to the memory cell structure shown in FIGS. 1 and 2, in which the n ⁻ type impurity diffusion region 26 is separated below the channel region 25.

In the case of the configuration shown in FIG. 9, when erasing, V
Sub = Vch = 0 V, and n ⁻ type impurity diffusion region 26
The holes generated in a thermal equilibrium state are injected into the floating gate 28 through the gate oxide film 26.

With this configuration, the channel region 25
Since the potential is set to the potential of the substrate 21 and the floating state does not occur, voltage control becomes easy. 10 and 11 are each for explaining a nonvolatile semiconductor memory device according to the fourth embodiment of the present invention. FIG. 10 is a plan view of the pattern, and FIG. 11 is taken along the line BB ′ of FIG. FIG. In FIG. 10, the interlayer insulating film and the bit line are omitted in order to simplify the drawing.

The memory cell shown in FIGS. 10 and 11 has one
A plurality of memory cells are formed on one pillar 22. The other basic structure is the same as the structure shown in FIGS. 1 and 2, and therefore, the same parts are denoted by the same reference numerals and detailed description thereof will be omitted.

According to this structure, the floating gates 28 of a plurality of memory cells are formed on the side wall of one pillar 22.
Since the control gate 30 (word line) can be formed, it is suitable for high integration.

In each of the above-described embodiments, the use of hot carriers for writing and erasing eliminates the need for a thin tunnel oxide film and suppresses defects such as erroneous reading due to defects in the tunnel oxide film. Further, the hot carrier injection is less susceptible to fluctuations in the oxide film thickness and the like as compared with the FN tunnel current, so that the erase characteristics can be made uniform, and the occurrence of over-erase can be suppressed. The present invention is not limited to the above-described first to fourth embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

[0038]

As described above, according to the present invention, it is possible to obtain a non-volatile semiconductor memory device which can obtain a uniform erase characteristic and can prevent erroneous reading of data. In addition, a nonvolatile semiconductor memory device that can improve the charge retention characteristics can be obtained.

[Brief description of drawings]

FIG. 1 is a sectional view showing a configuration of a memory cell in a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a pattern plan view showing a configuration of a memory cell in the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

3 is a cross-sectional view showing a first manufacturing process for explaining a manufacturing process of the nonvolatile semiconductor memory device shown in FIGS. 1 and 2. FIG.

FIG. 4 is a cross-sectional view showing a second manufacturing process for explaining the manufacturing process of the nonvolatile semiconductor memory device shown in FIGS. 1 and 2;

5 is a cross-sectional view showing a third manufacturing step for explaining the manufacturing step of the nonvolatile semiconductor memory device shown in FIGS. 1 and 2. FIG.

FIG. 6 is a cross-sectional view showing a fourth manufacturing step for explaining the manufacturing step of the nonvolatile semiconductor memory device shown in FIGS. 1 and 2;

FIG. 7 is a sectional view showing the structure of a memory cell in a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

8 is a pattern plan view showing an arrangement example of contacts between a bit line and a drain region for realizing the configuration shown in FIG. 7. FIG.

FIG. 9 is a sectional view showing the structure of a memory cell in a nonvolatile semiconductor memory device according to a third embodiment of the present invention.

FIG. 10 is a pattern plan view showing a configuration of a memory cell in a nonvolatile semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 11 is a cross-sectional view taken along the line BB ′ of the pattern shown in FIG. 10, for illustrating the structure of the memory cell in the nonvolatile semiconductor memory device according to the fifth embodiment of the present invention.

FIG. 12 is a perspective view showing a configuration of a memory cell for explaining a conventional nonvolatile semiconductor memory device.

FIG. 13 is a cross-sectional configuration diagram of the memory cell shown in FIG. 11 for explaining a conventional nonvolatile semiconductor memory device.

[Explanation of symbols]

21 ... P-type silicon substrate (semiconductor substrate), 22 ... Columnar structure (pillar), 23 ... Source region, 24 ... Drain region, 2
5 ... Channel region, 26 ... N ^-- type impurity diffusion region, 27
... Gate oxide film, 28 ... Floating gate, 29 ...
Insulating film, 30 ... Control gate (word line), 31
... interlayer insulating film, 32 ... bit line.

Claims (4)

(57) [Claims] 1. A memory cell having a floating gate formed on a semiconductor substrate via a gate oxide film, and writing and erasing data to and from the memory cell,
Channel hot electron injection and hot hole injection into the floating gate should be performed.
The channel hot electrode to the floating gate above.
The gate oxidation is performed from the vicinity of the drain region by using the Ktron injection.
Hot through the floating gate through the film
Hole injection is provided adjacent to the source region and
Region has the same conductivity type and has a lower impurity concentration than the source region
A nonvolatile semiconductor memory device, characterized in that the operation is performed from the impurity diffusion region through the gate oxide film . 2. The channel hot electron injection and hot hole injection to the floating gate are performed in a region between the drain region and the source region formed in the semiconductor substrate. Non-volatile semiconductor memory device. 3. A pillar formed on the main surface of the semiconductor substrate,
A floating gate formed around the pillar via a gate oxide film, a control gate formed around the floating gate via an insulating film, and formed on a surface region of the semiconductor substrate below the control gate. A source region, a drain region formed above the pillar, and a channel region formed in the pillar between the source region and the drain region in a direction perpendicular to the main surface of the semiconductor substrate. A memory cell formed in the semiconductor substrate under the floating gate and the channel region, the memory cell having an impurity diffusion region having the same conductivity type as the source region and a lower impurity concentration than the source region. Nonvolatile semiconductor memory device. 4. Writing data to the memory cell from the channel region near the drain region,
Channel hot electrons are injected into the floating gate through the gate oxide film to erase data in the memory cell, and hot holes are injected into the floating gate from the impurity diffusion region through the gate oxide film. The non-volatile semiconductor memory device according to claim 3 , wherein the non-volatile semiconductor memory device comprises: