JPH06177358A - Nonvolatine storage device - Google Patents

Abstract

PURPOSE:To enable the data to be rapidly written-in by a method wherein the surface potential is graded between a charge accumulated layer and a select gate to efficiently produce a charge having high etching capacity in a channel region thereby enabling the charge to be implanted from the source region side of the charge accumulated layer. CONSTITUTION:The non-volatile memory is provided with a select gate 19 formed in a sidewall shape along the line direction holding a floating gate 15 and an insulating film. Accordingly, the surface potential can be graded between the floating gate 15 and the select gate 19 to efficiently produce channel hot electrons thereby enabling the hot electrons to be implanted from the source region 12a side of the floating gate 15. Furthermore, the implanted current between the floating gate 15 and the select gate 19 is to be continuously increased with the increase in the impressed voltage on a control gate 17 regardless of the current in a source region 12a and a drain region 12b thereby enabling the data to be written-in without decelerating the rate thereof.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a flash EEPROM (Ele
ctrically Erasable Programmable Read OnMemory)
For example, the present invention relates to a nonvolatile memory device including a nonvolatile memory element that stores information by injecting or extracting charges.

[0002]

2. Description of the Related Art Conventionally, a non-volatile memory element (hereinafter referred to as "memory transistor") that stores data by injecting and extracting charges on a single semiconductor substrate.
However, various non-volatile memory devices (hereinafter referred to as “non-volatile memory”) arranged in a matrix along the row direction and the column direction have been proposed.

An example of the above memory transistor is shown in FIG. FIG. 9 is a diagram schematically showing a schematic configuration of a conventional memory transistor. This memory transistor is of a flash type, and as shown in FIG. 9, a P-type silicon substrate 1 and an N-type source region 2 and an N-type drain region 3 which are formed in a surface layer of the silicon substrate 1 with a predetermined gap. And a control gate 5 formed on the channel region 4 which is formed so as to be sandwiched between the source region 2 and the drain region 3,
A floating gate 6 surrounded by an insulating film (not shown) and having no external connection is provided between the control gate 5 and the channel region 4.

In the memory transistor, data is written from the drain region 3 side. That is, writing is performed by applying a high electric field between the control gate 5 and the drain region 3b and flowing a saturated channel current between the source region 2 and the drain region 3. Drain region 3
In the nearby pinct off region, the electrons accelerated by the high electric field are ionized.
The so-called channel hot electrons are generated, and these channel hot electrons are generated by FN (Fowler-No.
It is injected into the floating gate 6 through a tunnel.

[0005]

With the recent development of the semiconductor industry, there is a demand for higher speed devices. Therefore, in the non-volatile memory including the memory transistor shown in FIG. 9, there is a need to reduce the drain voltage of the memory transistor as much as possible for the following two reasons in design in order to speed up data writing. .

The drain breakdown voltage when the memory transistor is turned on is reduced to reduce the size of the drain region. Reduce the current consumption when writing data. Therefore, in order to reduce the drain voltage to about 4 V or 5 V, it has been considered to increase the gate voltage to raise channel hot electrons to the floating gate to improve the writing speed.

However, when writing data from the drain side, when the gate voltage is raised while keeping the drain voltage constant, the injection current increases at first, but channel hot electrons are optimally generated at a certain gate voltage. Since it has a value, even if the drain voltage is fixed and the gate voltage is increased, the electric field along the channel direction becomes weak near the drain. Therefore, the generation of hot electrons is reduced, and the actual efficiency of electron injection into the floating gate is not so high.

In order to deal with the above, the control gate 5 is formed on the channel region 4 as shown in FIG.
Also, a memory transistor has been proposed in which a select gate 7 formed in a sidewall shape is arranged beside the floating gate 6 and channel hot electrons are injected into the floating gate 6 from the source region 2 side (see “IEDM 89 "reference). The source region 2 and the drain region 3 are in contact with the bit line BL, the control gate 5 is in contact with the word line WL, and the select gate 7 is in contact with the select gate SGL.

In this memory transistor, since hot electrons can be injected from the source region side, the injection current continues to increase as the gate voltage increases. Therefore, the data can be written without slowing down the speed. However, in the above memory transistor, the length of the select gate in the channel direction (hereinafter,
"Width" must also be scaled down.
However, as described above, since the select gate 7 is in contact with the select gate SGL, its wiring resistance becomes high and the operation is delayed. for that reason,
The cell could not be made smaller than a certain area, and there was a limit to the size reduction of the cell.

In view of the above, it is an object of the present invention to provide a non-volatile memory device which can improve charge injection efficiency, can write data at high speed, and can cope with further miniaturization.

[0011]

According to the means for solving the problems according to the present invention, information is stored by injecting or extracting charges on a single semiconductor substrate having a predetermined first conductivity type. A non-volatile memory device in which a plurality of non-volatile memory elements are arrayed in a matrix along a row direction and a column direction, the predetermined non-volatile memory device being arranged in a column direction and in a row direction on a surface layer of the semiconductor substrate. The second conductivity type, which is formed with a space between the first and second conductivity types and serves as the source region and the drain region of the non-volatile memory elements adjacent to each other in the row direction and also serves as the bit line. A plurality of impurity diffusion layers of the type and a channel region formed so as to be sandwiched between the impurity diffusion layers described above are formed on a region other than a predetermined region on the source region side, and each channel is formed. Tunnel insulating film that allows passage of electric charges having high energy generated in the region, a charge storage layer that is formed on each of the tunnel insulating films and that stores charges that have passed through the tunnel insulating film, and a source on each of the channel regions. A gate insulating film formed in a predetermined region located on the region side and thicker than the tunnel insulating film, and formed on each gate insulating film in a sidewall shape next to each charge storage layer and in a row. And a select gate that is a select gate line shared by non-volatile memory elements arranged in the column direction and arranged in the column direction, and formed in the row direction on each of the charge storage layers and arranged in the row direction. And a gate which is a word line shared by the respective nonvolatile memory elements.

[0012]

In the above problem solving means, when writing information, a low voltage of the channel-on limit is applied to the select gate line which is the select gate of the nonvolatile memory element for writing information, A high voltage is applied to the word line that is the gate.

Then, in the selected non-volatile memory element, a surface potential gradient is generated between the select gate and the charge storage layer, and concentrated under the tunnel insulating film between the select gate and the charge storage layer. An electric field will be applied. Here, charges having high energy are generated, and the charges are injected from the source region side of the charge storage layer by FN tunneling through the tunnel insulating film. As described above, since the charges can be injected from the source region side, information can be written without decreasing the speed.

Further, since the impurity diffusion layer is formed along the column direction so that the non-volatile memory elements adjacent in the row direction share the source region and the drain region to form a bit line, the impurity diffusion layer is formed. Does not require a contact on the semiconductor substrate, and can afford a cell area. Therefore, the width of the select gate per cell can be made relatively wide. In addition to this, the select gates are also formed along the column direction so that the non-volatile memory elements arranged in the column direction share the select gate line, so that a contact on the semiconductor substrate is not required. Therefore, the wiring resistance can be reduced.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 shows a structure of a nonvolatile memory according to an embodiment of the present invention. FIG. 1A is a plan view showing a state in which a passivation film is peeled off, and FIG. 1B is a plan view of FIG. It is an II sectional view. The structure of the nonvolatile memory MD1 according to the present embodiment will be described with reference to FIGS.

The nonvolatile memory MD1 of this embodiment is shown in FIG.
As shown in (a) and (b), on a single P-type silicon substrate 11,
A plurality of flash type memory transistors MTr that store data by injecting or extracting electrons
1, MTr2, MTr3, MTr4 are arranged in a matrix along the row direction X and the column direction Y.

A memory transistor MTr is provided at one end (left side in the figure) of the surface layer of the P-type silicon substrate 11.
1, the source region 12a of MTr3, that is, the N-type impurity diffusion layer 121 to be the bit line BL1 is formed along the column direction Y. Similarly, at the other end (on the left side in the figure), the drain region 12b of the memory transistors MTr2, MTr4, that is, the N-type impurity diffusion layer 123 to be the bit line BL3 is formed along the column direction Y. Then, between the N-type impurity diffusion layer 121 and the N-type impurity diffusion layer 123, the drain regions 12 of the memory transistors MTr1 and MTr3 arranged in the column direction X are arranged.
b and the source regions 12a of the memory transistors MTr2 and MTr4, that is, N serving as the bit line BL2.
The impurity diffusion layers 122 are the impurity diffusion layers 121 and 123.
And are formed along the column direction Y at a predetermined interval. That is, the impurity diffusion layer 122 that becomes the bit line BL2 is adjacent to the memory transistor M in the row direction X.
Tr1, MTr2 and memory transistor MTr3
It is shared by MTr4.

Each buried impurity diffusion layer 121, 122,
Channel regions 1 generated so as to be sandwiched between 133
3, a tunnel oxide film 14 capable of tunneling channel hot electrons generated in the channel region 13 is formed on each of the regions except the predetermined region on the source region 12a side. Memory transistor MTr1,
Floating gates 151 and 152 for accumulating electrons tunneling through the tunnel oxide film 14 are formed on the tunnel oxide film 14 in the MTr2 formation region. Although not shown, the memory transistor MT
A floating gate is also formed on the tunnel oxide film in the r3 and MTr4 formation region.

Capacitor films 16 are formed on the floating gates 151 and 152, respectively, for confining the electrons accumulated in the floating gates 151 and 152 for a long time. Although not shown, a capacitor film is similarly formed on the floating gates in the memory transistor MTr3 and MTr4 formation regions.

Each memory transistor MTr1, MTr
2, a control gate 1 to which a predetermined control voltage is applied at the time of writing, erasing and reading of data on the capacitor film 16 in the formation region of 2, MTr3, MTr4.
71, 172, 173, 174 are formed. A gate oxide film 18 is formed on each of the channel regions 13 other than a predetermined region on the side of the source region 12a in the formation region of the memory transistors MTr1 and MTr2. Although not shown, the memory transistor MT
A gate oxide film is similarly formed on the channel region except the predetermined region on the source region side in the r3 and MTr4 formation region.

Memory transistors M arranged in the column direction Y
On the gate oxide film 18 in the Tr1 and MTr4 formation region,
Select gate 1 to be the select gate line SGL1
91 are formed along the column direction Y. Similarly, each memory transistor MTr arranged in the column direction Y is
2, select gates 192 serving as select gate lines SGL2 are formed on the gate oxide film 18 in the MTr4 formation region along the column direction Y. That is, the select gates 191 serving as the select gate lines SGL1 are the memory transistors M arranged in the column direction Y.
The select gate 192, which is shared by Tr1 and MTr3 and serves as the select gate line SGL2, includes the memory transistors MTr2 and MTr arranged in the column direction Y.
Share on 4.

Memory transistors M arranged in the row direction X
Control gate 17 in the formation region of Tr1 and MTr2
Gate wirings 201 serving as word lines WL1 are formed in the columns 1 and 172 along the column direction X. Similarly, the memory transistors MTr arranged in the row direction X are also arranged.
3, control gates 173, 1 in the MTr4 formation region
74 includes a gate wiring 202 which becomes the word line WL2.
Are formed along the column direction X. That is, the gate wiring 201 serving as the word line WL1 is shared by the memory transistors MTr1 and MTr2 arranged in the row direction X, and the gate wiring 202 serving as the word line WL2.
Are memory transistors MTr3 arranged in the row direction X.
It is shared by MTr4.

In the following description, the memory transistors MTr1, MTr2, MTr3, MTr4 are collectively referred to as "memory transistor MTr". The N-type impurity diffusion layers 121, 122 and 123 are collectively referred to as "N-type impurity diffusion layer 12", and the floating gates 151, 152, 153 and 154 are collectively referred to as "floating gate 15" and the control gate 171. , 172, 173, 174 are collectively referred to as "control gate 17" and select gates 191, 1
92 is generically referred to as "select gate 19," and gate lines 201 and 202 are collectively referred to as "gate line 2".
"0".

The P-type silicon substrate 11 has a specific resistance of 5 to 2
As low as 0 Ωcm is used. The source region 12a of the N-type impurity diffusion layer 12 has a single source structure composed of only the N ⁺ -type impurity diffusion layer, and the drain region 12b includes the N ⁺ -type impurity diffusion layer and the N ⁺ -type impurity diffusion layer. N ⁻ joined to the end portion on the source region 12a side
Type LDD (light dop)
ed drain) structure. Incidentally, N-type impurity diffusion layer 12, and the N ⁺ -type impurity diffusion layer, N ⁺ -type impurity diffusion layer so as to surround the deep-formed N ^- may be double diffusion structure comprising a type impurity diffusion layer.

The tunnel oxide film 14 is made of, for example, an insulating material such as SiO _{2 and} has a very thin film thickness of about 100 Å in order to tunnel electrons. The floating gate 15 is made of, for example, a conductive material such as polysilicon which is doped with phosphorus at a high concentration to reduce its resistance, and is provided at a predetermined distance from the select gate 19.

The capacitor film 16 is made of an insulating material such as SiO ₂ and has a film thickness of the floating gate 15.
4 is set to a film thickness capable of confining accumulated electrons. The capacitor film 16 may be formed of, for example, Si ₃ instead of the single layer structure of the SiO ₂ film.
An ONO (oxide) having a multilayer structure in which a nitride film such as N _{4 is} sandwiched from above and below by an oxide film such as SiO ₂
-nitride-oxide) film may be used. In this case, the thickness of the bottom oxide film is about 100Å and the thickness of the nitride film is about 15
The thickness of the top oxide film is preferably about 0Å and about 50Å.

The control gate 17 is made of, for example, a conductive material such as polysilicon which is doped with phosphorus at a high concentration to reduce its resistance, and is provided at a predetermined distance from the select gate 19. The gate oxide film 18 is, for example, Si
It is made of an insulating material such as O _{2 and} has a thin film thickness of about 150Å.

The select gate 19 is made of a conductive material such as polysilicon which is doped with phosphorus at a high concentration to reduce its resistance, and is provided in a sidewall shape. The gate wiring 20 is made of, for example, a conductive material such as polysilicon which is doped with phosphorus at a high concentration to reduce resistance. Further, between the select gate 19 and the gate wiring 20, between the select gate 19 and the control gate 17, and between the select gate 19 and the floating gate 15,
PSG (phospho-silicate gl) which is P-doped SiO ₂
BPSG (bron-phospho-silicate) with B mixed in ass)
An interlayer insulating film 21 made of an insulating material such as glass is filled. Therefore, the select gate 19 and the gate wiring 20, the select gate 19 and the control gate 17, and the select gate 16 and the floating gate 15 are insulated from each other. In addition, the tunnel oxide film 14 and ONO are formed around the floating gate 15.
It is surrounded by the film 16 and the interlayer insulating film 21 and is not connected to the outside.

Further, although not shown, the gate wiring 2
A passivation film made of an insulating material such as PSG is laminated on the entire surface of the memory cell 0 to protect the surface of the memory transistor MTr and prevent the invasion of contaminants from the outside. As described above, the nonvolatile memory MD1 is a so-called virtual ground array in which the impurity diffusion layer 12 is not contacted on the silicon substrate 1, so that the memory transistors MTr are mounted at high density.

FIG. 2 is an equivalent circuit diagram of the nonvolatile memory. The electrical configuration of the nonvolatile memory MD1 will be described with reference to FIG. The non-volatile memory MD1 is
As shown in FIG. 2, memory cells MC1, MC2 surrounded by dotted lines
MC3 and MC4 are arranged and each memory cell MC1 and MC
2, MC3 and MC4 are one memory transistor MTr
1 cell / 1 consisting of 1, MTr2, MTr3, MTr4
It has a transistor structure.

The word line WL1 is connected to the control gates of the memory transistors MTr1 and MTr2 arranged in the row direction X, and the word line WL2 is connected to the control gates of the memory transistors MTr3 and MTr4 arranged in the row direction X. ing. In addition, the memory transistors MTr1 and MT arranged in the column direction Y
Select gate line SGL1 to the select gate of r3
And the select gate line SGL2 is connected to the select gates of the memory transistors MTr2, MTr4 arranged in the column direction Y.

Further, the bit line BL is connected to the sources of the memory transistors MTr1 and MTr3 arranged in the column direction Y.
1 is connected, and the bit line BL3 is connected to the drains of the memory transistors MTr2 and MTr4 arranged in the column direction Y. Then, the memory transistors MTr1, MTr2 and MTr3, M that are adjacent in the row direction X
The source and drain of Tr4 are connected in series, and the bit line BL2 is connected to the connection intermediate point.

3 and 4 are schematic sectional views showing a method of manufacturing a nonvolatile memory in the order of steps. Note that, in FIGS. 3 and 4, only one memory transistor is shown for convenience of description. First, a tunnel oxide film, a floating gate, a capacitor film and a control gate are formed. That is, as shown in FIG. 3A, thermal oxidation (for example, thermal oxidation temperature: about 800 ° C., reaction gas: O
₂ / N ₂ = 1/100, oxidation time: 3 minutes), and thermal oxidation (S) that becomes a tunnel oxide film on the P-type silicon substrate 11 is performed.
The iO ₂ ) film 30 is laminated to about 100 Å. Furthermore, L
Polysilicon 31 serving as a floating gate is deposited on the thermal oxide film 30 by a PCVD (Low Pressure Chemical Vapor Deposition) method, and the polysilicon 31 is doped with a conductive substance such as phosphorus at a high concentration. Subsequently, the polysilicon 31 is thermally oxidized to form a thermal oxide (SiO ₂ ) film 32 which will be a capacitor film on the polysilicon 31. Further, a polysilicon 33 to be a floating gate is deposited on the thermal oxide film 32 by the LPCVD method, and the polysilicon 33 is doped with a conductive material such as phosphorus at a high concentration.

Then, as shown in FIG. 3B, a resist 34 is applied on the polysilicon 33, and the thermal oxide film 30 and the polysilicon are left by a photolithographic technique, leaving a portion directly below the resist 34. 3, the thermal oxide film 32 and the polysilicon 33 are removed to remove the tunnel oxide film 14 and the floating gate 1.
5, the capacitor film 16 and the control gate 17 are formed in an island shape.

After the formation process of the tunnel oxide film, the floating gate, the capacitor film and the control gate is completed, the gate oxide film, the select gate and the impurity diffusion layer are formed. That is, as shown in FIG. 3C, wet oxidation (for example, wet oxidation temperature:
The gate oxide film 14 is stacked on the entire surface by about 900 ° C. and wet oxidation time: about 1 hour by about 150Å. Further, polysilicon 35 is deposited on the entire surface of the gate oxide film 14 by the LPCVD method, and the polysilicon 34 is doped with a conductive substance such as phosphorus at a high concentration. Then, the polysilicon 34 is etched back to form the tunnel oxide film 1.
4, sidewalls 36 and 37 are formed in stripes along the column direction on the source region and drain region sides of the floating gate 15, the capacitor film 16 and the control gate 17.

Then, as shown in FIG. 3D, the implantation (imp) is performed by using the control gate 17, the floating gate 15 and the sidewalls 36 and 37 as a mask.
lantation) or the like, for example, P ⁺ or the like is injected. As a result, the N ⁺ layer 38 is formed on the surface layer of the P-type silicon substrate 11.
Is deeply formed. Next, as shown in FIG. 3E, the sidewall 37 on the drain region side is removed by etching. As a result, the sidewall 36 on the source region side becomes the select gate 19. Then, using the control gate 17, the floating gate 15, and the select gate 19 (sidewall 36) as a mask, LDD ions such as As ⁺ are implanted by implantation or the like. As a result, the surface layer of the P-type silicon substrate 11 is
The N ⁻ layer 39 is shallowly formed.

When the steps of forming the gate oxide film, the select gate and the impurity diffusion layer are completed, an interlayer insulating film is formed. That is, as shown in FIG.
The BPSG 40 is thickly deposited on the entire surface by the memical vapor deposition method, and the BPSG 40 is flattened by reflowing to form the interlayer insulating film 21. After that, annealing is performed. Then, the N ⁺ layer 38 and the N ⁻ layer 39 are joined, and the N-type impurity diffusion layer 12 is formed in the column direction in a self-aligned manner with the channel region 13 interposed therebetween. That is, the source region 12a has a single source structure composed only of the N ⁺ -type impurity diffusion layer, and the drain region 12b has the N ⁺ -type impurity diffusion layer.
-Type impurity diffusion layer, N source region of the N ⁺ -type impurity diffusion layer is joined to the end portion ^- the LDD structure comprising the impurity diffusion layer.

When the step of forming the interlayer insulating film is completed, metallization is performed. That is, as shown in FIG. 4B, the interlayer insulating film 21 is etched back to expose the surface of the control gate 17. And FIG. 4 (c)
As shown in FIG. 3, polysilicon is deposited on the entire surface by sputtering or the like, and a conductive material such as phosphorus is doped at a high concentration. Then, this polysilicon is patterned in a stripe shape along the row direction to form a gate wiring 20.

When the metallization is completed, a passivation film is formed. That is, as shown in FIG. 4D, the passivation film 41 is formed by depositing silicon nitride (Si ₃ N ₄ ) on the entire surface by the CVD (Cmemical Vapor Deposition) method. Next, referring mainly to FIG. 2 and Table 1, the nonvolatile memory MD1
The operation of writing, erasing and reading the data will be described. Note that the writing and reading shown in Table 1 are
It is assumed that the memory cell MC1 shown in FIG. 2 is selected.

[0040]

[Table 1]

<Write (WRITE)> The word line WL2 and the select gate SGL2 are set to the ground potential 0V, and the write inhibit voltage 5V is applied to the bit lines BL2 and BL3 to write data in the memory cell MC.
In order to select 11, bit line BL1 is set to ground potential 0V.
And the channel gate of the memory transistor MTr1 is 1.5V to the select gate line SGL1.
And a high voltage of 17 V is applied to the word line WL1.

Then, as shown in FIG. 5, in the memory transistor MTr1 in the selected memory cell MC1, the select gate 191 and the floating gate 15 are formed.
A surface potential gradient is generated between the select gate 19 and
Therefore, an electric field is intensively applied under the oxide film between 1 and the floating gate 151. Here, the electrons are accelerated and channel hot electrons are generated. The hot electrons are FN tunneled and injected from the source region 12a side of the floating gate 151, and a data "1" write state is set.

On the other hand, in the memory transistor of the non-selected memory cell, the surface potential gradient is not generated between the select gate and the floating gate, and the injection current is not generated, so that the channel hot electrons are not injected into the floating gate. That is, no data is written. <Erase> Data is erased collectively. That is, all word lines WL1, WL
2 and select gates SGL1 and SGL2 are set to ground potential 0V, and all bit lines BL1, BL2
A high voltage of 14V is applied to BL3.

Then, as shown in FIG. 6, in the memory transistor MTr, the floating gate 15
An FN tunnel current is generated between the drain region 12b and the electrons accumulated in the floating gate 15 are FN tunneled and flow out to the drain region 12b to be removed, whereby a data erased state, that is, data "0".
The writing state becomes. <Read (READE)> A read inhibit voltage of -5V is applied to the word line WL2, the select gate SGL2 is set to the ground potential 0V, and 1V is applied to the bit lines BL2 and BL3 to select the memory cell MC1 to be read. , 5V is applied to the select gate SGL1 to set the bit line BL1 and the word line WL1 to the ground potential 0V.

Then, FIGS. 7A and 7B and FIG.
As shown in (a) and (b), the selected memory cell MC
Memory transistor MTr1 and memory cell M in 1
The memory transistor MTr3 in the non-selected memory cell MC3 sharing the select gate line SGL1 with C1
Since 5 V is applied to the select gate 191, the P-type silicon substrate 11 immediately below the select gate 191 is
Electrons having a concentration equal to the hole concentration of the silicon substrate 11 are induced on the surface of the inversion layer (inversion layer).
ayer) IL will occur.

At this time, as shown in FIG. 7A, the floating gate 1 of the selected memory transistor MTr1 is
When electrons are accumulated in 51, positive charges are aligned on the surface of the silicon substrate 11 directly below the floating gate 151 under the influence of the electrons.
Therefore, the channel is not formed in the memory transistor MTr1 and the drain region 12b to the source region 12 are not formed.
No current flows through a. On the other hand, as shown in FIG.
If no electrons are stored in the floating gate 151 of the selected memory transistor MTr1, negative charges are aligned on the surface of the silicon substrate 11 directly below the floating gate 151. Therefore, a channel is formed in the memory transistor MTr1 and a current flows from the drain region 12b to the source region 12a. If this state is sensed by a decoder and a sense amplifier (not shown), the data stored in the memory transistor MTr1 is read.

Further, as shown in FIG. 8A, in the non-selected memory transistor MTr3, when electrons are accumulated in the floating gate 153, −5V is applied to the control gate 173.
The influence of this negative charge is blocked by the electrons and does not reach the surface of the silicon substrate 11 directly below the floating gate 153. That is, the floating gate 15
As described above, the positive charges remain aligned on the surface of the silicon substrate 11 immediately below the silicon substrate 3. Therefore, no channel is formed in the memory transistor MTr3, and no current flows from the drain region 12b to the source region 12a. On the other hand, as shown in FIG. 8B, the memory transistor MT
When electrons are not accumulated in the floating gate 153 of r3, the influence of the negative charge from the control gate 173 extends to the surface of the silicon substrate 11 directly below the floating gate 153. Then, as described above, if electrons are not accumulated in the floating gate 153, the floating gate 153
Since the negative charges are aligned on the surface of the silicon substrate 11 immediately below, the negative charges aligned on the surface of the silicon substrate 11 and the negative charges from the control gate 173 repel each other. Positive charges are aligned on the surface. Therefore, no channel is formed in the memory transistor MTr3, and no current flows from the drain region 12b to the source region 12a. That is, in the non-selected memory cell MC3 sharing the select gate line SGL1 with the selected memory cell MC1, whether in the data write state or the data erase state,
The memory transistor MTr3 never becomes conductive. Therefore, the data stored in the non-selected memory cell MC3 will not be erroneously read.

In the memory transistor MTr, the channel region 13 formed so as to be sandwiched by the impurity diffusion layers 12 is formed.
Of the tunnel oxide film 14 formed on the source region 12a side except the predetermined region and allowing passage of channel hot electrons generated in the channel region 13, and the tunnel oxide film 14 formed on the tunnel oxide film 14. A floating gate 15 for accumulating the passed hot electrons, a gate oxide film 18 formed on the channel region 13 in a predetermined region on the source region 12a side and thicker than the tunnel oxide film 14, and a gate oxide film 18
Since the floating gate 15 and the select gate 19 formed in a sidewall shape along the column direction with the insulating film sandwiched therebetween are provided above, the surface potential gradient between the floating gate 15 and the select gate 19 is increased. To generate channel hot electrons efficiently, and to generate these hot electrons in floating gate 1
5 from the source region 12a side.

In this way, by injecting hot electrons from the source region 12a side, the source region 12 is formed.
Regardless of the current between the a-drain region 12b, the injection current between the floating gate 15 and the select gate 19 continues to increase as the voltage applied to the control gate 17 increases, so that data can be written without slowing down. It can be carried out.

As described above, the generation of hot electrons occurs regardless of the current between the source region 12a and the drain region 12b, so that the impurity concentration on the drain region 12b side is such that electrons are transferred from the floating gate 15 to the drain region 12b. It can be optimized considering only the deletion of data that is leaked to. In addition, the width of the select gate 19 must be scaled down with the miniaturization, but the impurity diffusion layer 12 is shared by the memory transistors adjacent in the row direction to share the source region and the drain region to form a bit line. Since the impurity diffusion layer 12 is formed along the column direction, the impurity diffusion layer 12 does not need a contact on the silicon substrate 11, and the cell area can be afforded. Therefore, the width of the select gate 19 per cell can be made relatively wide. In addition to this, since the select gate 19 is also formed along the column direction so as to be shared by memory transistors arranged in the column direction to form a select gate line, a contact on the silicon substrate 11 is required. Therefore, the wiring resistance can be reduced. Therefore,
It is possible to prevent the operation from being delayed due to the miniaturization of the element, and it is possible to cope with further miniaturization without much restriction on the reduction of the cell area.

The present invention is not limited to the above embodiments, and it goes without saying that many modifications and changes can be made within the scope of the present invention. For example, in the above embodiment, the case where the P-type silicon substrate is used is described, but the N-type silicon substrate is used to inject holes,
The data may be stored by being taken out.

The same effect can be obtained by applying the present invention to a non-volatile memory including a MNOS type or MONOS type memory transistor which eliminates a floating gate and accumulates charges in a trap film. . Further, as shown in Table 2, when writing data, the select gate SGL2 is set to the ground potential 0 V, and the bit line B
In order to select a memory cell in which data is to be written, 5 V is applied to L2 and BL3 in advance, the bit line BL1 is set to the ground potential of 0 V, and the select gate line SGL1 is set to 1.
5V may be applied and a high voltage of 14V may be applied to the word lines WL1 and WL2. Further, at the time of reading data, the select gate SGL2 is set to the ground potential 0V, 1V is applied to the bit lines BL2 and BL3, and 5V is applied to the select gate SGL1 to select the memory cell to be read, The line BL1 and the word lines WL1 and WL2 may be set to the ground potential 0V.

[0053]

[Table 2]

According to the above data writing method, the data can be written in a line batch to the memory cells sharing the select gate line SGL1. According to the data reading method, the select gate line SGL is
The data stored in the memory cells sharing 1 can be collectively read out by the line. Further, instead of the data reading method shown in Tables 1 and 2, the data may be read by applying a sense voltage to the word line of the memory cell to be read.

[0055]

As is apparent from the above description, according to the present invention, a surface potential gradient is formed between the charge storage layer and the select gate to efficiently generate charges having high energy in the channel region. Since charges can be injected from the source region side of the charge storage layer, data can be written without slowing down the speed.

Further, since the impurity diffusion layer does not require contact on the semiconductor substrate and the cell area can be afforded,
The width of the select gate per cell can be made relatively wide. In addition to this, the select gate does not need a contact on the semiconductor substrate, and the wiring resistance can be reduced. Therefore, it is possible to prevent the operation from being delayed due to the miniaturization of the device, and it is possible to cope with further miniaturization without much restriction on the reduction of the cell area.

[Brief description of drawings]

1A and 1B show a structure of a nonvolatile memory according to an embodiment of the present invention, FIG. 1A is a plan view showing a state in which a passivation film is peeled off, and FIG. I-
FIG.

FIG. 2 is an equivalent circuit diagram of a nonvolatile memory.

FIG. 3 is a schematic cross-sectional view showing a method of manufacturing a nonvolatile memory in the order of steps.

4A to 4D are schematic cross-sectional views showing the manufacturing method following the one in FIG.

FIG. 5 is an explanatory diagram schematically showing the operation of the memory transistor at the time of writing data.

FIG. 6 is an explanatory diagram schematically showing the operation of the memory transistor when erasing data.

FIG. 7 is an explanatory diagram schematically showing the operation of the memory transistor in the selected memory cell at the time of reading data.

FIG. 8 is an explanatory diagram schematically showing the operation of a memory transistor in a non-selected memory cell sharing a select gate line with a selected memory cell when reading data.

FIG. 9 is a diagram schematically showing a schematic configuration of a memory transistor used in a conventional nonvolatile memory.

FIG. 10 is a schematic cross-sectional view showing a schematic configuration of a memory transistor according to a prior art.

[Explanation of symbols]

MD1 Non-volatile memory MC1, MC2, MC3, MC4 Memory cell MTr, MTr1, MTr2, MTr3, MTr4 Memory transistor 11 P type silicon substrate 12, 121, 122, 123 N ⁺ type impurity diffusion layer 12a Source region 12b Drain region 13 Channel Region 14 Tunnel oxide film 15, 151, 152, 153 Floating gate 16 Capacitor film 17, 171, 172, 173, 174 Control gate 18 Gate oxide film 19, 191, 192 Select gate 20, 201, 202 Gate wiring BL1, BL2 BL3 bit line SGL1, SGL2 select gate line WL1, WL2 word line

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 29/788 29/792 H01L 29/78 371

Claims (1)

[Claims] 1. A plurality of non-volatile storage elements for storing information by injecting and extracting charges on a single semiconductor substrate having a predetermined first conductivity type are arranged in a row direction and a column direction. A non-volatile memory device, which is arranged in a matrix along with, wherein the semiconductor substrate is formed on the surface layer of the semiconductor substrate along the column direction and at predetermined intervals in the row direction, and is adjacent to each other in the row direction. A plurality of impurity diffusion layers having a second conductivity type opposite to the first conductivity type and serving as a bit line and a source region and a drain region between the nonvolatile memory elements, and the impurity diffusion layers. Each of the channel regions formed so as to be sandwiched between the layers is formed on a region except a predetermined region on the source region side, and a transistor having a high energy generated in each channel region is passed through. A channel insulating film, a charge storage layer formed on each of the tunnel insulating films and storing charges that have passed through the tunnel insulating film, and formed on a predetermined region located on the source region side on each of the channel regions, A gate insulating film that is thicker than the tunnel insulating film, and formed on each of the gate insulating films in a sidewall shape next to each of the charge storage layers, extending in the column direction, and each nonvolatile arrayed in the column direction. A select gate that is a select gate line shared by storage elements, and a word formed on each charge storage layer along the row direction and shared by each nonvolatile storage element arranged in the row direction. A non-volatile memory device including a gate that is a line.