KR100798267B1 - Flash memory device and method for manufacturing the same - Google Patents

Abstract

A flash memory device and a manufacturing method thereof are provided to reduce resistance of a source line and to improve integration degree of a cell by forming the source line with a silicide layer. Plural trench lines are formed in a first direction. Plural gate lines are formed in a second direction perpendicular to the first direction. A junction(21) is formed between the gate lines by implanting ion into an active region and a trench region in the second direction parallel with the gate line. A silicide layer(23) is self-aligned on the junction in a direction parallel with the gate line in a common source region. The trench line is parallel with a bit line. The gate line is parallel with a word line. The self-aligned silicide layer is formed on the same plane. The trench region, the trench region, and the common source region are formed on a semiconductor substrate.

Description

Flash memory device and manufacturing method therefor {FLASH MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME}

1 is a view for explaining a flash memory device according to the present invention.

FIG. 2 is a cross-sectional view taken along the line II-II 'of FIG. 1.

3 is a side view of FIG. 2;

4 is a view for explaining a method for forming a junction by a flash memory device manufacturing method according to the present invention.

<Explanation of symbols for the main parts of the drawings>

11 ... common source region 13 ... gate line

15 ... drain region 17 ... drain contact

19 ... trench line 21 ... junction

23 ... Silicide layer 100 ... SAS mask

The present invention relates to a flash memory device and a method of manufacturing the same.

In general, a flash memory device is manufactured by taking advantage of EPROM having programming and erasing characteristics and EEPROM having electrical programming and erasing characteristics. Such a flash memory device includes a tunnel oxide film of a thin film formed on a silicon substrate, a floating gate and a control gate stacked under an insulating film, and a source and drain region formed in an exposed substrate portion. Realize the storage state, and also program and erase electrically.

Such a flash memory device has a source connection layer connecting a source of each unit cell to form a source line. Such a source connection layer may be formed using a metal contact method of forming and connecting a contact to a source of each unit cell, but this method is not suitable for highly integrated devices because the contact margin must be considered. not. Therefore, in order to realize high integration of devices, a common source line including a dopant diffusion layer has been frequently applied through a self aligned source (SAS) process.

Specifically, in the SAS process, a field oxide layer is formed in order to form a common source line with an adjacent cell after opening a source region of a cell using a separate SAS mask in a state in which a gate electrode having a stacked structure is formed. Refers to the process of performing anisotropic etching to remove.

This SAS technology reduces the size of the cell in the direction of the bit line BL, which is essential for the 0.25-micron technology because it can reduce the gate-to-source space portion. It is a process. The introduction of this SAS technology can reduce cell size by about 20%. However, since the common source line is formed along the trench profile in the memory cell to which the SAS technology is applied, the contact resistance of the source per cell is rapidly increased.

In this case, a junction is widely used as a source line of the flash memory as described above, and as a conventional method of forming the source line, a junction is formed through ion implantation as is well known. The method is widely used.

However, the source line formed by the junction has a high electrical resistance corresponding to about 200 to 300 Ω for each cell, so the loss of current is large. Supplying. In this way, not only is the current loss large, but also a source contact is required for each of 16 to 24 cells, so that a significant loss can be incurred even in the layout.

As described above, according to the conventional method of forming a flash memory device and a source line thereof, there is a problem that the loss of unnecessary current is increased due to high resistance, and many source contacts are required in layout, resulting in a decrease in cell density.

An object of the present invention is to provide a flash memory device capable of reducing the resistance of a source line and improving the degree of integration of a cell, and a method of manufacturing the same.

In order to achieve the above object, a flash memory device according to the present invention includes a flash memory device including a semiconductor substrate having an active region, a trench region, and a common source region, the plurality of trench lines formed in a first direction; A plurality of gate lines formed in a second direction perpendicular to the first direction; A junction formed between the gate lines and formed by ion implantation into the active region and the trench region in a second direction parallel to the gate line; A silicide layer self-aligned over said junction in a direction parallel to said gate line in said common source region; It includes.

Further, in the present invention, the trench line is formed parallel to the bit line direction, the gate line is formed parallel to the word line direction.

In the present invention, the self-aligned silicide layer is formed on the same plane.

In addition, the flash memory device manufacturing method according to the present invention in order to achieve the above object comprises the steps of forming an active region, a trench region, a common source region in the semiconductor substrate; Forming an insulating material in the trench region and the common source region; Forming a first oxide film, a first polysilicon, a second oxide film, and a second polysilicon on the semiconductor substrate; Patterning the second polysilicon, the second oxide film, and the first polysilicon to form a plurality of gate lines; Implanting ions using a SAS mask to form junctions between the gate lines in the active region and the trench regions in a direction parallel to the gate lines; Forming a self-aligned silicide layer over the junction in the common source region in a direction parallel to the gate line; It includes.

In the present invention, the ion implantation is performed by a gradient ion implantation method.

In addition, in the present invention, the ion implantation is performed by inclined ion implantation in a direction perpendicular to the gate line direction.

In the present invention, the self-aligned silicide layer is formed on the same plane.

According to the present invention, there is an advantage that can reduce the resistance of the source line and improve the integration of the cell.

In the description of an embodiment according to the present invention, each layer (film), region, pattern or structure is "on / above / over / upper" of the substrate, each layer (film), region, pad or patterns or In the case described as being formed "down / below / under / lower", the meaning is that each layer (film), region, pad, pattern or structure is a direct substrate, each layer (film), region, It may be interpreted as being formed in contact with the pad or patterns, or may be interpreted as another layer (film), another region, another pad, another pattern, or another structure formed in between. Therefore, the meaning should be determined by the technical spirit of the invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a view illustrating a flash memory device according to the present invention, FIG. 2 is a cross-sectional view taken along the line II-II ′ of FIG. 1, and FIG. 3 is a side view of FIG. 2.

1 to 3, in the flash memory device according to the exemplary embodiment, trench lines 19 corresponding to device isolation regions are formed on a semiconductor substrate, and a plurality of trench lines 19 are formed. Is formed parallel to the bit line BL direction. Here, the dotted line represents the boundary of the side wall slope of the trench line 19.

A common source region 11 formed by implanting impurity ions in the word line WL direction is formed under the surface of the semiconductor substrate. The common source region 11 includes a junction formed by implanting impurity ions and a silicide layer formed by self-alignment. This will be described later.

In addition, a plurality of gate lines 13 are formed in a direction perpendicular to the trench line 19, that is, in a direction parallel to the word line WL. A drain region 15 is formed in a region opposite to the common source region 11 based on the gate line 13, and a drain contact 17 is formed in a portion of the drain region 15.

As shown in FIG. 1, the SAS mask 100 exposes a portion of the gate line 13 and a gate line 13 adjacent to each other, and an exposed boundary line of the SAS mask 100 is formed in the gate line ( 13) aligned with the gate line 13 at the top.

According to the flash memory device manufacturing method according to the present invention, an active region, a trench region, a common source region is formed in a semiconductor substrate, and an insulating material is formed in the trench region and the common source region which are etched and patterned.

The trench region is a region in which an isolation layer is formed, and a junction and a silicide layer are formed later in the common source region.

Subsequently, a first oxide film, a first polysilicon, a second oxide film, and a second polysilicon are formed on the semiconductor substrate, and the second polysilicon, the second oxide film, and the first polysilicon are patterned to form a plurality of gate lines 13. ).

Subsequently, the first oxide layer formed between the gate lines 13 adjacent to each other using the SAS mask 100 and the inside of the common source region 11 and the trench line 19 in which the silicide layer 23 is to be formed are formed. The insulating film is etched to expose the surface.

Next, ions are implanted using the SAS mask 100 to form the junction 21 between the gate lines 13 in the active region and the trench region in a direction parallel to the gate line 13. .

In the present invention, ion implantation for forming the junction 21 may be performed by a gradient ion implantation method.

In this case, as shown in FIG. 4, inclined ion implantation may be performed in a direction perpendicular to the gate line 13 direction. 4 is a view for explaining a method of forming a junction by a flash memory device manufacturing method according to the present invention.

In this case, as shown in FIG. 4, the gradient ion implantation may be performed by dividing into (a) direction and (b) direction. Accordingly, the implanted ions can be smoothly implanted into the sidewalls, and the resistance of the region can be lowered by the implantation of impurities.

In the common source region, a silicide layer 23 self-aligned is formed on the junction 21 in a direction parallel to the gate line 13.

The self-aligned silicide layer 23 may be formed through heat treatment, and a method of forming the self-aligned silicide layer 23 through heat treatment is already known, and thus the detailed description thereof will be omitted.

In the present invention, the self-aligned silicide layer 23 may be formed on the same plane. As an example for implementing this, in forming the trench line 19 to form an isolation layer on a semiconductor substrate, the regions where the silicide layer 23 is to be formed may be patterned together. Accordingly, the silicide layer 23 may be implemented on the same plane.

The silicide layer 23 makes it possible to reduce the resistance of the source line, and current can flow from the silicide layer 23 through the junction 21 to the cell.

As described above, the flash memory device manufactured by the flash memory device manufacturing method according to the present invention includes a plurality of trench lines 19 formed in a first direction and a plurality of gate lines formed in a second direction perpendicular to the first direction. 13).

In addition, the flash memory device according to the present invention is formed between the gate line 13, the junction 21 formed by ion implantation in the active region and the trench region in a second direction parallel to the gate line 13, And a silicide layer 23 self-aligned over the junction 21 in a direction parallel to the gate line 13.

The trench line 19 is parallel to the bit line direction, and the gate line 13 is formed parallel to the word line direction. In addition, the self-aligned silicide layer 23 is formed on the same plane.

When the source line is formed of the silicide layer 23 as described above, it is possible to have a low electrical resistance corresponding to about 5 to 6? As a result, current loss can be effectively prevented, and the number of cells that one source contact can cover can be increased by about 50 to 60 times. As a result, the number of source contacts required to process the same number of cells can be significantly reduced, and the density of cells can be improved.

As described above, according to the flash memory device and the manufacturing method thereof according to the present invention, there is an advantage in that the resistance of the source line can be reduced and the cell density can be improved.

Claims (7)

A flash memory device comprising a semiconductor substrate on which an active region, a trench region, and a common source region are formed, A plurality of trench lines formed in a first direction; A plurality of gate lines formed in a second direction perpendicular to the first direction; A junction formed between the gate lines and formed by ion implantation into the active region and the trench region in a second direction parallel to the gate line; A silicide layer self-aligned over said junction in a direction parallel to said gate line in said common source region; Flash memory device comprising a. The method of claim 1, And the trench line is parallel to the bit line direction and the gate line is parallel to the word line direction. The method of claim 1, And the self-aligned silicide layer is formed on the same plane. Forming an active region, a trench region, and a common source region in the semiconductor substrate; Forming an insulating material in the trench region and the common source region; Forming a first oxide film, a first polysilicon, a second oxide film, and a second polysilicon on the semiconductor substrate; Patterning the second polysilicon, the second oxide film, and the first polysilicon to form a plurality of gate lines; Implanting ions using a SAS mask to form junctions between the gate lines in the active region and the trench regions in a direction parallel to the gate lines; Forming a self-aligned silicide layer over the junction in the common source region in a direction parallel to the gate line; Including , And ion implantation is performed by a gradient ion implantation method. delete The method of claim 4, wherein And ion implantation is inclined ion implantation in a direction perpendicular to the gate line direction. The method of claim 4, wherein And the self-aligned silicide layer is formed on the same plane.

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