KR20050107698A - Flash memory device having finfet structure and fabrication method thereof - Google Patents

Abstract

Embodiments of the present invention provide a flash memory device having a pinpet structure and a method of manufacturing the same. The flash memory device includes an active region having a fin structure that traverses a semiconductor substrate. Assist gates are disposed across the active region of the fin structure. Gate spacers are disposed to cover the upper and sidewalls of the assist gates. A conformal tunnel oxide film is disposed between the neighboring assist gates to cover the active region of the fin structure. Conformed floating gate patterns covering sidewalls of the neighboring gate spacers and the tunnel oxide layer are disposed. Conformed dielectric layer patterns are disposed on the floating gate patterns. Control gate patterns are disposed on the assist gates to cover the dielectric layer patterns along the active region of the fin structure.

Description

Flash memory device having a finFET structure and a method of manufacturing the same {flash memory device having FinFET structure and fabrication method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a flash memory device having a finpet structure and a method of manufacturing the same.

Unlike a volatile memory device, a nonvolatile memory device retains previous data even when power is not supplied. Therefore, nonvolatile memory devices such as flash memory devices are widely used in file systems, memory cards, portable devices, and the like.

Flash memory devices can be broadly divided into NOR-type structures in which cells are arranged in parallel between bit lines and ground lines, and NAND-type structures arranged in series.NOR types are AND, DINOR, and VGA (Variable Ground) variants. Array type). The NOR type has the advantage of simplifying peripheral circuits and reducing read access time by configuring address decoding for read and program operations similar to those of DRAM. It also has the advantage of fast programming by using the hot electron injection method for programming. However, since the contact electrodes of the bit lines are required for each cell, there is a disadvantage that the cell area becomes larger than that of the NAND type.

In contrast, the NAND type is advantageous for integration, but the programming speed is slower than that of the hot electron injection method by using the FN tunneling method using the voltage difference between the gate and silicon substrate for programming, and the block is selected before the read operation. The disadvantage is that the read speed is relatively slow because each cell is connected in series and the operating resistance is large.

Therefore, taking advantage of the existing NOR type and the NAND type, the research has been conducted to improve the programming speed by using a channel hot electron (CHE) injection method, which is a programming method of the NOR type with similar density as NAND. . Among them, T. KoByashi et al.'A Giga-Scale Assist-Gate (AG) -AND-Type Flash Memory Cell with 20 MB / s programming throughput for content downloading applications. with 20-MB / s Programming Throughput for Content-Downloading Applications' (International Electron Devices Meeting, 2001, P29-32). In this study, as the channel hot electron (CHE) injection is possible in each cell by using the assist gate, the programming speed can be improved.

1 is a schematic diagram illustrating a programming principle of a flash memory device having an assist gate according to the related art.

Referring to FIG. 1, 0V is applied to the semiconductor substrate S, 0.6V is applied to the selected assist gate, and 8V is applied to the floating gate FG and 5V is applied to the data line DL. Do it. A channel is formed by applying 0.6 V to the selected assist gate to move electrons from the source S to the drain D of the gate, wherein the floating gate is driven by the voltage applied to the floating gate FG. Electrons flow into (FG) and are programmed. In this case, the neighboring unselected assist gate (unselected AG) maintains 0V to serve as device isolation. The voltage of the floating gate FG is formed through a word line WL crossing the assist gate.

2A is a plan view illustrating a flash memory device having an assist gate according to the related art.

FIG. 2B is a cross-sectional view taken along the line X-X 'of FIG. 2A.

FIG. 2C is a cross-sectional view taken along the line Y-Y 'of FIG. 2A.

FIG. 2D is a cross-sectional view along the line Y1-Y1 'of FIG. 2A.

2A to 2D, assist gates G crossing the semiconductor substrate 110 are disposed on the semiconductor substrate 110. The assist gates G may include a gate insulating layer pattern 130, a polysilicon pattern 133, and a tungsten silicide pattern 135 that are sequentially stacked. Gate spacers 137 covering upper portions of the assist gates G and sidewalls are disposed. A high concentration source / drain region 140 is disposed in the semiconductor substrate on one side of the assist gates G.

Tunnel oxide layer patterns 142 covering the semiconductor substrate 110 between the neighboring assist gates G are disposed. Conformed floating gate patterns 145 covering sidewalls of the neighboring gate spacers 137 and the tunnel oxide layer patterns 142 are disposed. Conformed dielectric layer patterns 150 are disposed on the floating gate patterns 145. The dielectric layer patterns 150 and the floating gate patterns 145 may be uniformly spaced on the semiconductor substrate 110 between the neighboring assist gates G as shown in FIGS. 2A and 2D. Is placed. Control gate patterns 152 and conductive layer patterns 155 may be disposed to cover the dielectric layer patterns 150 and cross the upper portions of the assist gates G. Referring to FIG.

However, as the integration of devices increases recently, the channel length of the MOSFET is shortened, which increases I _off due to the short channel effect, and the channel width of the MOSFET decreases, which results in a decrease in I _on and a decrease in I _on / I _off ratio. Margin is getting smaller. This causes a malfunction of the device. In addition, as the device shrinks, the coupling ratio, which determines the rate at which the voltage applied to the gate is applied to the channel, becomes smaller, requiring a higher gate voltage to be applied for program / erase operation. The problem is that the amount of current is reduced by reducing the voltage felt by the region.

Therefore, there is a need for research to improve I _on / I _off ratio and coupling ratio while increasing the programming speed using assist gate.

The technical problem to be achieved by the present invention is to provide a pin-pet structure that can improve the I _on / I _off ratio and coupling ratio while increasing the programming speed by performing the program by the CHE method with an integration similar to NAND using an assist gate. It is to provide a flash memory device and a method of manufacturing the same.

Embodiments of the present invention provide a flash memory device having a finpet structure. The flash memory device includes a fin active region crossing a semiconductor substrate. Assist gates are disposed across the active region of the fin structure. Gate spacers are disposed to cover the upper and sidewalls of the assist gates. A conformal tunnel oxide film is disposed between the neighboring assist gates to cover the active region of the fin structure. Conformed floating gate patterns covering sidewalls of the neighboring gate spacers and the tunnel oxide layer are disposed. Conformed dielectric layer patterns are disposed on the floating gate patterns. Control gate patterns are disposed on the assist gates to cover the dielectric layer patterns along the active region of the fin structure.

It is preferable that the edge of the fin structure of the active region of the fin structure is a smooth curved surface.

The assist gate may be a gate insulating layer pattern, a polysilicon pattern, and a tungsten silicide pattern that are sequentially stacked.

The gate spacers may be SiN material.

It may have a high concentration source / drain region in the semiconductor substrate on one side of the assist gates.

An oxide layer pattern may be further included between the active regions of the fin structure.

The dielectric film pattern is preferably an oxide-nitride-oxide (ONO) film.

Another embodiment of the present invention provides a method of manufacturing a flash memory device having a finpet structure. The method involves forming an active region of fin structure across the semiconductor substrate. The assist gates may be formed on the active region of the fin structure to cross the active regions of the fin structure and be parallel to each other. Gate spacers covering upper portions of the assist gates and sidewalls are formed. The semiconductor substrate having the gate spacers is thermally oxidized to form a tunnel oxide layer, and a conformal floating gate layer is formed on the tunnel oxide layer and sidewalls of the gate spacers. Subsequently, a conformal dielectric film is formed on the floating gate film, and a control gate film is formed on a semiconductor substrate having the dielectric film. Thereafter, the control gate layer, the dielectric layer, and the floating gate layer are sequentially patterned to cross the assist gates, and to include control gate patterns surrounding the active region of the fin structure, and the fin structure between the assist gates. Dielectric layer patterns and floating gate layer patterns surrounding the active region are formed.

Forming the fin active region may form a pad oxide film and a pad nitride film on the semiconductor substrate. Subsequently, the pad nitride layer and the pad oxide layer are patterned in order to form a pad nitride layer pattern and a pad oxide layer pattern that cross the semiconductor substrate. The semiconductor substrate is thermally oxidized to form a first thermal oxide film in the semiconductor substrate. The semiconductor substrate having the first thermal oxide film is etched back to form a trench in the semiconductor substrate. The semiconductor substrate having the trench is thermally oxidized to form a second thermal oxide film on the inner wall of the trench. An oxide layer is formed on the semiconductor substrate having the second thermal oxide layer to expose the upper surface of the pad nitride layer pattern while filling the trench. After the oxide film is wet-etched to form an oxide film pattern exposing an active region of a fin structure, the pad nitride film and the pad oxide film are removed. The oxide film may be formed of an HDP oxide film.

The assist gates may be formed of a gate insulating layer, a polysilicon pattern, and a tungsten silicide pattern, which are sequentially stacked.

The gate insulating layer, the polysilicon pattern, and the tungsten silicide pattern may be formed by thermally oxidizing a semiconductor substrate having the active region having the fin structure. A polysilicon film is formed on the semiconductor substrate having the gate insulating film. The polysilicon film is planarized, and a tungsten silicide film is formed on the planarized polysilicon film. The tungsten silicide layer and the polysilicon layer are patterned to form the polysilicon pattern and the tungsten silicide pattern crossing the active region of the fin structure.

After forming the gate spacers and before forming the tunnel oxide layer, further, forming a high concentration source / drain region by self-alignment by performing gradient ion implantation using the gate spacers on the semiconductor substrate having the gate spacers. It may include.

Forming the conformal floating gate layer on the tunnel oxide layer and the sidewalls of the gate spacers may include forming a conformal preliminary floating gate layer on the semiconductor substrate having the tunnel oxide layer. Subsequently, a sacrificial layer is formed on the preliminary floating gate layer. The sacrificial layer may be planarized to form a sacrificial layer pattern exposing the preliminary floating gate layer on the gate spacer. Etching the exposed preliminary floating gate layer to expose the upper portion of the gate spacer, a floating gate layer having the same height as the sacrificial layer pattern is formed. Thereafter, the sacrificial layer pattern is removed by wet etching.

It is preferable to form the edge of the fin structure of the fin structure active region in a smooth curved surface.

The gate spacers may be formed of SiN material.

The dielectric layer pattern may be formed of an oxide-nitride-oxide (ONO) layer.

The method may further include forming a control gate film on the semiconductor substrate having the dielectric film and then forming a conductive film on the semiconductor substrate having the control gate film.

The conductive layer, the control gate layer, the dielectric layer, and the floating gate layer are sequentially patterned to cross the assist gates, and to include conductive layer patterns and control gate patterns surrounding the active region of the fin structure, and the assist gates. Dielectric layer patterns and floating gate layer patterns surrounding the active region of the fin structure may be formed therebetween.

The conductive film is preferably formed of a tungsten silicide film.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided as examples to sufficiently convey the spirit of the present invention to those skilled in the art. Accordingly, the invention is not limited to the embodiments described below and may be embodied in other forms. In the drawings, lengths, thicknesses, and the like of layers and regions may be exaggerated for convenience of description. Like numbers refer to like elements throughout.

3A to 3E are cross-sectional views of a method of manufacturing an active region of a fin structure according to an embodiment of the present invention.

Referring to FIG. 3A, a pad oxide film is formed on the semiconductor substrate 10. A pad nitride film is formed on the pad oxide film. Subsequently, the pad nitride layer and the pad oxide layer are patterned to form pad nitride layer patterns 15 and pad oxide layer patterns 12 having a fin structure width.

Referring to FIG. 3B, a semiconductor substrate having the pad nitride layer patterns 15 is thermally oxidized to form a first thermal oxide layer 17 in an exposed semiconductor substrate between the patterns. The first thermal oxide layer 17 penetrates the lower edges of the pad oxide layer patterns 12.

Referring to FIG. 3C, the semiconductor substrate having the first thermal oxide film 17 is etched back. As a result, a trench 20 is formed in the semiconductor substrate 10. Thereafter, the semiconductor substrate having the trench 20 is thermally oxidized. By the thermal oxidation, a second thermal oxide film 22 is formed on the inner wall of the trench 20. The purpose of the thermal oxidation is performed to mitigate damage to the trench inner wall by the etch back process.

Referring to FIG. 3D, an oxide film 25 is formed on a semiconductor substrate having the trench 20. The oxide layer 25 is planarized to expose upper portions of the pad nitride layer patterns 15. The oxide layer 25 may be formed of a high density plasma (HDP) oxide layer.

Referring to FIG. 3E, the semiconductor substrate having the oxide layer 25 is wet-etched to etch the oxide layer 25 to a predetermined thickness to form an oxide layer pattern 25a. Accordingly, the active region A having a fin structure is formed in the semiconductor substrate 10. At this time, the remaining first thermal oxide layer 17 formed by penetrating the lower edges of the pad oxide layer patterns 12 is simultaneously removed. Thereafter, the pad nitride film pattern 15 and the pad oxide film pattern 12 are removed. An edge portion of the active region A of the fin structure may be curved by the first thermal oxide layer 17 formed by penetrating the lower edges of the pad oxide layer patterns 12.

4A to 11A, 4B to 11B, 4C to 11C, and 7D to 11D illustrate a method of manufacturing a flash memory device having a finpet structure according to an embodiment of the present invention.

4A to 11A are plan views illustrating a method of manufacturing a flash memory device having a finpet structure according to an embodiment of the present invention.

4B through 11B are cross-sectional views taken along the lines X-X 'of FIGS. 4A through 11A, respectively.

4C through 11C are cross-sectional views taken along the line Y-Y 'of FIGS. 4A through 11A, respectively.

7D through 11D are cross-sectional views taken along lines Y 1 -Y 1 ′ of FIGS. 7A through 11A, respectively.

4A to 4C, a semiconductor substrate 10 having a fin structured active region A formed through the manufacturing method of FIGS. 3A to 3E is prepared. In the semiconductor substrate 10, a trench 20 is formed between the active regions A of the fin structure, and an oxide layer pattern 25a filling the bottom of the trench is formed in the trench 20. A second thermal oxide film 22 is formed between the oxide film pattern 25a and the semiconductor substrate 10. The semiconductor substrate 10 having the active region A having the fin structure is heat-treated to form a gate insulating layer 30 on the semiconductor substrate 10. A polysilicon film 33 is formed on the semiconductor substrate having the gate insulating film 30. The polysilicon film 33 is planarized. A tungsten silicide layer 35 is formed on the planarized polysilicon layer 33.

5A through 5C, the tungsten silicide layer 35 and the polysilicon layer 33 are patterned to cross the tungsten silicide patterns 35a and the polysilicon patterns across the active region A of the fin structure. 33a is formed. In this case, the gate insulating layer 30 may be patterned together to form a gate insulating layer pattern 30a. The gate insulating layer pattern 30a, the polysilicon pattern 33a, and the tungsten silicide pattern 35a constitute an assist gate AG. Subsequently, a gate spacer 37 surrounding upper and sidewalls of the assist gate AG is formed. The gate spacer 37 may be a SiN material.

6A to 6C, gradient ion implantation is performed in the semiconductor substrate 10. In this case, a high concentration source / drain region 40 may be formed by using the assist gate AG and the gate spacer 37. The high concentration source / drain region 40 is formed in the semiconductor substrate under one side of the assist gate AG.

7A to 7D, a tunnel oxide film 42 is formed on the semiconductor substrate by heat treating the semiconductor substrate having the high concentration source / drain region 40. A conformal preliminary floating gate film 45 is formed on the semiconductor substrate having the tunnel oxide film 42. The preliminary floating gate layer 45 may be formed of polysilicon. A sacrificial layer 47 is formed on the preliminary floating gate layer 45. The sacrificial layer 47 may be formed of borophosphate silicate glass (BPSG).

8A through 8D, the sacrificial layer 47 is planarized lower than the assist gate AG to expose the preliminary floating gate layer 45 on the gate spacer 37. ). Next, the preliminary floating gate layer 45 is etched back to form a floating gate layer 45a exposing the upper portion of the gate spacer 37.

9A to 9D, the sacrificial layer pattern 47a is removed to expose the floating gate layer 45a. A conformal dielectric film 50 is formed on the exposed floating gate film 45a. The dielectric layer 50 may be formed of an oxide-nitride-oxide (ONO) layer. The area of the dielectric film 50 is formed three-dimensionally by the assist gate AG. Therefore, the vertical portions B of the dielectric film 50 are portions increased by the assist gate AG. In addition, the vertical portions (B) are increased along the sidewall of the fin by the active region (A) of the fin structure to include an increase in the sidewall portion compared to the active region of the planar structure. Therefore, the capacitance of the dielectric film 50 is increased to increase the coupling ratio of the flash memory device to be manufactured later. In the conventional finpet flash structure, a problem arises in that the erase voltage increases due to the reduction of the coupling ratio. However, by applying the assist gate (AG) structure and the finpet structure simultaneously, this problem can be solved and the coupling ratio can be increased. .

10A to 10D, the control gate film 52 is formed on the semiconductor substrate having the dielectric film 50 and then planarized by a planarization process. The control gate layer 52 may be a polysilicon layer. A conductive film 55 is formed on the control gate film 52. The conductive layer 55 may be formed of a tungsten silicide layer.

11A to 11D, the conductive layer 55, the control gate layer 52, the dielectric layer 50, and the floating gate layer 45a are sequentially patterned to form conductive layer patterns 55a and control gate patterns. 52a, dielectric layer patterns 50a and floating gate patterns 45b are formed. The conductive layer patterns 55a and the control gate patterns 52a may be formed to cross the assist gates AG and surround the active region A of the fin structure. In addition, the dielectric layer patterns 50a and the floating gate patterns 45b are formed to surround the active region A of the fin structure between the assist gates AG.

The flash memory device manufactured as described above is formed in a structure in which the gate of the transistor surrounds three surfaces of the fin by forming the transistor element in a fin structure instead of a planar structure. Accordingly, it is possible to reduce the I _off by about 10 times by improving the gate channel controllability. In addition, the fin structure increases I _on about three times as the channel width increases up to the side walls. Accordingly, the I _on / I _off ratio is increased to increase the sensing margin width, thereby improving the performance of the device. In addition, as the I _on increases, the absolute amount of CHE increases during programming, thereby improving programming speed by comparing the assist gate in the prior art with a flash memory device.

11A to 11D, a flash memory device according to an exemplary embodiment of the present invention will be described.

11A through 11D, an active region A having a fin structure crossing the semiconductor substrate is disposed on the semiconductor substrate 10. An edge of the fin structure of the active region A of the fin structure may be a smooth curved surface. The trench 20 is disposed between the active regions A of the fin structure, and the oxide layer pattern 25a filling the bottom of the trench is disposed in the trench 20. In addition, a second thermal oxide layer 22 is disposed between the oxide layer pattern 25a and the semiconductor substrate 10.

Assist gates AG are disposed across the active region A of the fin structure. The assist gates AG may include a gate insulating layer pattern 30a, a polysilicon pattern 33a, and a tungsten silicide pattern 35a that are sequentially stacked. Gate spacers 37 are disposed on the upper and sidewalls of the assist gates AG. The gate spacers 37 may be SiN material. A high concentration source / drain region 40 may be disposed in the semiconductor substrate on one side of the assist gates AG.

A conformal tunnel oxide layer 42 covering the fin active region A is disposed between the neighboring assist gates AG. Conformed floating gate patterns 45b covering sidewalls of the neighboring gate spacers 37 and the tunnel oxide layer 42 are disposed. The floating gate patterns 45b may be polysilicon material. Conformed dielectric layer patterns 50a are disposed on the floating gate patterns 45b. The dielectric layer patterns 50a may be oxide-nitride-oxide (ONO). The dielectric layer patterns 50a and the floating gate patterns 45b may be uniformly spaced on the semiconductor substrate 10 between the neighboring assist gates AG as shown in FIGS. 11A and 11D. Is placed. Control gate patterns 52a and conductive layer patterns 55a are disposed across the assist gates AG to cover the dielectric layer patterns 50a along the active region A of the fin structure. . The control gate patterns 52a may be polysilicon material. The conductive layer patterns 55a may be tungsten silicide material.

The present invention made as described above has a programming speed in comparison with a conventional assist gate AND flash memory device by incorporating a pin-pet structure into an assist gate AND flash memory device that performs programming according to the CHE method while having a density similar to that of NAND. In addition, the I _on / I _off ratio and coupling ratio of the device can be further improved to implement a high performance flash memory device.

1 is a schematic diagram illustrating a programming principle of a flash memory device having an assist gate according to the related art.

2A is a plan view illustrating a flash memory device having an assist gate according to the related art.

FIG. 2B is a cross-sectional view taken along the line X-X 'of FIG. 2A.

FIG. 2C is a cross-sectional view taken along the line Y-Y 'of FIG. 2A.

FIG. 2D is a cross-sectional view along the line Y1-Y1 'of FIG. 2A.

3A to 3E are cross-sectional views of a method for manufacturing an active region of a finpet structure according to an embodiment of the present invention.

4A to 11A are plan views illustrating a method of manufacturing a flash memory device having a finpet structure according to an embodiment of the present invention.

4B through 11B are cross-sectional views taken along the lines X-X 'of FIGS. 4A through 11A, respectively.

4C through 11C are cross-sectional views taken along the line Y-Y 'of FIGS. 4A through 11A, respectively.

7D through 11D are cross-sectional views taken along lines Y 1 -Y 1 ′ of FIGS. 7A through 11A, respectively.

Claims (20)

Semiconductor substrates; An active region having a fin structure crossing the semiconductor substrate; Assist gates crossing the active region of the fin structure; Gate spacers covering upper portions of the assist gates and sidewalls; A conformal tunnel oxide film covering an active region of the fin structure between the neighboring assist gates; Conformal floating gate patterns covering sidewalls of the neighboring gate spacers and the tunnel oxide layer; Conformal dielectric layer patterns disposed on the floating gate patterns; And control gate patterns crossing the assist gates while covering the dielectric layer patterns along the active region of the fin structure. The method of claim 1, And the edge of the fin structure of the active region of the fin structure is a smooth curved surface. The method of claim 1, And the assist gate is a gate insulating layer pattern, a polysilicon pattern, and a tungsten silicide pattern, which are sequentially stacked. The method of claim 1, And the gate spacers are SiN material. The method of claim 1, And a high concentration source / drain region in the semiconductor substrate on one side of the assist gates. The method of claim 1, And an oxide layer pattern between the active regions of the fin structure. The method of claim 1, The dielectric film pattern is a flash memory device, characterized in that the oxide-nitride-oxide (ONO) film. Forming an active region of a fin structure across the semiconductor substrate, Crossing the active region of the fin structure on the active region of the fin structure, forming assist gates parallel to each other; Gate spacers covering upper portions of the assist gates and sidewalls, Thermally oxidizing the semiconductor substrate having the gate spacers to form a tunnel oxide film, Forming a conforming floating gate film on sidewalls of the tunnel oxide film and the gate spacers, Forming a conformal dielectric film on the floating gate film, Forming a control gate film on the semiconductor substrate having the dielectric film, Patterning the control gate layer, the dielectric layer, and the floating gate layer in order to traverse the assist gates, the control gate patterns surrounding the active region of the fin structure, and the active region of the fin structure between the assist gates. A method of manufacturing a flash memory device comprising forming dielectric layer patterns and floating gate layer patterns surrounding the dielectric layer. The method of claim 8, Forming the active region of the fin structure, Forming a pad oxide film and a pad nitride film on the semiconductor substrate, Patterning the pad nitride film and the pad oxide film in sequence to form a pad nitride film pattern and a pad oxide film pattern crossing the semiconductor substrate; Thermally oxidizing the semiconductor substrate to form a first thermal oxide film in the semiconductor substrate; Forming a trench in the semiconductor substrate by etching back the semiconductor substrate having the first thermal oxide film; Thermally oxidizing the semiconductor substrate having the trench to form a second thermal oxide film on the inner wall of the trench, Forming an oxide film exposing the upper surface of the pad nitride film pattern while filling the trench on the semiconductor substrate having the second thermal oxide film, Wet etching the oxide film to form an oxide pattern to expose the active region of the fin structure, And removing the pad nitride film and the pad oxide film. The method of claim 9, And the oxide film is formed of an HDP oxide film. The method of claim 8, And the assist gates are formed of a gate insulating layer, a polysilicon pattern, and a tungsten silicide pattern, which are sequentially stacked. The method of claim 11, Forming the gate insulating film, polysilicon pattern and tungsten silicide pattern, Thermally oxidizing a semiconductor substrate having the fin-type active region to form a gate insulating film, Forming a polysilicon film on the semiconductor substrate having the gate insulating film, Planarize the polysilicon film, Forming a tungsten silicide film on the planarized polysilicon film, And patterning the tungsten silicide layer and the polysilicon layer to form the polysilicon pattern and the tungsten silicide pattern across the active region of the fin structure. The method of claim 8, After forming the gate spacers and before forming the tunnel oxide layer, And inclining ion implantation using the gate spacers on the semiconductor substrate having the gate spacers to form a high concentration source / drain region by self-alignment. The method of claim 8, Forming a conforming floating gate film on sidewalls of the tunnel oxide film and the gate spacers, Forming a conformal preliminary floating gate film on the semiconductor substrate having the tunnel oxide film; Forming a sacrificial layer on the preliminary floating gate layer, Planarizing the sacrificial layer to form a sacrificial layer pattern exposing the preliminary floating gate layer on the gate spacer; Etching the exposed preliminary floating gate layer to expose an upper portion of the gate spacer to form a floating gate layer having the same height as the sacrificial layer pattern, The method of claim 1, wherein the sacrificial layer pattern is removed by wet etching. The method of claim 8, And forming a smooth curved edge of the fin structure of the fin structure active region. The method of claim 8, The gate spacers are formed of SiN material. The method of claim 8, The dielectric layer pattern is formed of an oxide-nitride-oxide (ONO) film flash memory device manufacturing method characterized in that formed. The method of claim 8, After the control gate film is formed on the semiconductor substrate having the dielectric film, And forming a conductive film on the semiconductor substrate having the control gate film. The method of claim 18, The conductive layer, the control gate layer, the dielectric layer, and the floating gate layer may be sequentially patterned to cross the assist gates, and may include conductive layer patterns and control gate patterns surrounding the active region of the fin structure, and the assist gates. And forming dielectric layer patterns and floating gate layer patterns surrounding the active region of the fin structure therebetween. The method of claim 18, And the conductive film is formed of a tungsten silicide film.