KR20010065022A - Cell structure of flash memory and method of forming thereof - Google Patents

Abstract

PURPOSE: A cell structure of a flash memory device is provided to improve an erase speed and to control over-erase, by forming a floating gate of a concave groove structure by an improved stack-type cell structure, and by forming an insulation layer between gates and a control gate inside the groove. CONSTITUTION: A tunnel oxide layer is formed on an active region of a semiconductor substrate(100). A floating gate of a concave groove structure is formed on the tunnel oxide layer. A thin insulation layer(104) between gates is formed inside the concave groove of the floating gate. A control gate is filled in the groove on the insulation layer between the gates. Source/drain regions(120a,120b) are separated in the surface of the substrate, formed at both sides of a channel under the tunnel oxide layer.

Description

Cell structure of flash memory device and manufacturing method thereof {Cell structure of flash memory and method of forming}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a cell structure of a flash memory device capable of improving the reliability of an erase operation and a method of manufacturing the same.

In general, nonvolatile flash memory devices have the advantage that the stored data is not lost even when the power is interrupted. They are widely used for data storage such as PC Bios, Set-top Box, printers and network servers. It is also used in many mobile phones.

FIG. 1 is a cross-sectional view showing a stacked cell structure of a conventional flash memory device, in which the field oxide film 12 formed on the silicon substrate 10 as a semiconductor substrate and the activity of the substrate exposed by the field oxide film 12 are shown. There is a tunnel oxide film 14 formed in the region, and a stacked gate electrode G including a floating gate 16, an inter-gate insulating film 18, and a control gate 20 sequentially stacked thereon. The flash memory cell includes source / drain regions 22a and 22b in which conductive impurities are implanted into the substrate between the gate electrode G and the field oxide film 12.

A flash memory device having a cell having a stacked gate structure as described above applies a predetermined voltage to the control gate 20 to inject electrons from the drain 22b to the floating gate 16 to perform a programming operation. Erasing is performed by emitting electrons injected into the floating gate 16 under the substrate to lower the threshold voltage.

Since the stacked flash memory performs a batch erasing scheme in units of sectors or blocks, when a few slow bits exist, the threshold voltage of a cell that has been normally erased due to the slow bits has a value of 0V or less. (over erase) will cause a serious error.

In addition, the cell of the stacked gate structure is programmed by hot-carrier injection through the tunnel oxide film in the drain region 22b and erased back to the channel through the tunnel oxide film, thereby increasing the stress on the tunnel oxide film.

Meanwhile, according to a high integration trend, a flash memory device improves a selection transistor for selecting cells of a specific column or row among a plurality of memory cells into a split gate structure integrating a control gate of the memory cell. This increased the integration of the memory device.

FIG. 2 is a cross-sectional view illustrating a split gate type cell structure of a conventional flash memory device. Referring to this, a unit cell of a flash memory includes a field oxide film 32 formed on a silicon substrate 30 and the field oxide film ( A tunnel oxide film 34 formed in an active region of the substrate between the substrate 32, a floating gate 36 thereon, a control and selection gate 40 partially overlapping the sides and top of the floating gate 36, and An inter-gate insulating film 38 which insulates the control and selection gate 40 and the floating gate 36, a source region 42a formed in the substrate between the edge of the floating gate 36 and the field oxide film 32, and And a drain region 42b formed in the substrate between the edge of the select gate 40 and the field oxide film 32.

As such, the split gate type cell is programmed through the tunnel oxide film 34 in the source region 42b and applied to the tunnel oxide film 34 by erasing it toward the control gate 40 through the inter-gate insulating film 38. It has the advantage of reducing stress and mitigating the problem of over-erasing.

However, since the erase operation is performed through the relatively thick inter-gate insulating film 38, the speed is slow. There is a limitation in manufacturing a cell array having a high density due to the large cell area.

An object of the present invention is to solve the above problems of the prior art, the floating gate has a concave groove shape by the improved stacked cell structure and programming by forming an inter-gate insulating film and a control gate in the groove The present invention provides a cell structure of a flash memory device and a method of manufacturing the same, which are performed between the drain and the floating, and an erase operation is performed between the floating and control gates to improve the erase speed and suppress over erasure.

1 is a cross-sectional view showing a stacked cell structure of a conventional flash memory device;

2 is a cross-sectional view showing a split gate type cell structure of a conventional flash memory device;

3 is a cross-sectional view showing an improved stacked cell structure of a flash memory device according to the present invention;

4A-4H are process flow diagrams for forming a stacked cell of a flash memory device according to the present invention.

Explanation of symbols on the main parts of the drawings

100 silicon substrate 102 field oxide film

104: insulating film 105: tunnel oxide film

106,114,116: photoresist pattern

108: first conductor 108 ': floating gate

110,110 ': inter-gate insulating film 112,112': control gate

In order to achieve the above object, the present invention provides a cell structure of a flash memory, comprising: a tunnel oxide film formed on an active region of a semiconductor substrate, a floating gate formed in a groove structure on the tunnel oxide film, and a gate formed thinly in the groove of the floating gate. An interlayer insulating film, a control gate filling a groove in an upper gate insulating film, and a source / drain region spaced apart from each other in a substrate surface with a channel under the tunnel oxide film interposed therebetween.

In the cell of the flash memory device of the present invention, the programming operation of the cell writes data to the floating gate in the drain region. On the other hand, the erase operation of the cell erases data from the floating gate to the control gate, but mainly on the sidewall between the floating gate and the control gate.

In order to achieve the above object, the present invention provides a method of manufacturing a cell of a flash memory, the method comprising: forming a field oxide film defining an active region and an inactive region of a device on a semiconductor substrate, depositing an insulating film on the substrate, and Forming a tunnel oxide film over the semiconductor substrate by etching the insulating film in a groove shape so that an insulating film having a predetermined thickness remains in the region, and sequentially laminating a first conductive film, an inter-gate insulating film, and a second conductive film on the entire surface of the insulating film; Patterning the second conductive film and the inter-gate insulating film to form a control gate, and patterning the inter-gate insulating film to form a shape surrounding the side of the control gate, and patterning the first conductive film to form a shape surrounding the inter-gate insulating film. Forming a floating gate having a recess structure, and self-aligning the floating gate edge And patterning the insulating film to, and forming a floating gate edge and spaced apart from each other the source / drain regions in the substrate surface between the field oxide film.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a cross-sectional view showing an improved stacked cell structure of a flash memory device according to the present invention, which is a field oxide film 102 formed on a silicon substrate 100 as a semiconductor substrate and a substrate between the field oxide film 102. A tunnel oxide film 104 formed in the active region, a floating gate 108 'formed with a recess structure on the tunnel oxide film 104, an inter-gate insulating film 110' thinly formed inside the recess of the floating gate 108, A control gate 112 'filling the groove on the inter-gate insulating film 110', and source / drain regions 120a and 120b spaced apart from each other in the substrate surface with the channel under the tunnel oxide film 104 interposed therebetween. .

In the cell of the flash memory device of the present invention having the structure described above, electrons in the drain region 120b are injected into the floating gate 108 'through the tunnel oxide film 104 to write data during the programming operation p. .

In addition, in the erase operation (e) of the cell, the injected electrons of the floating gate 108 ′ move to the control gate 112 ′ through the inter-gate insulating layer 110 ′ to erase the data. At this time, the movement of electrons in the erase operation is mainly performed at the sidewall between the floating gate 108 'and the control gate 112'.

Since the stacked gate cell structure of the flash memory device has a floating gate 108 'surrounding the control gate 112', the programming operation is the same as a conventional stacked cell structure, but the erase operation is controlled at the floating gate. Is done at the gate. Therefore, the present invention can reduce the stress on the tunnel oxide during programming and erasing, and since the erasing method adopts the same method as that of the split structure cell, it is possible to prevent over erasure due to the batch erasing, thereby improving the erasing rate. You can. In addition, since the stacked cell structure is maintained as it is, an extra area occupied by the cell is not required, thereby solving the problem of increasing cell density.

4A to 4H are process flowcharts for forming a stacked cell of a flash memory device according to the present invention. Referring to this, the improved method for manufacturing a stacked cell is as follows.

First, as shown in FIG. 4A, a field oxide film 102 defining an active region and an inactive region of an element is formed on a silicon substrate 100 as a semiconductor substrate, and an oxide is deposited as an insulating film 104 on the entire surface of the substrate. do. A photo process is performed to form a photoresist pattern 106 for forming a tunnel oxide layer on the insulating layer 104.

Next, as illustrated in FIG. 4B, the insulating film 104 is etched in the form of the recess 107 so that the insulating film 104 of a predetermined thickness remains in the active region of the substrate exposed by the photoresist pattern 106. A tunnel oxide film 105 having Wg) is formed, and the photoresist pattern 106 is removed.

Next, as shown in FIGS. 4C and 4D, doped polysilicon is deposited as the first conductive film 108 on the entire surface of the substrate on which the tunnel oxide film 105 is formed. Then, an oxide-nitride-oxide (ONO) as the inter-gate insulating film 110 and a doped polysilicon are sequentially stacked as the second conductive film 112.

Next, as shown in FIG. 4E, the photoconductive process using the control gate mask is performed to form the photoresist pattern 116 on the resultant, and then the second conductive film 112 and the inter-gate insulating film (etched) are etched. The 110 is patterned to form the control gate 112 '. In this case, the patterned inter-gate insulating layer 110 is formed to surround the side of the control gate 112 ′. Then, the photoresist pattern 116 is removed.

As shown in FIG. 4F, a photoresist pattern 118 is formed on the resultant by performing a photolithography process using a floating gate mask, and the first conductive layer is patterned by an etching process to form a floating gate 108 ′. do. In this case, the floating gate 108 ′ has a shape surrounding the remaining inter-gate insulating layer 110 ′ and has a concave groove structure as a whole. Then, the photoresist pattern 118 is removed.

Next, as shown in FIG. 4G, the remaining insulating film 104 is patterned using the patterned control gate 112 ′, the inter-gate insulating film 110 ′, and the floating gate 108 ′ as a mask. Then, the tunnel oxide film 105 self-aligned to the floating gate 108 ′ remains on the substrate. In this case, the insulating film 104 may be removed using the photoresist pattern 118.

Then, as shown in FIG. 4H, a source / drain region 120a spaced apart from each other in the substrate surface exposed between the floating gate 108 ′ edge and the field oxide film 102 by performing a conventional conductive impurity ion implantation process. 120b) to complete the manufacturing process of the flash memory cell according to the present invention.

As described above, the present invention is a stack cell structure in which a floating gate surrounds an inter-gate insulating film and a control gate, so that programming is performed in the same manner as a conventional stacked cell, a floating gate at a drain, and a general split is erased. As with the gated cell, it is made between the floating gate and the control gate.

Therefore, the present invention can solve the problem of over-erasing of the cell structure of the stack gate and stress of the tunnel oxide film.

In addition, in the present invention, the erase operation is performed through a relatively thin inter-gate insulating film, compared to the split gate type cell structure, and the erase speed can be improved by the increased contact area between the floating gate and the control gate. Because of the stacked cell structure, a cell array of high density can be manufactured.

Claims (5)

In the cell structure of a flash memory, A tunnel oxide film formed over the active region of the semiconductor substrate; A floating gate having a recess structure on the tunnel oxide layer; An inter-gate insulating film thinly formed inside the recess of the floating gate; A control gate filling the groove on the inter-gate insulating layer; And And a source / drain region spaced apart from each other in the substrate surface with the channel under the tunnel oxide layer interposed therebetween. The cell structure of claim 1, wherein the programming operation of the cell writes data to a floating gate in a drain region. The cell structure of claim 1, wherein the erasing operation of the cell erases data from a floating gate to a control gate. 2. The cell structure of a flash memory device according to claim 1, wherein the erasing operation of the cell is mainly performed at the sidewall between the floating gate and the control gate. In the cell manufacturing method of the flash memory, Forming a field oxide film on the semiconductor substrate, the field oxide film defining an active region and an inactive region of the device; Depositing an insulating film on the substrate, and etching the insulating film into a groove shape so that an insulating film having a predetermined thickness remains in an active region of the substrate to form a tunnel oxide film on the semiconductor substrate; Sequentially stacking a first conductive film, an inter-gate insulating film, and a second conductive film on the entire insulating film; Patterning the second conductive film and the inter-gate insulating film to form a control gate, and patterning the inter-gate insulating film to form a shape surrounding the side of the control gate; Patterning a first conductive layer so as to surround the inter-gate insulating layer to form a floating gate having a recess structure; Patterning the insulating film to self-align to the floating gate edge; And Forming a source / drain region spaced apart from each other in the substrate surface between the floating gate edge and the field oxide layer.