KR101150756B1 - method for manufacturing semiconductor device - Google Patents
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- KR101150756B1 KR101150756B1 KR1020040096231A KR20040096231A KR101150756B1 KR 101150756 B1 KR101150756 B1 KR 101150756B1 KR 1020040096231 A KR1020040096231 A KR 1020040096231A KR 20040096231 A KR20040096231 A KR 20040096231A KR 101150756 B1 KR101150756 B1 KR 101150756B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 238000000034 method Methods 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 29
- 229920005591 polysilicon Polymers 0.000 claims abstract description 29
- 125000006850 spacer group Chemical group 0.000 claims abstract description 18
- 150000004767 nitrides Chemical class 0.000 claims abstract description 16
- 229910052723 transition metal Inorganic materials 0.000 claims abstract description 16
- 150000003624 transition metals Chemical class 0.000 claims abstract description 16
- 238000010438 heat treatment Methods 0.000 claims abstract description 15
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 13
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 5
- 239000005300 metallic glass Substances 0.000 claims abstract description 4
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 230000004888 barrier function Effects 0.000 claims abstract description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical group [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- -1 spacer nitride Chemical class 0.000 description 4
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
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- Manufacturing & Machinery (AREA)
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Abstract
본 발명은 게이트의 면저항을 낮출 수 있는 반도체 소자의 제조방법을 개시한다. 개시된 본 발명은 반도체 기판 상에 게이트산화막과 폴리실리콘막 및 식각장벽용 질화막을 차례로 형성하는 단계; 상기 질화막 및 폴리실리콘막을 차례로 식각하여 상기 폴리실리콘막의 표면에 요홈을 형성하는 단계; 상기 질화막을 제거하는 단계; 상기 폴리실리콘막을 패터닝하여 표면에 요홈을 갖는 게이트를 형성하는 단계; 상기 게이트 양측벽에 스페이서를 형성하는 단계; 상기 스페이서를 포함한 게이트 양측의 기판 표면 내에 소오스/드레인 영역을 형성하는 단계; 상기 기판 전면 상에 전이금속막과 캡핑막을 차례로 형성하는 단계; 상기 기판 결과물을 1차 열처리하여 게이트 표면 및 소오스/드레인 영역의 표면 상에 비정질의 금속실리사이드막을 형성하는 단계; 상기 캡핑막 및 상기 1차 열처리시 미반응한 전이금속막을 제거하는 단계; 및 상기 기판 결과물을 2차 열처리하는 단계;를 포함한다.The present invention discloses a method of manufacturing a semiconductor device capable of lowering sheet resistance of a gate. The disclosed invention sequentially forms a gate oxide film, a polysilicon film, and an etch barrier nitride film on a semiconductor substrate; Etching the nitride film and the polysilicon film in order to form grooves on the surface of the polysilicon film; Removing the nitride film; Patterning the polysilicon film to form a gate having a groove on a surface thereof; Forming spacers on both sidewalls of the gate; Forming a source / drain region in the substrate surface on both sides of the gate including the spacer; Sequentially forming a transition metal film and a capping film on the entire surface of the substrate; First heat treating the substrate product to form an amorphous metal silicide film on a gate surface and a surface of a source / drain region; Removing the capping film and the unreacted transition metal film during the first heat treatment; And secondary heat treatment of the substrate resultant.
Description
도 1a 내지 도 1g는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도.1A to 1G are cross-sectional views of processes for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
11 : 기판 12 : 게이트 산화막11
13 : 게이트 폴리실리콘막 14 : 하드마스크 질화막13 gate
15a,15b : 감광막 16 : 게이트15a, 15b: photosensitive film 16: gate
17 : 스페이서 산화막 18 : 스페이서 질화막17
19 : 스페이서 20 : 소오스/드레인 영역19: spacer 20: source / drain region
21 : 전이금속막 22 : 캡핑막21: transition metal film 22: capping film
23 : 실리사이드 23: silicide
본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는, 게이트의 면저항을 낮출 수 있는 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device that can lower the sheet resistance of the gate.
반도체 소자가 고집적화, 소형화 및 고속화되어감에 따라, 트랜지스터의 게 이트로 더욱 낮은 저항을 갖는 도전성 물질을 필요로 하고 있으며, 또한, 접합부에서의 낮은 콘택 저항을 요구하고 있다. 최근들어 게이트의 저항을 낮추기 위한 하나의 방안으로 텅스텐이나 티타늄과 같은 전이 금속을 증착한 후 열처리하여 폴리실리콘막 상에 금속실리사이드가 형성된 폴리사이드 게이트를 적용하고 있다.As semiconductor devices become more integrated, smaller, and faster, a conductive material having a lower resistance as a gate of a transistor is required, and a lower contact resistance at a junction is required. Recently, as a way to lower the resistance of the gate, a polyside gate having a metal silicide formed on a polysilicon layer is applied by depositing a transition metal such as tungsten or titanium and heat treatment.
이하에서는 종래 폴리사이드 게이트를 갖는 반도체 소자의 제조방법을 간략하게 설명하도록 한다.Hereinafter, a manufacturing method of a semiconductor device having a conventional polyside gate will be briefly described.
먼저, 반도체 기판 상에 게이트 산화막과 게이트 폴리실리콘막을 형성하고, 이들을 패터닝하여 게이트를 형성한다. 그런다음, 상기 기판 결과물 전면 상에 산화막 또는 질화막 등의 절연체를 증착하고 이를 블랭킷 식각하여 게이트의 양측벽에 스페이서를 형성한다. 이어서, 상기 스페이서를 포함한 게이트의 양측 기판 내에 고농도로 불순물을 이온주입하여 소오스/드레인 영역을 형성한다. First, a gate oxide film and a gate polysilicon film are formed on a semiconductor substrate, and these are patterned to form a gate. Then, an insulator, such as an oxide film or a nitride film, is deposited on the entire surface of the substrate resultant and blanket-etched to form spacers on both side walls of the gate. Subsequently, impurities are ion-implanted at high concentration into both substrates of the gate including the spacer to form a source / drain region.
계속해서, 상기 기판 결과물 상에 전이 금속막을 증착한 후, 열처리를 진행하여 게이트 상부와 소오스/드레인 영역의 표면에 선택적으로 실리사이드를 형성한다. 여기서, 평탄한 게이트 위에 실리사이드가 형성되는데, 면저항을 감소시키기 위해서는 실리사이드 형성영역을 증가시켜야 하지만 이는 고집적화에 역행하는 것이므로 적용할 수 없다. 따라서, 게이트의 면저항을 감소시킴에 한계가 있다.Subsequently, after depositing a transition metal film on the substrate resultant, heat treatment is performed to selectively form silicide on the gate and the surface of the source / drain regions. Here, the silicide is formed on the planar gate, but in order to reduce the sheet resistance, the silicide forming region should be increased, but this is inverse to the high integration and thus cannot be applied. Therefore, there is a limit in reducing the sheet resistance of the gate.
따라서, 본 발명은 종래의 문제점을 해결하기 위해 안출된 것으로서, 게이트의 면저항을 낮추어 저전력 및 고속의 소자에 적용시킬 수 있는 반도체 소자의 제조 방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device that can be applied to low power and high speed devices by reducing the sheet resistance of a gate.
상기와 같은 목적을 달성하기 위한 본 발명은, 반도체 기판 상에 게이트산화막과 폴리실리콘막 및 식각장벽용 질화막을 차례로 형성하는 단계; 상기 질화막 및 폴리실리콘막을 차례로 식각하여 상기 폴리실리콘막의 표면에 요홈을 형성하는 단계; 상기 질화막을 제거하는 단계; 상기 폴리실리콘막을 패터닝하여 표면에 요홈을 갖는 게이트를 형성하는 단계; 상기 게이트 양측벽에 스페이서를 형성하는 단계; 상기 스페이서를 포함한 게이트 양측의 기판 표면 내에 소오스/드레인 영역을 형성하는 단계; 상기 기판 전면 상에 전이금속막과 캡핑막을 차례로 형성하는 단계; 상기 기판 결과물을 1차 열처리하여 게이트 표면 및 소오스/드레인 영역의 표면 상에 비정질의 금속실리사이드막을 형성하는 단계; 상기 캡핑막 및 상기 1차 열처리시 미반응한 전이금속막을 제거하는 단계; 및 상기 기판 결과물을 2차 열처리하는 단계;를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법을 제공한다.The present invention for achieving the above object, the step of sequentially forming a gate oxide film, a polysilicon film and an etching barrier nitride film on a semiconductor substrate; Etching the nitride film and the polysilicon film in order to form grooves on the surface of the polysilicon film; Removing the nitride film; Patterning the polysilicon film to form a gate having a groove on a surface thereof; Forming spacers on both sidewalls of the gate; Forming a source / drain region in the substrate surface on both sides of the gate including the spacer; Sequentially forming a transition metal film and a capping film on the entire surface of the substrate; First heat treating the substrate product to form an amorphous metal silicide film on a gate surface and a surface of a source / drain region; Removing the capping film and the unreacted transition metal film during the first heat treatment; And performing a second heat treatment on the resultant of the substrate.
본 발명의 다른 일면에 따라, 상기 폴리실리콘 게이트의 요홈은 십자형으로 형성한다.According to another aspect of the invention, the groove of the polysilicon gate is formed crosswise.
본 발명의 다른 일면에 따라, 상기 전이금속막은 코발트이고, 캡핑막은 티타늄질화막이다.According to another aspect of the invention, the transition metal film is cobalt, the capping film is a titanium nitride film.
본 발명의 또 다른 일면에 따라, 상기 1차 열처리는 급속열공정에 따라 450～500℃에서 수행하고, 상기 2차 열처리는 급속열공정에 따라 650～700℃에서 수행한다.According to another aspect of the invention, the first heat treatment is carried out at 450 ~ 500 ℃ according to the rapid heat process, the second heat treatment is carried out at 650 ~ 700 ℃ according to the rapid heat process.
(실시예) (Example)
이하, 첨부된 도면을 참조해서 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1g는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정 단면도로서, 이를 설명하면 다음과 같다.1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도 1a를 참조하면, 반도체 기판(11)을 열산화하여 게이트 산화막(12)을 23Å의 두께로 형성한다. 그런 다음, 상기 게이트 산화막(12) 상에 2000Å의 두께로 폴리실리콘막(13)을 형성한다. 이어서, 상기 폴리실리콘막(13) 상에 500Å의 두께로 하드마스크 질화막(14)을 형성한다. 여기서, 상기 게이트 폴리실리콘막(13)과 하드마스크 질화막(14)은 LP-CVD(low pressure-chemical vapor deposition), PE-CVD(plasma enhanced-CVD), HDP-CVD(high density plasma-CVD) 또는 AP-CVD(atmospheric pressure-CVD) 방식으로 형성한다. Referring to FIG. 1A, the
계속해서, 상기 하드마스크 질화막 상에 1800Å의 두께로 감광막(15a)을 도포한다.Subsequently, a
도 1b를 참조하면, 상기 감광막(15a)을 십자형 마스크(CROSS-SAL MASK)로 노광하고 현상하여 감광막 패턴(15a)을 형성한다. 그런 다음, 상기 감광막 패턴(15a)을 식각마스크로 하드마스크 질화막(14)을 식각한다. 도 2는 십자형 마스크의 평면도이다.Referring to FIG. 1B, the
도 1c를 참조하면, 상기 감광막 패턴(15a)을 애싱(ashing) 공정으로 제거한 후, 하드마스크 질화막(14)을 마스크로 게이트 폴리실리콘막(13)의 일부 두께를 식각하여 폴리실리콘막(13) 표면에 십자형의 요홈을 형성한다. 그런 다음, 상기 게이트 폴리실리콘막(13) 상에 감광막 도포, 노광, 현상공정을 거쳐 게이트 영역을 한정하는 감광막 패턴(15b)을 형성한다. Referring to FIG. 1C, after the
도 1d를 참조하면, 상기 감광막 패턴(15b)을 식각마스크로 게이트 폴리실리콘막(13)과 게이트 산화막(12)을 식각하여 표면에 요홈을 구비한 폴리실리콘 게이트(16)를 형성한다. 도 2는 도 1d의 A부분에 대한 확대 사시도로서, 요홈을 구비한 폴리실리콘 게이트(16)를 도시한 것이다.Referring to FIG. 1D, the
도 1e를 참조하면, 상기 기판 결과물 전면 상에 200Å의 두께로 스페이서 산화막(17)을 형성한다. 상기 스페이서 산화막(17)은 HTO(high temperature oxide), HLD(high temperature dielectric) 또는 LTO(low thermal oxide)방식으로 형성한다. 그런 다음, 상기 스페이서 산화막 상에 850Å의 두께로 스페이서 질화막(18)을 형성한다. 상기 스페이서 질화막(18)은 LP-CVD, PE-CVD, HDP-CVD 또는 AP-CVD 방식으로 증착한다. 이어서, 상기 스페이서 질화막(18)과 스페이서 산화막(17)을 블랭킷 식각하여 게이트(16)의 양측벽에 스페이서(19)를 형성한다.Referring to FIG. 1E, a
도 1f를 참조하면, 상기 스페이서(19)를 포함한 게이트(16) 양측의 기판(11) 표면 내에 불순물을 이온주입하여 소오스/드레인 영역(20)을 형성한다. 이어서, 상기 소오스/드레인 영역(20)이 형성된 기판(11) 전면 상에 스퍼터링을 이용한 PVD(physical vapor deposition) 방법으로 전이금속막(21)과 캡핑막(22)을 차례로 증착한다. 여기서, 상기 전이금속막(21)으로는 코발트를 사용하며, 캡핑막(22)으로는 티타늄질화막을 사용한다.Referring to FIG. 1F, impurities are implanted into the surface of the
도 1g를 참조하면, 상기 기판(11)을 450～500℃에서 1차열처리하여 표면에 요홈을 구비한 폴리실리콘 게이트(16) 및 소오스/드레인 영역(20)의 표면에 선택적으로 실리사이드(23)를 형성한 후, 미반응한 전이금속막(21)과 캡핑막(22)을 제거한다. 그런 다음 상기 기판 결과물을 650～700℃에서 2차열처리하여 실리사이드(23)를 결정화한다.Referring to FIG. 1G, the
이후, 공지된 일련의 후속공정들을 차례로 진행하여 본 발명에 따른 반도체 소자의 제조를 완성한다.Thereafter, a series of known successive processes are performed in order to complete the manufacture of the semiconductor device according to the present invention.
이상에서와 같이 본 발명은, 상기 게이트 폴리실리콘막 상부에 요홈을 형성하여 게이트 표면에 실리사이드 형성영역을 증가시킬 수 있다. 이에따라, 실리사이드 형성영역을 증가시킴으로써 게이트의 면저항을 감소시킬 수 있다. 또한, 본 발명은 게이트의 면저항을 감소시킬 수 있으므로, 저전력 및 고속 소자의 구현을 가능하게 할 수 있다.As described above, the present invention may increase the silicide formation region on the gate surface by forming a groove on the gate polysilicon layer. Accordingly, the sheet resistance of the gate can be reduced by increasing the silicide formation region. In addition, the present invention can reduce the sheet resistance of the gate, it is possible to implement a low power and high speed device.
본 발명을 특정의 바람직한 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니고 이하의 특허청구의 범위에 의해 마련되는 본 발명의 정신이나 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변화될 수 있다는 것을 당 업계에서 통상의 지식을 가진 자는 용이하게 알 수 있다.While the invention has been shown and described with respect to certain preferred embodiments thereof, the invention is not so limited and it is intended that the invention be limited without departing from the spirit or the scope of the invention as defined by the following claims. It will be readily apparent to one of ordinary skill in the art that various modifications and variations can be made.
Claims (7)
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990072018A (en) * | 1996-10-09 | 1999-09-27 | 야스카와 히데아키 | Thin film transistors and liquid crystal displays and electronic devices using them |
| KR20010065022A (en) * | 1999-12-20 | 2001-07-11 | 박종섭 | Cell structure of flash memory and method of forming thereof |
| KR20020058462A (en) * | 2000-12-30 | 2002-07-12 | 박종섭 | Test pattern for verification performance of semiconductror device |
| KR20030056910A (en) * | 2001-12-28 | 2003-07-04 | 주식회사 하이닉스반도체 | Method for forming salicide of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990072018A (en) * | 1996-10-09 | 1999-09-27 | 야스카와 히데아키 | Thin film transistors and liquid crystal displays and electronic devices using them |
| KR20010065022A (en) * | 1999-12-20 | 2001-07-11 | 박종섭 | Cell structure of flash memory and method of forming thereof |
| KR20020058462A (en) * | 2000-12-30 | 2002-07-12 | 박종섭 | Test pattern for verification performance of semiconductror device |
| KR20030056910A (en) * | 2001-12-28 | 2003-07-04 | 주식회사 하이닉스반도체 | Method for forming salicide of semiconductor device |
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