KR100571381B1 - Semiconductor element and manufacturing method thereof - Google Patents

Abstract

A method of manufacturing a semiconductor device according to the present invention includes sequentially forming an oxide film and a polysilicon layer on a semiconductor substrate on which an active region is defined, and then patterning the gate to form a gate, forming a spacer on the sidewall of the gate, Forming a source and drain region, forming a silicide metal layer by sputtering on the entire upper surface of the semiconductor substrate, forming a protective metal layer on the silicide metal layer and performing a first heat treatment to deposit the silicide on the gate, source and drain regions. Forming a side, forming a protective metal layer and a non-silicided silicide metal layer, and stabilizing the silicide by performing a second heat treatment on the substrate.

Resistance, cobalt, silicide

Description

Semiconductor device and method of manufacturing the same

1 is a cross-sectional view of a semiconductor device in accordance with an embodiment of the present invention.

2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention in the order of process.

The present invention relates to a semiconductor device and a manufacturing method thereof.

The performance of a transistor constituting a semiconductor device is closely related to the speed, drive current, and leakage current of the transistor. Therefore, in order to increase the speed of the transistor and reduce the leakage current, the resistance of the source and drain of the transistor, the resistance of the gate of the transistor, and the resistance of the contact portion must be small.

In order to reduce the resistance of this portion, silicide is formed at the interface between the drain and the source and the interface between the gate and the gate. The silicide is formed by depositing a metal such as titanium (Ti) or cobalt (Cobalt: Co) and then performing a rapid temperature process (RTP) to react the lower layer with the metal.

At this time, it is preferable to maintain a clean state free of impurities in the portion where the metal is deposited. When exposed to the air, a natural oxide film is formed at the interface of the semiconductor substrate. Thus, a number of cleanings are performed prior to depositing the metal, but the natural oxide film is not removed but often remains.

If the metal is deposited while the natural oxide film remains, silicide is not properly formed when the silicide is formed by heat treatment, and thus, the resistance of the drain, the source, and the gate portion increases, thereby preventing the semiconductor device from operating properly. have.

Accordingly, an object of the present invention for solving the above problems is to provide a semiconductor device stably formed silicide and a method of manufacturing the same.

According to an aspect of the present invention, there is provided a method of fabricating a semiconductor device, by sequentially forming an oxide film and a polysilicon layer on a semiconductor substrate on which an active region is defined, and then patterning the gate to form a gate, and forming a spacer on a sidewall of the gate. Forming a source and drain region in an active region, forming a silicide metal layer on a front surface of a semiconductor substrate by a sputtering method, forming a protective metal layer on the silicide metal layer and performing a first heat treatment to form a gate, Forming a silicide on the source and drain regions, forming a protective metal layer and an unsilicided silicide metal layer, and stabilizing the silicide by performing a second heat treatment on the substrate.

The method may further include forming a lightly doped region in the active region before forming the spacer on the sidewall of the gate. At this time, the silicide metal layer is preferably cobalt.

In addition, the protective metal layer is preferably any one of Ti, TiN, or Ti / TiN, and the deposition of the silicide metal layer by the sputtering method is preferably performed at a high energy in the range of 2 to 10 KW of DC power in the sputter.

In addition, it is preferable that the argon gas injected into the sputter when forming the silicide metal layer in the sputter is 40 to 70 sccm, and the heater argon gas is 8 to 15 sccm.

In addition, the first heat treatment is carried out for 10 to 60 seconds at 400 ~ 600 degrees by RTP method, the second heat treatment is preferably carried out for 10 to 60 seconds at 800 ~ 950 ℃ by RTP method.

In addition, the first heat treatment is performed for 20 to 60 minutes at 300 ~ 600 ℃ in the electric furnace, the second heat treatment is preferably performed for 20 to 60 minutes at 500 ~ 900 ℃ in the electric furnace.

In accordance with another aspect of the present invention, a semiconductor device includes a semiconductor substrate having an active region defined therein, a gate formed on a semiconductor substrate corresponding to a predetermined region of the active region, a spacer formed on sidewalls of the gate, and an active region. It includes a silicide formed on the source and drain regions formed on the semiconductor substrate of the gate, the gate, the source and drain regions, and deposited by a sputtering method and then heat treated.

It is preferable to further include a lightly doped region formed in the active region under the spacer. In addition, the silicide is preferably cobalt silicide.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is over another part, this includes not only the part directly above the other part but also another part in the middle. On the contrary, when a part is just above another part, it means that there is no other part in the middle.

It will now be described in detail with reference to the drawings with reference to embodiments of the present invention.

1 is a cross-sectional view of a semiconductor device according to the present invention.

As shown in FIG. 1, a device isolation region 12 defining an active region is formed in the semiconductor substrate 10. The gate oxide film 14 is formed on a part of the active region, and the gate 16 is formed on the gate oxide film 14.

Spacers 18 made of an insulating material are formed on sidewalls of the gate 16. The semiconductor substrate 10 of both the gate 16 and the spacer 18 has a source region 20 and a drain region 20 doped with n-type or p-type impurities at high concentration.

On top of gate 16 a silicide layer (hereinafter referred to as polyside to distinguish it from the silicide above source and drain regions) layer 20 is formed, where gate 16 and spacer 18 are not located. Silicides 22 are formed on the source and drain regions 19, respectively. The polyside layer 20 and silicide layer 22 reduce the contact resistance of the interface upon contact with a wiring which is subsequently formed of metal or polycrystalline silicon. The method of manufacturing the semiconductor device described above will be described in detail with reference to the accompanying drawings.

2A to 2F are diagrams illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention in the order of their processes.

First, as shown in FIG. 2A, a device isolation region 12 made of an insulating material formed by LOCOS (local oxidation of silicon, not shown) or shallow trench insulation (STI) is formed on the semiconductor substrate 10. do. The LOCOS method forms a device isolation region by partially growing an oxide film in a predetermined region of the substrate, and the STI method forms a device isolation region by filling a trench with an insulating material after forming a trench in a predetermined region of the substrate. .

As shown in FIG. 2B, an oxide film and a polycrystalline silicon layer are sequentially formed on the substrate 10, and then the polycrystalline silicon layer and the oxide film are sequentially patterned by a photolithography process using a mask to form the gate poly layer 16 and the gate oxide film ( The gates 14 and 16 made of 14 are formed.

As shown in FIG. 2C, silicon nitride (SiNx) is deposited on the entire surface of the substrate to cover the gates 14 and 16, and a nitride film is etched back to form a spacer 18 on the sidewall of the gate 16. Form.

As shown in Fig. 2D, an oxide film is formed on the entire surface of the substrate and then patterned to form a cap oxide film 17 for protecting the gates 14 and 16. Afterwards, the source region 19 and the drain region 19 are formed by doping conductive type impurity ions in the active region using the cap oxide layer 17 as a mask. In this case, the implanted ions are implanted with, for example, phosphorus (P) and boron (B) as n-type or p-type impurities. Although only the source region 19 and the drain region 19 are formed in the above, a light doped division (LDD) (not shown) may be formed before the formation of the spacer 18.

As shown in FIG. 2E, the cap oxide layer 17 is removed and washed by wet etching using an etchant such as SC1, HF, Dilute HF, and the like to remove impurities and natural oxide layers remaining on the substrate 10. SC1 is a mixture of hydrogen peroxide, ammonia and ultrapure water.

Subsequently, after wet cleaning, dry plasma etching using a cleaning gas such as CF 4 is performed to remove the remaining natural oxide film without being removed by wet cleaning. At this time, the removal of the natural oxide film removes the RF power of the substrate side of the plasma apparatus at 60 to 90 W and the chamber side RF power at 250 to 350 W.

As shown in FIG. 2F, the silicide metal layer 20A and the protective metal layer 24 are sequentially formed on the entire substrate 10. The silicide metal layer 20A may be formed by depositing cobalt, and the protective metal layer 24 may be formed by depositing Ti, TiN, Ti / TiN, or the like.

The silicide metal layer 20A is deposited by a sputtering method. When sputtering, DC power is preferably applied with a high energy in the range of 2 to 10 kW, and an injection amount of argon, which is an injection gas, is 40 to 70 sccm, to a heater. Argon, the gas used, should be injected at 8 to 15 sccm. As such, the gas injection amount is injected to the minimum amount that sputtering can occur to minimize collisions with cobalt atoms.

The injection gas is a gas that changes from the chamber into a plasma and directly participates in the reaction process in the chamber. And the gas used for the heater is a gas for transferring the heat of the heater to the substrate in a convection manner. The gas used for the heater is also plasmated in the chamber together with the injection gas to participate in the reaction process.

The use of such a high power increases the kinetic energy of the sputtered cobalt atoms, and even though the natural oxide film remains, the cobalt atoms penetrate the natural oxide film sufficiently to enter the upper portion of the substrate, that is, the source region 19, the drain region 19, and the gate 14, 16 is sufficiently laminated at the interface. At this time, the cobalt atoms have sufficient kinetic energy and the amount of argon plasma present in the chamber is small, so that the problem of ignition in which electrons collide in the sputter can be solved.

After that, the first heat treatment is performed to form the silicide layer 22 and the polyside layer 20 on the source and drain regions 19 and the gates 14 and 16, respectively. At this time, even though the natural oxide film remains, cobalt atoms are sufficiently stacked at the interface between the source region 19, the drain region 19, and the gate 16, so that silicides 20 and 22 are formed. Does not work as

In this case, the primary heat treatment may be a rapid heat treatment of RTP or general electric furnace heat treatment. Of these, when the heat treatment by the RTP method it is preferable to proceed for 10 to 60 seconds while maintaining the temperature in the range of 300 ~ 600 ℃. And when the heat treatment in the electric furnace, it is preferable to proceed for 20 to 60 minutes at a temperature of 300 ~ 600 ℃.

Next, as shown in FIG. 1, the silicide metal layer 20A and the protective metal layer 24 that are not silicided are removed. At this time, the metal layer is removed by etching the substrate for 5 to 15 minutes with the SPM solution of 50 ~ 150 ℃ and washed for 3 to 10 minutes in the SC1 solution to remove impurities generated during etching. The SPM solution is a solution in which hydrogen peroxide and sulfuric acid are mixed at a ratio of 1: 6.

After that, the secondary heat treatment is performed to stabilize the polyside 20 and the silicide 22. At this time, when the heat treatment by the RTP method it is preferable to proceed for 10 to 60 seconds while maintaining the temperature in the range of 800 ~ 950 ℃. And when the heat treatment in the electric furnace, it is preferable to proceed for 20 to 60 minutes at a temperature of 500 ~ 900 ℃.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, when the cobalt for forming the silicide is deposited using a high power, even if the natural oxide film remains in the silicide formation portion, it is possible to penetrate the natural oxide film sufficiently to form the silicide stably and uniformly. Therefore, a high quality semiconductor device can be provided.

Claims (11)

Sequentially forming an oxide film and a polycrystalline silicon layer on a semiconductor substrate having an active region defined therein, and then patterning the gate to form a gate; Forming spacers on sidewalls of the gate; Forming a cap oxide film on the gate; Forming a source and a drain region in the active region, Removing the cap oxide layer; Forming a silicide metal layer on the entire upper surface of the semiconductor substrate by a sputtering method; Forming a protective metal layer on the silicide metal layer and performing a first heat treatment to form a silicide on the gate, source and drain regions; Removing the protective metal layer and the silicide metal layer that is not silicided, Stabilizing the silicide by subjecting the substrate to a second heat treatment, In the forming of the silicide metal layer, the silicide metal layer is formed at a high DC power capable of removing a natural oxide film formed on the substrate. The high DC power is a method of manufacturing a semiconductor device 2 to 10 kW. In claim 1, And forming a lightly doped region in said active region prior to forming a spacer on sidewalls of said gate. The method of claim 1 or 2, The silicide metal layer is a method of manufacturing a semiconductor device cobalt. The method of claim 1 or 2, The protective metal layer is a manufacturing method of a semiconductor device of any one of Ti, TiN or Ti / TiN. delete In claim 1, The argon gas injected into the sputter when forming the silicide metal layer in the sputter is 40 ~ 70sccm, the heater argon gas is 8-15sccm. The method of claim 1 or 2, The first heat treatment is performed for 10 to 60 seconds at 400 ~ 600 ℃ by RTP method, The secondary heat treatment is a method of manufacturing a semiconductor device that proceeds for 10 to 60 seconds at 800 ~ 950 ℃ by RTP method. The method of claim 1 or 2, The first heat treatment is performed for 20 to 60 minutes at 300 ~ 600 ℃ in an electric furnace, The secondary heat treatment is a method of manufacturing a semiconductor device is performed for 20 to 60 minutes at 500 ~ 900 ℃ in an electric furnace. delete delete delete

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