KR100498688B1 - Method for manufacturing multi-gate fin fet in semiconductor - Google Patents
Method for manufacturing multi-gate fin fet in semiconductor Download PDFInfo
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- KR100498688B1 KR100498688B1 KR10-2003-0060851A KR20030060851A KR100498688B1 KR 100498688 B1 KR100498688 B1 KR 100498688B1 KR 20030060851 A KR20030060851 A KR 20030060851A KR 100498688 B1 KR100498688 B1 KR 100498688B1
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- insulating film
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- 238000000034 method Methods 0.000 title claims abstract description 37
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000004020 conductor Substances 0.000 claims abstract description 25
- 239000007943 implant Substances 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 8
- 238000001312 dry etching Methods 0.000 claims abstract description 6
- 125000006850 spacer group Chemical group 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims abstract description 3
- 238000002513 implantation Methods 0.000 claims abstract 4
- 238000005468 ion implantation Methods 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- 239000002131 composite material Substances 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 229910021332 silicide Inorganic materials 0.000 claims description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 5
- 239000002019 doping agent Substances 0.000 abstract description 4
- 230000035515 penetration Effects 0.000 abstract description 4
- 239000003989 dielectric material Substances 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- 239000012212 insulator Substances 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000010405 reoxidation reaction Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
본 발명은 반도체의 멀티 게이트 핀 FET 제조방법에 관한 것으로, 반도체 기판 상에 절연막을 형성하고, 절연막 상에 핀(Fin) 형성을 위한 제1 도전체를 증착하는 단계와, 제1 도전체 상에 감광막 패턴을 형성하는 단계와, 형성된 패턴과 건식 식각을 통해 제2 도전체를 형성하고, 감광막을 제거하는 단계와, 감광막이 제거된 상태에서, 임플란테이션을 이용하여 Vt-어드저스트 임플란트(Adjust Implant)를 실시하는 단계와, 임플란트를 실시한 후, 게이트 절연막을 형성하며, 마스크 패턴을 이용하며 건식 식각을 통해 제3 도전체를 형성하는 단계와, 제3 도전체가 형성된 상태에서, 임플란테이션 방법을 이용하여 LDD 임플란트를 실시하는 단계와, LDD 임플란트를 실시한 상태에서, 전면 식각 방법을 통해 스페이서 막을 형성하며, 임플란테이션 방법을 이용하여 소스/드레인 임플란트를 실시하는 단계를 포함한다. 따라서, GOI 페일을 방지하여 반도체의 수율을 향상시키며, 트랜지스터의 폭을 크게함과 동시에 멀티 게이트 핀-FET의 사용에 따라 커런트 퍼포먼스를 향상시킬 수 있으며, 또한 게이트 유전체 메터리얼 내부로의 도펀트 침투를 최소화하여 우수한 게이트 리키지 특성을 얻을 수 있는 효과가 있다. The present invention relates to a method for manufacturing a multi-gate fin FET of a semiconductor, comprising: forming an insulating film on a semiconductor substrate, depositing a first conductor for forming a fin on the insulating film, and depositing a first conductor on the first conductor Forming a photoresist pattern, forming a second conductor through the formed pattern and dry etching, removing the photoresist, and removing the photoresist, using a implant, using a Vt-adjusted implant (Adjust) Implanting, forming a gate insulating film after implanting, forming a third conductor through dry etching using a mask pattern, and in a state in which the third conductor is formed, an implantation method Performing a LDD implant using the method, and in the state where the LDD implant is performed, forming a spacer layer through a front etching method, and using a source using an implantation method. / Performing the drain implant. This prevents GOI failing to improve semiconductor yield, increases transistor width, improves current performance with the use of multi-gate pin-FETs, and minimizes dopant penetration into the gate dielectric material. Thus, there is an effect of obtaining excellent gate leakage characteristics.
Description
본 발명은 반도체의 멀티 게이트 핀 에프이티(Fin FET) 제조방법에 관한 것으로, 특히, 슬로프 식각(slope etch)을 적용함과 동시에 저온 공정인 포밍 가스 어닐(Forming Gas Anneal)을 이용하여 게이트 유전체(gate dielectric)를 형성하여 핀 FET를 제작할 수 있도록 하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multi-gate fin FET of a semiconductor. In particular, the present invention relates to a method of manufacturing a gate dielectric using a forming gas anneal, which is a low temperature process while applying slope etching. A method of forming a gate dielectric allows a fin FET to be fabricated.
통상적으로, 핀 FET는 핀을 수직으로 형성하여 추후 게이트 절연(Gate Insulator) 물질을 형성함에 있어 핀 버텀 에지(fin bottom edge) 부위에서 게이트 절연물질이 얇게 증착되거나 혹은 비정상적인 형태로 인하여 지오아이(Gate Oxide Integrity Fail, GOI) 페일(Fail) 가능성이 많다. In general, in the fin FET, the fin is vertically formed to form a gate insulator material, and the gate insulator is thinly deposited or abnormally formed at the fin bottom edge. Oxide Integrity Fail (GOI) Fails are likely.
또한, 유전체 증착 공정, 혹은 후속 열처리 공정 동안에 유전체층 내부로의 도펀트 침투(dopant penetration)로 말미암아 소자의 신뢰도에 문제점이 있다. In addition, there is a problem in the reliability of the device due to dopant penetration into the dielectric layer during the dielectric deposition process or subsequent heat treatment process.
이뿐만 아니라, 소자의 미세화에 따른 커런트 퍼포먼스(current performance)가 충분히 나오지 않게 되는 문제점을 갖고 있다. In addition to this, there is a problem that the current performance due to the miniaturization of the device does not come out sufficiently.
따라서, 본 발명은 상술한 문제점을 해결하기 위해 안출된 것으로, 그 목적은 슬로프 식각(slope etch)을 적용함과 동시에 저온 공정인 포밍 가스 어닐(Forming Gas Anneal)을 이용하여 게이트 유전체(gate dielectric)를 형성하여 도펀트 침투(dopant penetration)를 방지하는 핀 FET를 제작할 수 있도록 하는 반도체의 멀티 게이트 핀 FET 제조방법을 제공함에 있다. Accordingly, the present invention has been made to solve the above-described problems, the object of which is to apply a slope etch (slope etch) and at the same time using a low temperature process forming gas anneal (Forming Gas Anneal) using a gate dielectric (gate dielectric) To provide a method for manufacturing a multi-gate fin FET of a semiconductor to form a fin FET that prevents dopant penetration by forming a.
이하, 첨부된 도면을 참조하여 본 발명의 구성 및 동작에 대하여 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the configuration and operation of the present invention.
도 1a 내지 도 1e는 본 발명의 일실시 예에 따른 반도체의 멀티 게이트 핀 FET 제조과정에 대하여 도시한 도면이다. 1A to 1E are views illustrating a process of manufacturing a multi-gate pin FET of a semiconductor according to an embodiment of the present invention.
즉, 도 1a를 참조하면, 반도체 기판(10) 상에 절연막(30)을 형성하고, 핀(Fin) 형성을 위한 막인 제1 도전체(50)를 절연막(30) 상에 증착한 다음, 제1 도전체(50) 상에 마스크 또는 감광막(55) 패턴을 형성한다. 여기서, 제1 도전체(50)를 식각 시에 슬로프 식각을 수행하며, 제1 도전체(50)를 폴리 실리콘으로 이용한다. That is, referring to FIG. 1A, an insulating film 30 is formed on the semiconductor substrate 10, and a first conductor 50, which is a film for forming fins, is deposited on the insulating film 30. 1 A mask or photosensitive film 55 pattern is formed on the conductor 50. Here, the slope etching is performed when the first conductor 50 is etched, and the first conductor 50 is used as polysilicon.
다음으로, 도 1b를 참조하면, 마스크 또는 감광막(55)에 의해 형성된 패턴을 이용하며 건식 식각을 통해 제2 도전체(75)를 형성하고, 마스크 또는 감광막(55)을 제거한 다음에, 이온주입 공정을 이용하여 Vt-어드저스트 임플란트(Adjust Implant)(80)를 실시한다. Next, referring to FIG. 1B, the second conductor 75 is formed by dry etching using a pattern formed by the mask or the photoresist layer 55, and after removing the mask or the photoresist layer 55, ion implantation is performed. The process is used to carry out the Vt-Adjust Implant 80.
이후, 도 1c를 참조하면, 도 1b의 상태에서, 게이트 절연막(도식하지 않음)을 증착한 후, 마스크 패턴을 이용하여 건식 식각을 통해 제3 도전체(90)를 형성한다. 이때, 스푸터링 방법(sputtering method)을 이용하여 하프늄(Hf)을 증착하고, 리옥사이데이션(reoxidation) 방법을 적용하여 하프늄 산화막(HfOx)을 형성한 다음에, 포밍 가스 어닐(Forming Gas Anneal) 처리를 수행한다. 또한, ALD(Atomic Layer Deposition) 방법을 이용하기도 한다. 여기서 게이트 절연막은 리플렉토리 메탈(refractory metal) 옥시 질화막으로 형성될 수 있다.Subsequently, referring to FIG. 1C, after depositing a gate insulating layer (not illustrated) in the state of FIG. 1B, a third conductor 90 is formed through dry etching using a mask pattern. At this time, hafnium (Hf) is deposited using a sputtering method, and a hafnium oxide film (HfOx) is formed by applying a reoxidation method, followed by forming gas annealing. Perform the process. In addition, an ALD (Atomic Layer Deposition) method is also used. The gate insulating layer may be formed of a reflective metal oxynitride layer.
여기서, 제3 도전체(90)는 폴리 실리콘을 이용하며, 또한 실리사이드(Silicide) 혹은 살리사이드(Salicide)를 이용할 수 있다. Here, the third conductor 90 may be made of polysilicon, and may use silicide or salicide.
제3 도전체(90)가 형성된 상태에서, 도 1d와 같이, 저농도 이온주입공정을 수행하여 LDD 임플란트(110) 영역을 형성한다. In the state where the third conductor 90 is formed, as shown in FIG. 1D, a low concentration ion implantation process is performed to form the LDD implant 110 region.
다음으로, 도 1e를 참조하면, LDD 임플란트(110)를 실시한 상태에서, 전면 식각 방법을 통해 스페이서 막(130)을 형성하며, 소오스/드레인 이온주입공정을 통해 소스/드레인을 형성한다. 여기서, 스페이서 막(130)은 질화막 또는 산화막을 이용하며, 또한 질화막과 산화막의 복합적인 막을 이용할 수 있다. Next, referring to FIG. 1E, in the state where the LDD implant 110 is performed, the spacer layer 130 is formed through the entire surface etching method, and the source / drain is formed through the source / drain ion implantation process. Here, the spacer film 130 may use a nitride film or an oxide film, and may also use a composite film of the nitride film and the oxide film.
도 2는 도 1e의 소스/드레인 임플란트(150)를 실시한 더블 핀 FET 또는 멀티 핀 FET의 탑-뷰(top-view) 레이 아웃에 대하여 도시한 도면이다. FIG. 2 shows a top-view layout of a double pin FET or multi pin FET with the source / drain implant 150 of FIG. 1E.
도 3a는 도 2의 A-A 방향으로 잘랐을 경우의 단면을 도시한 도면이다. 3A is a diagram illustrating a cross section when it is cut in the direction A-A of FIG. 2.
그리고, 도 3b는 도 2의 B-B 방향으로 잘랐을 경우의 단면을, 즉 제2 도전체(75) 식각 시에 슬로프 식각을 적용하여 형성한 제2 도전체(75)의 프로파일을 도시한 도면이다. 3B is a diagram illustrating a profile of the second conductor 75 formed by applying a slope etching at the time of etching the second conductor 75, that is, a cross section in the B-B direction of FIG. 2.
여기서, 도 2b(70)과 도 3b의 핀의 버텀 에지(70-1)는 게이트 절연막을 도식한 것이다.2B70 and the bottom edge 70-1 of the fin of FIG. 3B illustrate a gate insulating film.
상기와 같이 설명한 본 발명은 슬로프 식각(slope etch)을 적용함과 동시에 저온 공정인 포밍 가스 어닐(Forming Gas Anneal)을 이용하여 게이트 유전체(gate dielectric)를 형성하는 핀 FET를 제작함으로써, GOI 페일을 방지하여 반도체의 수율을 향상시키며, 트랜지스터의 폭을 크게함과 동시에 멀티 게이트 핀-FET의 사용에 따라 커런트 퍼포먼스를 향상시킬 수 있으며, 또한 게이트 유전체 물질 내부로의 도펀트 침투를 최소화하여 우수한 게이트 리키지 특성을 얻을 수 있는 효과가 있다. The present invention as described above, while applying a slope etch (slope etch) and at the same time forming a gate dielectric (gate dielectric) using a forming gas anneal (Forming Gas Anneal), a low temperature process, by forming a GOI fail Improves semiconductor yield, increases transistor width, improves current performance with the use of multi-gate pin-FETs, and minimizes dopant penetration into the gate dielectric material. There is an effect that can be obtained.
도 1은 본 발명의 일실시 예에 따른 반도체의 멀티 게이트 핀 에프이티 제조 과정에 대하여 도시한 도면이고, 1 is a diagram illustrating a process of manufacturing a multi-gate fin FFT of a semiconductor according to an embodiment of the present invention.
도 2는 도 1의 소스/드레인 임플란트를 실시한 더블 핀 FET 또는 멀티 핀 FET의 탑-뷰(top-view) 레이 아웃에 대하여 도시한 도면이며,FIG. 2 shows a top-view layout of a double pin FET or a multi pin FET with the source / drain implant of FIG. 1, FIG.
도 3은 도 2의 A-A 방향 및 B-B 방향으로 잘랐을 경우의 크로스 섹션을 도시한 도면이다. FIG. 3 is a diagram illustrating a cross section when cut in the A-A direction and the B-B direction of FIG. 2.
Claims (10)
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| KR10-2003-0060851A KR100498688B1 (en) | 2003-09-01 | 2003-09-01 | Method for manufacturing multi-gate fin fet in semiconductor |
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| KR10-2003-0060851A KR100498688B1 (en) | 2003-09-01 | 2003-09-01 | Method for manufacturing multi-gate fin fet in semiconductor |
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| KR20050024749A KR20050024749A (en) | 2005-03-11 |
| KR100498688B1 true KR100498688B1 (en) | 2005-07-01 |
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