KR100449323B1 - Method of manufacturing short-channel transistor in semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a transistor of a semiconductor device, which can reduce short channel effect (SCE) and DIBL without additional processing, thereby manufacturing a transistor having excellent characteristics. In the transistor manufacturing method of the semiconductor device according to the present invention for this purpose, a first oxide film is formed on a semiconductor substrate, and the first nitride film, the second oxide film, and the second nitride film are sequentially deposited, and then a predetermined pattern is formed using the first photosensitive film. Dry etching the second nitride film, the second oxide film and the first nitride film using the first photosensitive film as a mask, and performing a doping process on the structure to perform counter doping in the exposed semiconductor substrate. Forming a first insulating film by wet etching the first oxide film, forming a gate insulating film on an exposed semiconductor substrate of the structure, and depositing a gate conductor film on the gate insulating film. Forming a gate conductor by a polishing (CMP) process, the second nitride film, and the second oxide film The first nitride layer is removed by a wet etching method, and a lightly doped drain (LDD) is formed on the semiconductor substrate outside the gate by an implantation method, and then spacers are formed on both sides of the gate conductor, and then on the semiconductor substrate outside the spacer. Forming a source / drain region by performing an ion implantation process on impurities, wet etching the first insulating layer, and performing a heat treatment process to form a counter doping region, an LDD implant region, and a source / drain region; And depositing a salicide film on the gate conductor and the source / drain region by performing an annealing process after depositing the salicide on the structure.

Description

METHODS OF MANUFACTURING SHORT-CHANNEL TRANSISTOR IN SEMICONDUCTOR DEVICE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor manufacturing method of a semiconductor device. In particular, a transistor of a semiconductor device capable of manufacturing a transistor having excellent characteristics by reducing a short channel effect (SCE) and a drain induced barrier lowering (DIBL) without additional processing It relates to a manufacturing method.

1 is a cross-sectional view illustrating a transistor manufacturing method of a semiconductor device according to the prior art.

As shown, a buffer gate insulating film 2, a polysilicon layer 3a and a hard mask layer 3b are sequentially stacked on the semiconductor substrate 1 on which a field oxide film (not shown) having a predetermined height is formed.

Subsequently, the hard mask layer 3b is patterned in the form of a gate electrode, and then, in the form of the hard mask layer 3b, the polysilicon layer 3a and the buffer gate insulating film 2 are patterned to form a gate g. To form.

Thereafter, the spacers 4 are formed on both sides of the gate g by a known method, and then, impurities are injected into the semiconductor substrate 1 outside the spacers 4 to form the source and drain 5.

However, the conventional method of manufacturing a transistor of a semiconductor device having the above configuration has a disadvantage in that an additional process (Halo Implant) is required to overcome the short channel effect and the drain induced barrier lowering (DIBL) of the transistor. .

Accordingly, the present invention has been made to solve the above problems, and the present invention can manufacture a transistor having excellent characteristics by reducing the effects of the short channel effect (SCE) and the drain induced barrier lowering (DIBL) without additional processing. It is an object of the present invention to provide a method for manufacturing a short channel transistor of a semiconductor device.

1 is a cross-sectional view illustrating a transistor manufacturing method of a semiconductor device according to the prior art.

2A to 2E are cross-sectional views illustrating a method of manufacturing a transistor of a semiconductor device according to the present invention.

Explanation of symbols on the main parts of the drawings

1: semiconductor substrate 3, 3 ', 3 ": first oxide film

5, 5 ': first nitride film 7, 7': second oxide film

9, 9 ': 2nd nitride film 11: counter doping injection

13, 13 ': counter doping profile in substrate 15: gate insulating film

19, 19 ': Low doped drain (LDD) implant 21: spacer membrane

23, 23 ': source / drain implant or source / drain area

25: Salicide

30: first mask or first photosensitive film

A transistor manufacturing method of a semiconductor device according to the present invention for achieving the above object,

Forming a first oxide film on the semiconductor substrate, sequentially depositing a first nitride film, a second oxide film, and a second nitride film, and then forming a predetermined pattern using the first photosensitive film;

Dry etching the second nitride film, the second oxide film, and the first nitride film using the first photosensitive film as a mask;

Performing a doping process on the structure to perform counter doping in the exposed semiconductor substrate;

Etching the first oxide film by wet etching to form a first insulating film;

Forming a gate insulating film on the exposed semiconductor substrate of the structure;

Depositing a gate conductor film on the gate insulating film and forming a gate conductor by a chemical mechanical polishing (CMP) process;

The second nitride film, the second oxide film, and the first nitride film are removed by a wet etching method, and a lightly doped drain (LDD) is formed on a semiconductor substrate outside the gate by an implantation method, and then spacers are formed on both sides of the gate conductor. Thereafter, implanting impurities into the semiconductor substrate outside the spacer to form a source / drain region;

Wet etching the first insulating layer and then performing a heat treatment process to form a counter doped region, an LDD implant region, and a source / drain region;

And depositing a salicide film on the gate conductor and the source / drain region by performing an annealing process after depositing the salicide on the structure.

The counter doping source is characterized by using an implant source of the same type as the well.

The counter doping source is characterized in that using a germanium (Ge) implant source.

The spacer is characterized in that using a nitride film.

The gate conductor is characterized in that using polysilicon.

The gate conductor is characterized in that using a metal.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2E are cross-sectional views for explaining a transistor manufacturing method of a semiconductor device according to the present invention.

First, in the process shown in FIG. 2A, the first oxide film 3 is formed on the semiconductor substrate 1, and the first nitride film 5, the second oxide film 7, and the second nitride film 9 are sequentially deposited. A predetermined pattern is formed by using the first photosensitive film 30.

In the process shown in FIG. 2B, the second nitride film 9, the second oxide film 7, and the first nitride film 5 are etched by using the first photosensitive film 30 as a mask. '), The second oxide film 7' and the first nitride film 5 'are formed. At this time, the etching uses dry etching.

Next, a counter doping 11 is performed in the exposed semiconductor substrate 1 by performing an implantation process on the structure. Here, the source of the counter doping 11 uses an implant source of the same type as the well.

In the process shown in FIG. 2C, a counter doping implant 13 is formed in the semiconductor substrate 1 exposed by the counter doping 11 in FIG. 2B. Next, the first insulating layer 3 is etched by a wet etching method to form the first insulating layer 3 ′.

The process illustrated in FIG. 2D is performed by forming a gate insulating film 15 on the exposed semiconductor substrate 1, depositing a gate conductor film, and then using a chemical mechanical polishing (CMP) process. ).

Next, the second nitride film 9 ', the second oxide film 7' and the first nitride film 5 'are removed by a wet etching method.

Next, an LDD (Lightly DopedDrain) ion implantation process is performed on the semiconductor substrate 1 outside the gate conductor 17 to form the LDD implantation region 19.

Next, a spacer layer is deposited on both sides of the gate conductor 17 by depositing a spacer film and then etching the entire surface.

Next, the source / drain region 23 is formed by performing an ion implantation process on the semiconductor substrate 1 outside the spacer 21.

In the process illustrated in FIG. 2E, the first oxide layer 3 ′ is etched by the wet etching method using the structure of FIG. 2D to form the first oxide layer 3 ″.

Next, a heat treatment process is performed to form a counter doped region 13 ′, an LDD implanted region 19 ″, and a source / drain region 23 ′.

Next, after the salicide 25 is deposited on the structure, the salicide layer 25 is deposited on the gate conductor 17 and the source / drain regions 23 ′ by performing an annealing process. .

As described above, according to the method of manufacturing a semiconductor device according to the present invention, it is possible to reduce the effects of SCE and DIBL of the transistor without additional steps, and thus to produce a transistor having excellent characteristics.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims. something to do.

Claims (6)

In the manufacturing method of a semiconductor device, Sequentially depositing a first oxide film, a first nitride film, a second oxide film, and a second nitride film; Etching the second nitride film, the second oxide film, and the first nitride film by using a photoresist pattern; Defining a counter impurity region through the impurity implantation process into the structure; Etching the first oxide film to expose the substrate; Depositing a gate insulating film on the exposed substrate; Depositing a conductive film on the gate insulating film to form a gate electrode; Removing the second nitride film, the second oxide film, and the first nitride film; Defining an LDD region through an LDD impurity implantation process; Forming spacers on both sidewalls of the gate electrode; And And defining a source / drain region through a source / drain impurity implantation process. The method of claim 1, After defining the source / drain regions, removing the first oxide layer and forming silicide. The method of claim 1, The first oxide film is a method of manufacturing a semiconductor device, characterized in that the etching through wet etching. The method of claim 1, The counter doping source is a transistor manufacturing method of a semiconductor device, characterized in that using the same type of implant source as the well. The method of claim 1, The counter doping source is a transistor manufacturing method of a semiconductor device, characterized in that using a germanium implant source. The method of claim 1, The spacer is a transistor manufacturing method of a semiconductor device, characterized in that using the nitride film.