KR20000024755A - Method for forming gate electrode of semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming gate electrode of semiconductor device is provided to prevent an increase of a parasitic resistance by vertically forming a gate electrode using a damascene process. CONSTITUTION: A dummy oxidation film(106), a silicon nitration film(105), and a pad oxidation film(104) are successively etched using a mask for defining a gate electrode forming region and then an opening(108) for a gate electrode forming is vertically formed. The dummy oxidation film(106) is performed by an anisotropy etching, and an etching of the silicon nitration film(105) and the pad oxidation film(104) is performed by the anisotropy etching or an isotropy etching. An ion injection process is performed when forming the opening(108). The dummy oxidation film(106) is etched and the silicon nitration film(105) is exposed. The dummy oxidation film(106) and the silicon nitration film(105) are successively etched, and then the pad oxidation film(104) is exposed.

Description

METHOD OF FORMING GATE ELECTRODE FOR SEMICONDUCTOR DEVICE

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a gate electrode of a semiconductor device.

As the degree of integration of semiconductor devices has increased, the size has been reduced, and the design rule has been kept smaller. As a result, the gate electrode formation of the transistor becomes more difficult. In particular, the cell region in which the gate lines are repeatedly formed while maintaining a narrow space between the gate electrode and the gate electrode and the peripheral region in which the gate electrode is small in size and a large gate line is randomly formed are mixed. In the case of DRAM, it is difficult to vertically control the control of the critical dimension (CD) and in particular the slope of the gate electrode due to the landing effect in the anisotropic etching for forming the gate line. .

In addition, to reduce the resistance of the gate line, a polycide structure in which a polysilicon layer and a silicide layer are stacked as a conductive layer of the gate electrode and a silicon nitride layer (SiN) on the gate polyside Is used to cover the insulating film. In addition, a self-aligned contact (SAC) structure is applied to secure a margin of the cell contact. As a result, when forming the gate electrode, the process of etching the films having different etching rates in the stacked stack structure of the insulating film, the silicide, and the polysilicon becomes more difficult.

1A to 1B are flowcharts sequentially illustrating processes of a method of forming a gate electrode of a conventional semiconductor device.

Referring to FIG. 1A, in the conventional method of forming a gate electrode of a semiconductor device, a device isolation region 12 for defining an active region and an inactive region is first formed in a semiconductor substrate 10. Subsequently, a gate oxide film 14, a polysilicon film 16, a silicide film 17, and a gate mask 18 are sequentially formed on the semiconductor substrate 10.

The gate electrode 19 is formed by sequentially etching the gate mask 18, the silicide layer 17, and the polysilicon layer 16 using a gate electrode forming mask.

An etching process for forming the gate electrode 19 is mainly performed by using reactive ion etching (RIE). In general, a profile of the gate electrode 19 is vertically formed, and a gate oxide layer 14 during etching is performed. ) Should have a high etch selectivity to etch stop layer. However, in order to maintain a high etching selectivity with respect to the gate oxide layer 14 due to the characteristics of the RIE, the linearity of the gate electrode 19 is inevitably inclined during etching.

In particular, this becomes more difficult as the thickness of the gate oxide film 14 becomes thinner by a few nm and has a laminated structure of a complicated structure. In addition, the gate oxide layer 14 on both sides of the gate electrode 19 may be damaged by RIE during etching to form the gate electrode, and thus the gate oxide layer 14 may be degraded. In order to prevent this, an oxidation process or a thermal process is required. In the polyside structure, the polyside may be oxidized during the oxidation process.

Also, in a memory such as a DRAM having a different pattern density of gate lines, a pattern gap at a high pattern density is narrow, so that the amount of etchant reaching a dense pattern during etching is relatively small, compared to a wide pattern. Due to the landing effect of reducing the amount of etching, the gate of the cell surrounding area having a lower density than the cell area having the highest pattern density has a more gentle slope as shown in FIG. 1A.

Next, a nitride film is formed on the semiconductor substrate 10 including the gate electrode 19. The insulating film spacers 22 are formed on both sidewalls of the gate electrode 19 by etching the nitride film by an etch back process.

However, the insulating film spacer 22 formed on both side walls of the gate electrode 19 is formed as shown in FIG. 1B because the gate electrode 19 has a slope. As a result, the active width between the gate electrode 19 and the device isolation region 12 may be reduced to increase parasitic resistance, and may cause a problem of weak misalign margin during subsequent contact forming processes. have. In the cell region, a bit line contact and a storage node contact should be formed between the gate and the gate, and the size of the opening opened by the gate electrode 19 having the slope is reduced, resulting in an increase in contact resistance.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problems, and provides a gate electrode forming method of a semiconductor device capable of vertically forming gate electrodes and preventing deterioration of gate oxide films on both sides of the gate electrodes. There is this.

1A to 1B are flowcharts sequentially showing processes of a method of forming a gate electrode of a conventional semiconductor device; And

2A through 2E are flowcharts sequentially illustrating processes of a method of forming a gate electrode of a semiconductor device according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

10, 100: semiconductor substrate 12, 102: device isolation region

14 gate oxide film 106 dummy oxide film

19, 117: gate electrodes 22, 118: insulating film spacer

(Configuration)

According to the present invention for achieving the above object, a method of forming a gate electrode of a semiconductor device comprises the steps of sequentially stacking a first insulating film, a material film, and a second insulating film on a semiconductor substrate in which an active region and an inactive region are defined; ; The opening for forming the gate electrode is formed by sequentially etching the second insulating film, the material film, and the first insulating film until the surface of the semiconductor substrate is exposed using a mask for defining a gate electrode forming region, but vertically etching Making a step; Forming a gate electrode by sequentially stacking a third insulating film, a conductive film, and a gate mask on the opening; Removing second insulating films on both sides of the gate electrode; Forming insulating film spacers on both sidewalls of the gate electrode.

According to the present invention for achieving the above object, a gate electrode forming method of a semiconductor device comprises a second insulating film, a material film, and a first insulating film formed on a semiconductor substrate using a mask for defining a gate electrode forming region. Etching sequentially to form an opening for forming a gate electrode, but vertically etching; Filling the opening with a first conductive film; Etching the first conductive film evenly so as to be parallel to the second insulating film; Etching using the second insulating film as a mask so that a part of the thickness of the first conductive film remains; And sequentially forming a gate mask having a surface parallel to the second conductive film and the second insulating film on the first conductive film.

(Action)

Referring to FIG. 2B, a method of forming a gate electrode of a novel semiconductor device according to an embodiment of the present invention includes a first insulating film, a material film, and a second insulating film sequentially stacked on a semiconductor substrate in which active regions and inactive regions are defined. Is etched using a mask for defining the gate electrode formation region until the surface of the semiconductor substrate is exposed to form an opening for forming the gate electrode. At this time, the opening is vertically etched. After the opening is formed by stacking the third insulating film, the conductive film, and the gate mask in order, a gate electrode is formed, and the second insulating films on both sides of the gate electrode are removed. Subsequently, insulating film spacers are formed on both sidewalls of the gate electrode. By the gate electrode formation method of such a semiconductor device, the gate electrode is vertically formed by using a damascene process, thereby preventing parasitic resistance increase and misalignment margin from becoming weak, and contact resistance in the cell region. This can be prevented from increasing. In addition, the gate oxide films on both sides of the gate electrode can be prevented from being damaged by etching damage or the like, and the short channel effect of the transistor can be suppressed by ion implantation into the channel region under the gate electrode.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 2A to 2E.

2A through 2E are flowcharts sequentially illustrating processes of a method of forming a gate electrode of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 2A, in the gate electrode forming method of the semiconductor device of the present invention, an element isolation region 102 for defining an active region and an inactive region is first formed in the semiconductor substrate 100. The device isolation region 102 is formed of shallow trench isolation (STI). Subsequently, a pad oxide film 104, a silicon nitride film 105, and a dummy oxide film 106 are sequentially stacked on the semiconductor substrate 100. The silicon nitride layer 105 is used as a layer to prevent the pad oxide layer 104 from being etched and deteriorated during the subsequent etching of the gate electrode. When the subsequent contact forming process is not performed by the self-aligned contact (SAC) process, the dummy silicon nitride layer may be formed instead of the dummy oxide layer 106.

The pad oxide film 104 is formed in a thickness range of 5 nm to 20 nm, and the silicon nitride film 105 is formed in a thickness range of 10 nm to 30 nm. The dummy oxide film 106 is formed in a thickness range of 150 nm to 400 nm.

In FIG. 2B, an opening 108 for vertical gate electrode formation is formed by sequentially etching the dummy oxide film 106, the silicon nitride film 105, and the pad oxide film 104 using a mask for defining a gate electrode formation region. ) Is formed. The dummy oxide layer 106 may be etched by anisotropic etching, and the silicon nitride layer 105 and the pad oxide layer 104 may be etched by anisotropic etching or isotropic etching. At this time, an ion implantation process is performed when the opening 108 is formed, which is performed after the dummy oxide film 106 is etched and the silicon nitride film 105 is exposed, or the dummy oxide film 106 is exposed. And the silicon nitride layer 105 are sequentially etched, and then the pad oxide layer 104 is exposed.

Alternatively, after the etching to the pad oxide film 104, an oxide film may be formed again, and then an ion implantation process may be performed (not shown).

The ion implantation process is a process for forming a punchthrough stopper to adjust the threshold voltage of the transistor or to prevent the short channel effect of the transistor. No ions are implanted under the junction. As a result, the well doping of the junction part is increased to increase leakage current at the junction part, the junction breakdown voltage is lowered, and the junction capacitance is increased to effectively prevent the phenomenon of deterioration of device characteristics and the like. The short channel effect of the transistor can be prevented.

Referring to FIG. 2C, a gate oxide layer 110 is formed on the semiconductor substrate 100 of the opening 108. The gate oxide film 110 is formed in a thickness range of 3nm to 10nm. A polysilicon film 112 doped to fill the opening 108 is then formed. Subsequently, the polysilicon layer 112 is planarized by one of a chemical mechanical polishing (CMP) process and an etch back process until the surface of the dummy oxide layer 106 is exposed, and then the dummy oxide layer 106 is formed. The polysilicon film 112 is etched by an etch back process so that a thickness range of 50 nm to 300 nm remains.

Here, the pad oxide layer 104 may be used as a gate oxide layer without etching the pad oxide layer 104 when the opening 108 is formed. Alternatively, the pad oxide layer 104 may be gated while the pad oxide layer 104 remains. The oxide film can be grown again. However, in order to adjust the thickness of the gate oxide film or to resist the gate oxide film, it is preferable to form the gate oxide film after removing the pad oxide film completely.

Next, a silicide film 114 is formed on the polysilicon film 112. In detail, the silicide layer 114 may perform a silicidation process on any one of a Ti layer, a Co layer, and a Ni layer on the polysilicon layer 112, and then may not react with the silicide layer 114. It is formed by removing. As another method, the method may be formed by covering the silicide layer and etching the same by either the CMP process or the etch back process as in the method of forming the polysilicon layer 112. The silicide layer 114 is formed in a thickness range of 50 nm to 150 nm.

Subsequently, the gate mask 116 is formed of a silicon nitride film to completely fill the opening 108, and then the gate mask 116 is flatly etched until the surface of the dummy oxide film 106 is exposed. 117 is formed. Here, the gate mask 116 is used as a mask to prevent the silicide layer 114 from being exposed during the etching of the interlayer insulating layer for subsequent contact hole formation.

As mentioned above, the gate mask 116 is formed of an oxide film when the opening for forming the gate electrode is formed using the dummy silicon nitride film.

Subsequently, in FIG. 2D, the dummy oxide film 106 is etched by either anisotropic etching or isotropic etching until the surface of the silicon nitride film 105 on both sides of the gate electrode 117 is exposed. In this case, when the dummy silicon nitride layer is used instead of the dummy oxide layer 106, the dummy silicon nitride layer is etched until the pad oxide layer is exposed. In addition, the insulating layers may be etched until the semiconductor substrate 100 is exposed.

Thereafter, a silicon nitride film or an oxide film is formed on the semiconductor substrate 100 including the gate electrode 117 and then etched by an etch back process, thereby as shown in FIG. 2E. An insulating film spacer 118 is formed on both side walls.

According to the present invention, the gate electrode is vertically formed using a damascene process to prevent an increase in parasitic resistance and a weak margin of misalignment, and to prevent an increase in contact resistance in a cell region. There is. In addition, the gate oxide films on both sides of the gate electrode can be prevented from being damaged by etching damage, or the like, and ion implantation into the channel region under the gate electrode can suppress the short channel effect of the transistor.

Claims (11)

Sequentially stacking a first insulating film, a material film, and a second insulating film on a semiconductor substrate in which an active region and an inactive region are defined; The opening for forming the gate electrode is formed by sequentially etching the second insulating film, the material film, and the first insulating film until the surface of the semiconductor substrate is exposed using a mask for defining a gate electrode forming region, but vertically etching Making a step; Forming a gate electrode by sequentially stacking a third insulating film, a conductive film, and a gate mask on the opening; Removing second insulating films on both sides of the gate electrode; Forming an insulating film spacer on both sidewalls of the gate electrode. The method of claim 1, And the gate electrode is formed by a damascene process. The method of claim 1, Wherein the first insulating film is an oxide film, the material film is a silicon nitride film, and the second insulating film is one of an oxide film and a silicon nitride film. The method according to claim 1 or 2, The first insulating film is 5nm to 20nm, the second insulating film is 150nm to 400nm, and the material film is a gate electrode forming method of the semiconductor device is formed in a thickness range of 10nm to 30nm. The method of claim 1, And the third insulating film is a gate oxide film, and the gate mask is any one of a silicon nitride film and an oxide film. The method of claim 1, The third insulating film is a gate electrode forming method of a semiconductor device formed in a thickness range of 3nm to 10nm. The method of claim 1, The conductive film has a structure in which a polysilicon film and a silicide film are laminated. The method of claim 7, wherein The silicide layer is formed of any one of TiSix, CoSix, and NiSix, and formed in a thickness range of 50 nm to 150 nm. Etching the second insulating film, the material film, and the first insulating film formed on the semiconductor substrate in order using a mask for defining the gate electrode forming region, thereby forming an opening for forming the gate electrode, but vertically etching; Filling the opening with a first conductive film; Etching the first conductive film evenly so as to be parallel to the second insulating film; Etching using the second insulating film as a mask so that a part of the thickness of the first conductive film remains; And sequentially forming a gate mask having a surface parallel to the second conductive film and the second insulating film on the first conductive film. The method of claim 9, The first conductive film is a polysilicon film, and the second conductive film is a silicide film. The method of claim 9, The partial thickness is a gate electrode forming method of a semiconductor device is formed in the range of 50nm to 300nm.