KR20030054784A - Method of manufacturing short-channel transistor in semiconductor device - Google Patents
Method of manufacturing short-channel transistor in semiconductor device Download PDFInfo
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- KR20030054784A KR20030054784A KR1020010085194A KR20010085194A KR20030054784A KR 20030054784 A KR20030054784 A KR 20030054784A KR 1020010085194 A KR1020010085194 A KR 1020010085194A KR 20010085194 A KR20010085194 A KR 20010085194A KR 20030054784 A KR20030054784 A KR 20030054784A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 238000000034 method Methods 0.000 claims abstract description 40
- 150000004767 nitrides Chemical class 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000004020 conductor Substances 0.000 claims abstract description 19
- 125000006850 spacer group Chemical group 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 5
- 238000002513 implantation Methods 0.000 claims abstract description 5
- 238000010438 heat treatment Methods 0.000 claims abstract description 4
- 238000005498 polishing Methods 0.000 claims abstract description 4
- 239000000126 substance Substances 0.000 claims abstract description 4
- 239000007943 implant Substances 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 10
- 238000001039 wet etching Methods 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 7
- 230000004888 barrier function Effects 0.000 abstract description 4
- 150000002500 ions Chemical class 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract 1
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 125000001475 halogen functional group Chemical group 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66537—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a self aligned punch through stopper or threshold implant under the gate region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Inorganic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체 소자의 트랜지스터 제조방법에 관한 것으로, 특히 추가적인 공정없이도 쇼트 채널 효과(Short Channel Effect; SCE)와 DIBL(Drain Induced Barrier Lowering)를 줄여서 특성이 우수한 트랜지스터를 제조할 수 있는 반도체 소자의 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor manufacturing method of a semiconductor device. In particular, a transistor of a semiconductor device capable of manufacturing a transistor having excellent characteristics by reducing a short channel effect (SCE) and a drain induced barrier lowering (DIBL) without additional processing It relates to a manufacturing method.
도 1은 종래 기술에 따른 반도체 소자의 트랜지스터 제조 방법을 설명하기 위한 단면도이다.1 is a cross-sectional view illustrating a transistor manufacturing method of a semiconductor device according to the prior art.
도시된 바와 같이, 소정 높이의 필드 산화막(도시되지 않음)이 형성된 반도체 기판(1) 상부에 버퍼 게이트 절연막(2), 폴리실리콘층(3a) 및 하드 마스크층(3b)을 순차적으로 적층한다.As shown, a buffer gate insulating film 2, a polysilicon layer 3a and a hard mask layer 3b are sequentially stacked on the semiconductor substrate 1 on which a field oxide film (not shown) having a predetermined height is formed.
이어서, 하드 마스크층(3b)을 게이트 전극의 형태로 패터닝한다음, 이 하드 마스크층(3b)의 형태로, 폴리실리콘층(3a) 및 버퍼 게이트 절연막(2)을 패터닝하여, 게이트(g)를 형성한다.Subsequently, the hard mask layer 3b is patterned in the form of a gate electrode, and then, in the form of the hard mask layer 3b, the polysilicon layer 3a and the buffer gate insulating film 2 are patterned to form a gate g. To form.
그후, 공지의 방법에 의하여 게이트(g) 양측에 스페이서(4)를 형성한 다음, 스페이서(4) 외측의 반도체 기판(1)에 불순물을 주입하여 소오스, 드레인(5)을 형성한다.Thereafter, spacers 4 are formed on both sides of gate g by a known method, and then impurities are injected into semiconductor substrate 1 outside of spacers 4 to form source and drain 5.
그런데, 상기 구성을 갖는 종래의 반도체 소자의 트랜지스터 제조방법에 있어서는 트랜지스터의 쇼트 채널 효과(Short Channel Effect)와 DIBL(Drain Induced Barrier Lowering)를 극복하기 위해서 추가적인 공정(Halo Implant)이 요구되는 단점이 있었다.However, the conventional method of manufacturing a transistor of a semiconductor device having the above configuration has a disadvantage in that an additional process (Halo Implant) is required to overcome the short channel effect and the drain induced barrier lowering (DIBL) of the transistor. .
따라서, 본 발명은 상기 문제점을 해결하기 위하여 이루어진 것으로, 본 발명은 추가적인 공정없이도 트랜지스터의 SCE(Short Channel Effect)와 DIBL(Drain Induced Barrier Lowering)의 효과를 줄임으로써 특성이 우수한 트랜지스터를 제조할 수 있는 반도체 소자의 쇼트 채널 트랜지스터 제조 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems, and the present invention can manufacture a transistor having excellent characteristics by reducing the effects of the short channel effect (SCE) and the drain induced barrier lowering (DIBL) without additional processing. It is an object of the present invention to provide a method for manufacturing a short channel transistor of a semiconductor device.
도 1은 종래 기술에 따른 반도체 소자의 트랜지스터 제조 방법을 설명하기 위한 단면도1 is a cross-sectional view illustrating a transistor manufacturing method of a semiconductor device according to the prior art.
도 2a 내지 도 2e는 본 발명에 의한 반도체 소자의 트랜지스터 제조 방법을 설명하기 위한 단면도2A to 2E are cross-sectional views illustrating a method of manufacturing a transistor of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1 : 반도체 기판3, 3', 3" : 제 1 산화막1: semiconductor substrate 3, 3 ', 3 ": first oxide film
5, 5' : 제 1 질화막7, 7' : 제 2 산화막5, 5 ': first nitride film 7, 7': second oxide film
9, 9' : 제 2 질화막11 : 카운터 도핑 주입9, 9 ': 2nd nitride film 11: counter doping injection
13, 13' : 기판에서의 카운터 도핑 프로필15 : 게이트 절연막13, 13 ': counter doping profile on substrate 15: gate insulating film
19, 19' : LDD(Low Doped Drain) 임플런트21 : 스페이서 막19, 19 ': Low doped drain (LDD) implant 21: spacer membrane
23, 23' : 소오스/드레인 임플런트 또는 소오스/드레인 영역23, 23 ': source / drain implant or source / drain region
25 : 살리사이드25: Salicide
30 : 제 1 마스크 또는 제 1 감광막30: first mask or first photosensitive film
상기 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 트랜지스터 제조방법은,A transistor manufacturing method of a semiconductor device according to the present invention for achieving the above object,
반도체 기판 위에 제 1 산화막을 형성하고 제 1 질화막, 제 2 산화막 및 제 2 질화막을 차례로 증착한 다음 제 1 감광막을 이용하여 소정의 패턴을 형성한 단계와,Forming a first oxide film on the semiconductor substrate, sequentially depositing a first nitride film, a second oxide film, and a second nitride film, and then forming a predetermined pattern using the first photosensitive film;
상기 제 1 감광막을 마스크로 하여 상기 제 2 질화막과 상기 제 2 산화막 및 상기 제 1 질화막을 건식 식각하는 단계와,Dry etching the second nitride film, the second oxide film, and the first nitride film using the first photosensitive film as a mask;
상기 구조물 위에 주입 공정을 실시하여 노출된 반도체 기판 내에 카운터 도핑을 실시하는 단계와,Performing a doping process on the structure to perform counter doping in the exposed semiconductor substrate;
상기 제 1 산화막을 습식식각으로 식각하여 제 1 절연막을 형성하는 단계와,Etching the first oxide film by wet etching to form a first insulating film;
상기 구조물의 노출된 반도체 기판 위에 게이트 절연막을 형성하는 단계와,Forming a gate insulating film on the exposed semiconductor substrate of the structure;
상기 게이트 절연막 위에 게이트 전도체 막을 증착한 후 화학기계적연마(CMP) 공정으로 게이트 전도체를 형성하는 단계와,Depositing a gate conductor film on the gate insulating film and forming a gate conductor by a chemical mechanical polishing (CMP) process;
상기 제 2 질화막, 상기 제 2 산화막 및 상기 제 1 질화막을 습식 식각 방법으로 제거하고, 주입 방법으로 상기 게이트 외측의 반도체 기판에 LDD(Lightly Doped Drain)를 형성한 후에 상기 게이트 전도체 양측에 스페이서를 형성한 다음, 상기 스페이서 외측의 반도체 기판에 불순물을 이온주입 공정을 진행하여 소오스/드레인 영역을 형성한 단계와,The second nitride film, the second oxide film, and the first nitride film are removed by a wet etching method, and a lightly doped drain (LDD) is formed on a semiconductor substrate outside the gate by an implantation method, and then spacers are formed on both sides of the gate conductor. Next, an impurity ion implantation process is performed on the semiconductor substrate outside the spacer to form a source / drain region;
상기 제 1 절연막을 습식 식각한 후 열처리 공정을 진행하여 카운터 도핑 영역, LDD 주입 영역, 소오스/드레인 영역을 형성하는 단계와,Wet etching the first insulating film and then performing a heat treatment process to form a counter doped region, an LDD implant region, and a source / drain region;
상기 구조물 위에 살리사이드를 증착한 후, 어닐 공정을 실시하여 상기 게이트 전도체와 소오스/드레인 영역에 살리사이드막을 증착한 단계를 포함하는 것을 특징으로 한다.And depositing a salicide layer on the gate conductor and the source / drain regions by depositing salicide on the structure.
상기 카운터 도핑의 소오스는 웰(Well)과 동일한 타입(Type)의 임플런트 소오스를 사용하는 것을 특징으로 한다.The source of the counter doping is characterized by using an implant source of the same type as the well.
상기 카운터 도핑의 소오스는 게르마늄(Ge)을 임플런트 소오스를 사용하는 것을 특징으로 한다.The source of the counter doping is characterized in that the germanium (Ge) using an implant source.
상기 스페이서는 질화막을 사용하는 것을 특징으로 한다.The spacer is characterized in that using a nitride film.
상기 게이트 전도체는 폴리실리콘을 사용하는 것을 특징으로 한다.The gate conductor is characterized in that using polysilicon.
상기 게이트 전도체는 메탈을 사용하는 것을 특징으로 한다.The gate conductor is characterized in that using a metal.
이하, 본 발명의 실시예에 관하여 첨부도면을 참조하면서 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명에 의한 반도체 소자의 트랜지스터 제조 방법을 설명하기 위한 단면도이다.2A to 2E are cross-sectional views for explaining a transistor manufacturing method of a semiconductor device according to the present invention.
먼저, 도 2a에 도시된 공정은, 반도체 기판(1) 위에 제 1 산화막(3)을 형성하고 제 1 질화막(5), 제 2 산화막(7) 및 제 2 질화막(9)을 차례로 증착한 후 제 1 감광막(30)를 이용하여 소정의 패턴을 형성한 단계이다.First, in the process shown in FIG. 2A, the first oxide film 3 is formed on the semiconductor substrate 1, and the first nitride film 5, the second oxide film 7, and the second nitride film 9 are sequentially deposited. A predetermined pattern is formed by using the first photosensitive film 30.
도 2b에 도시된 공정은, 상기 제 1 감광막(30)을 마스크로 하여 상기 제 2 질화막(9)과 상기 제 2 산화막(7) 및 상기 제 1 질화막(5)을 식각하여 제 2 질화막(8')과 제 2 산화막(7') 및 제 1 질화막(5')을 형성한다. 이때, 식각은 건식식각을 사용한다.In the process shown in FIG. 2B, the second nitride film 9, the second oxide film 7, and the first nitride film 5 are etched by using the first photosensitive film 30 as a mask. '), The second oxide film 7' and the first nitride film 5 'are formed. At this time, the etching uses dry etching.
다음, 상기 구조물 위에 주입(Implantation) 공정을 실시하여 노출된 상기 반도체 기판(1) 내에 카운터 도핑(Counter Doping)(11)을 실시하는 단계이다. 여기서, 카운터 도핑(11)의 소오스는 웰(Well)과 동일한 타입(Type)의 임플런트 소오스를 사용한다.Next, a counter doping 11 is performed in the exposed semiconductor substrate 1 by performing an implantation process on the structure. Here, the source of the counter doping 11 uses an implant source of the same type as the well.
도 2c에 도시된 공정은, 도 2b에서의 카운터 도핑(11)에 의해 노출된 상기 반도체 기판(1) 내에 카운터 도핑 임플런트(13)가 형성된다. 다음, 습식 식각 방법으로 상기 제 1 절연막(3)을 식각하여 제 1 절연막(3')을 형성한 단계이다.In the process shown in FIG. 2C, a counter doping implant 13 is formed in the semiconductor substrate 1 exposed by the counter doping 11 in FIG. 2B. Next, the first insulating layer 3 is etched by a wet etching method to form the first insulating layer 3 ′.
도 2d에 도시된 공정은, 노출된 상기 반도체 기판(1) 위에 게이트 절연막(15)을 형성한 후 게이트 전도체 막을 증착한 다음 화학기계적연마(Chemical Mechanical Polishing: CMP) 공정을 이용하여 게이트 전도체(17)를 형성한다.The process illustrated in FIG. 2D is performed by forming a gate insulating film 15 on the exposed semiconductor substrate 1, depositing a gate conductor film, and then using a chemical mechanical polishing (CMP) process. ).
다음, 습식 식각 방법으로 상기 제 2 질화막(9'), 상기 제 2 산화막(7') 및 상기 제 1 질화막(5')을 제거한다.Next, the second nitride film 9 ', the second oxide film 7' and the first nitride film 5 'are removed by a wet etching method.
다음, 상기 게이트 전도체(17) 외측의 반도체 기판(1)에 LDD(Lightly DopedDrain) 이온주입 공정을 진행하여 LDD 주입 영역(19)을 형성한다.Next, an LDD (Lightly DopedDrain) ion implantation process is performed on the semiconductor substrate 1 outside the gate conductor 17 to form the LDD implantation region 19.
다음, 스페이서 막을 증착한 다음 전면 식각 방법으로 상기 게이트 전도체(17) 양측에 스페이서(21)를 형성한다.Next, a spacer layer is deposited on both sides of the gate conductor 17 by depositing a spacer film and then etching the entire surface.
다음, 상기 스페이서(21) 외측의 반도체 기판(1)에 불순물을 이온주입 공정을 진행하여 소오스/드레인 영역(23)을 형성한 단계이다.Next, a source / drain region 23 is formed by performing an ion implantation process on the semiconductor substrate 1 outside the spacer 21.
도 2e에 도시된 공정은, 도 2d의 구조물을 이용하여 습식식각 방법으로 상기 제 1 산화막(3')을 식각하여 제 1 산화막(3")을 형성한다.In the process illustrated in FIG. 2E, the first oxide layer 3 ′ is etched by the wet etching method using the structure of FIG. 2D to form the first oxide layer 3 ″.
다음, 열처리 공정을 진행하여 카운터 도핑 영역(13'), LDD 주입 영역(19"), 소오스/드레인 영역(23')을 형성한다.Next, a heat treatment process is performed to form a counter doped region 13 ′, an LDD implanted region 19 ″, and a source / drain region 23 ′.
다음, 상기 구조물 위에 살리사이드(Salicide)(25)를 증착한 후, 어닐 공정을 실시하여 상기 게이트 전도체(17)와 소오스/드레인 영역(23')에 살리사이드막(25)을 증착한 단계이다.Next, after the salicide 25 is deposited on the structure, the salicide layer 25 is deposited on the gate conductor 17 and the source / drain regions 23 ′ by performing an annealing process. .
이상에서 설명한 바와 같이, 본 발명에 의한 반도체 소자의 제조 방법에 의하면, 추가적인 공정없이도 트랜지스터의 SCE와 DIBL의 효과를 줄일 수 있어 특성이 우수한 트랜지스터를 제조할 수 있다.As described above, according to the method of manufacturing a semiconductor device according to the present invention, it is possible to reduce the effects of SCE and DIBL of the transistor without additional steps, and thus to produce a transistor having excellent characteristics.
아울러 본 발명의 바람직한 실시예들은 예시의 목적을 위해 개시된 것이며, 당업자라면 본 발명의 사상과 범위 안에서 다양한 수정, 변경, 부가등이 가능할 것이며, 이러한 수정 변경등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims. something to do.
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