CN108962896B - Memory device - Google Patents
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- CN108962896B CN108962896B CN201811091933.0A CN201811091933A CN108962896B CN 108962896 B CN108962896 B CN 108962896B CN 201811091933 A CN201811091933 A CN 201811091933A CN 108962896 B CN108962896 B CN 108962896B
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- 239000000758 substrate Substances 0.000 claims abstract description 86
- 239000004065 semiconductor Substances 0.000 claims abstract description 62
- 230000015654 memory Effects 0.000 claims abstract description 49
- 238000005530 etching Methods 0.000 claims description 53
- 238000000034 method Methods 0.000 claims description 34
- 230000007547 defect Effects 0.000 claims description 27
- 230000000903 blocking effect Effects 0.000 claims description 12
- 230000005641 tunneling Effects 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims description 5
- 230000000149 penetrating effect Effects 0.000 abstract description 8
- 239000000463 material Substances 0.000 description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention relates to a memory, comprising: a substrate, wherein a storage stack structure is formed on the surface of the substrate; a channel hole penetrating the storage stack structure; and the bottom surface of the epitaxial semiconductor layer is connected with the substrate, and the distance between the bottom surface of the epitaxial semiconductor layer and the surface of the substrate is smaller than a preset value. The performance of the memory is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a memory.
Background
In recent years, flash (Memory) memories have been developed particularly rapidly. The flash memory has the main characteristics of long-term storage of stored information without power up, and has the advantages of high integration level, high access speed, easy erasing and rewriting, and the like, thereby being widely applied to various fields such as microcomputers, automatic control, and the like. In order to further increase the Bit Density (Bit Density) of the flash memory while reducing the Bit Cost (Bit Cost), three-dimensional flash memory (3D NAND) technology has been rapidly developed.
In the process of forming the 3D NAND memory, a stacked structure formed by stacking a sacrificial layer and an insulating layer on a surface of a substrate is required, and then the stacked structure is etched to form a channel hole, and a channel hole structure is formed in the channel hole to serve as a memory string. In the process of forming the channel hole structure, the substrate is usually over-etched, an opening is formed in the substrate, and the surface of the inner wall of the opening is easily damaged and oxidized in the process of forming the channel hole, so that an oxide layer is generated. The prior art generally performs a post-etch treatment (PET) on the bottom of the trench after forming the trench, and removes the oxide layer on the substrate surface at the bottom of the trench and repairs the damage on the substrate surface by a low-energy short-time ion etching process.
In order to avoid damage to the stacked structure of the sidewall of the channel hole, the post-etching treatment generally adopts an anisotropic etching process, and etching is performed along the direction perpendicular to the bottom of the channel hole. Therefore, the damage and the oxide layer on the bottom surface of the bottom of the opening at the bottom of the trench hole are easy to be removed, and the damage and the oxide layer on the surface of the side wall of the opening cannot be completely cleaned. In the subsequent process of forming the epitaxial semiconductor layer at the bottom of the channel hole, the side wall of the formed epitaxial semiconductor layer can generate defects such as holes and the like due to the fact that the surface of the side wall of the opening is provided with a damage or oxidation layer, so that the quality of the formed epitaxial semiconductor layer is affected. In addition, as the side wall of the epitaxial semiconductor layer is connected with the sacrificial layer at the side part of the channel hole, in the process of replacing the sacrificial layer by the metal gate, the metal gate material easily enters the hole of the side wall of the epitaxial semiconductor layer, so that the gate leakage problem of the bottom selection transistor of the memory is caused, and the performance of the memory is influenced.
Disclosure of Invention
The invention aims to solve the technical problem of providing a memory with improved performance.
The technical scheme of the invention provides a memory, which comprises the following components: a substrate, wherein a storage stack structure is formed on the surface of the substrate; a channel hole penetrating the storage stack structure; and the bottom surface of the epitaxial semiconductor layer is connected with the substrate, and the distance between the bottom surface of the epitaxial semiconductor layer and the surface of the substrate is smaller than a preset value.
Optionally, the bottom of the epitaxial semiconductor layer is located on the surface of the substrate.
Optionally, the bottom surface of the epitaxial semiconductor layer is located in the substrate, below the surface of the substrate.
Optionally, a distance between a bottom surface of the epitaxial semiconductor layer and a surface of the substrate is 100nm or less.
Optionally, the memory stack structure includes control gate structure layers and insulating layers alternately stacked, and a top portion of the epitaxial semiconductor layer is higher than the first control gate structure layer upward from the substrate surface.
Optionally, the top of the epitaxial semiconductor layer is lower than the second control gate structure layer upward from the substrate surface.
Optionally, the method further comprises: the functional side wall is positioned on the surface of the side wall of the channel hole; and the channel dielectric layer covers the functional side wall and fills the channel hole.
Optionally, the functional side wall includes: the semiconductor device comprises a charge blocking layer covering the side wall of the channel hole, a charge capturing layer covering the charge blocking layer, a tunneling layer covering the charge blocking layer and a channel layer covering the tunneling layer and connected with the epitaxial semiconductor layer.
Optionally, the method further comprises: and an array common source extending through the storage stack structure.
Optionally, the memory is a 3D NAND memory.
The bottom of the epitaxial semiconductor layer at the bottom of the memory channel hole structure is smaller in distance from the surface of the substrate, the epitaxial semiconductor layer is higher in quality, defects such as holes and the like are not easy to occur in the side wall, therefore, the performance of a bottom selection transistor formed by the control gate structure layer and the epitaxial layer semiconductor is improved, the problems such as electric leakage and the like are not easy to occur, and the performance of the memory is further improved.
Drawings
Fig. 1 to 8 are schematic structural views illustrating a memory forming process according to an embodiment of the invention.
Detailed Description
The following describes in detail embodiments of a memory and a method for forming the same provided by the present invention with reference to the accompanying drawings.
Referring to fig. 1 to 8, a schematic structure diagram of a memory forming process according to an embodiment of the invention is shown. In this embodiment, the memory formed is a 3D NAND memory.
Referring to fig. 1, a substrate 100 is provided, the substrate 100 has a first surface 11, and a stacked structure 110 is formed on the first surface 11 of the substrate 100.
The substrate 100 may be a single crystal silicon substrate, a Ge substrate, a SiGe substrate, SOI, GOI, or the like; suitable semiconductor materials may be selected as the substrate 100 according to the actual requirements of the device, and are not limited herein. In this embodiment, the substrate 100 is a monocrystalline silicon wafer.
The stack structure 110 includes an insulating layer 111 and a sacrificial layer 112 stacked on each other in a direction perpendicular to a surface of the substrate 100. In one embodiment, the material of the insulating layer 111 is silicon oxide, and the material of the sacrificial layer 112 is silicon nitride; in other embodiments, other suitable materials for the insulating layer 111 and the sacrificial layer 112 may be used. In another embodiment, the stacked structure 110 includes conductive layers and insulating layers alternately stacked, for example, the conductive layers may be control gates.
Referring to fig. 2, the stacked structure 110 is etched to form a channel hole 130 penetrating the stacked structure 110.
The stacked structure 110 may be etched to the surface of the semiconductor substrate 100 using a reactive ion etching process. In this embodiment, in the process of etching the stacked structure, the etching process is used to etch the stacked structure and the substrate by an etching selectivity ratio greater than 100, so that etching can be stopped in time after the stacked structure 110 is etched to the surface of the semiconductor substrate 100, and excessive etching on the substrate 100 is avoided.
The distance between the bottom surface of the channel hole 130 and the first surface 11 of the substrate 100 is smaller than a preset value, preferably, the preset value is 100nm.
In this embodiment, the bottom surface of the channel hole 130 is located in the substrate 100 and slightly lower than the first surface 11 of the substrate 100, and specifically, the distance between the bottom surface of the channel hole 130 and the first surface 11 of the substrate 100 is 50nm to 100nm.
In another embodiment, the bottom surface of the channel hole 130 exposes the first surface 11 of the substrate 100. In the process of etching the channel hole 130, no etching is performed on the substrate 100, so that the bottom of the channel hole 130 only exposes the first surface 11 of the substrate 100. The distance between the bottom surface of the channel hole 130 and the first surface 11 of the substrate 100 is 0.
During etching, the parameters of the etching process may be adjusted to avoid etching the substrate 100. The material layer in the stacked structure 100, particularly the gas having a higher etching selectivity to the insulating layer 111 is selected to etch the stacked structure 100, so that etching of the substrate 100 can be reduced when the insulating layer 111 at the bottommost layer is etched. In addition, the etching rate may be reduced when etching to the last insulating layer or layers 111 and the sacrificial layer 112 on the surface of the substrate 100, so that the etching can be stopped rapidly when etching to the first surface 11 of the substrate 100.
In a specific embodiment, C 4F8 is used as an etching gas, and is adjusted by combining parameters such as flow rate, air pressure temperature and the like of the gas, so that the insulating layer 111 and the sacrificial layer 112 have a higher etching selectivity relative to the substrate 100 in the etching process. Those skilled in the art can adjust the etching gas and the etching parameters in each direction according to the performance of the etching base station and the feature size of the channel hole, so as to realize higher etching selectivity to the stacked structure 110.
Referring to fig. 3, an etching post-treatment is performed on the bottom of the channel hole 130 to remove impurities and defects on the substrate surface at the bottom of the channel hole.
During the process of etching the channel hole 130, due to the bombardment effect of the plasma, etching damage is caused on the exposed surface of the substrate 100 at the bottom of the channel hole 130, and a natural oxide layer is formed, which is not beneficial to the subsequent epitaxial growth of the semiconductor layer at the bottom of the channel hole 130.
The defect layer 300 in fig. 3 is used to identify the defect, oxide layer, and other impurities that need to be removed from the bottom surface of the channel hole 130. In this embodiment, the defect layer 300 is removed by performing an post-etch treatment on the bottom surface of the channel hole 130.
The post-etching treatment may be an anisotropic etching process, specifically a plasma etching process, and the etching direction is perpendicular to the first surface 11 of the substrate 100 and faces the bottom of the channel hole 130. To remove the defect layer 300. Since the distance between the bottom surface of the channel hole 130 and the first surface 11 of the substrate 100 is smaller, the defect layer 300 is mainly located on the bottom surface parallel to the first surface 11 of the substrate 100, and the sides are fewer. Therefore, in the process of removing the defect layer 300 by using the anisotropic etching process, when the defect layer 300 on the bottom surface is removed, part of the plasma can bombard the defect layer 300 on the side wall due to the reflection of the plasma and the like, so that a small amount of the defect layer 300 on the side wall is removed.
In other embodiments, the etching direction of the post-etching treatment may be adjusted, so that the defect layer 300 on the sidewall and the bottom is further completely removed by slight lateral etching. The inclination angle of the lateral etching is low and can be 1-10 degrees, and the parameters of the etching process are easy to adjust and control.
The post-etching treatment process mainly adopts plasma to bombard the bottom surface of the channel hole 130 so as to remove impurities such as defects, natural oxide layers and the like. In order to avoid secondary damage to the bottom of the channel hole 130, the post-etching treatment process adopts low-power dry etching, reduces the energy of etching plasma and etching time, and can avoid secondary damage to the surface of the substrate 100 while removing the defect layer 300.
In another embodiment, in order to further remove the defect layer 300 at the bottom of the channel hole 130, before performing the post-etching treatment, an oxidation treatment may be performed on the surface of the substrate 100 at the bottom of the channel hole 130 to remove etching damage, and then the oxidation layer generated during the oxidation treatment is removed by the post-etching treatment.
Referring to fig. 4, after the defect layer 300 is removed, an epitaxial semiconductor layer 131 is formed on the substrate surface at the bottom of the channel hole 130.
An epitaxial semiconductor layer 131 is formed on the surface of the substrate 100 at the bottom of the channel hole 130 by using a selective epitaxial process. In this embodiment, the material of the epitaxial semiconductor layer 131 is silicon. After the surface of the substrate 100 at the bottom of the channel hole 130 is etched, the surface defects and the oxide layer are removed, so that the formed epitaxial semiconductor layer 131 has higher quality, fewer defects, higher quality of the interface between the bottom surface and the side wall of the channel hole 130, and no defects such as holes.
The top of the epitaxial semiconductor layer 131 is above the first sacrificial layer 112 upward from the first surface 11 of the substrate 100 and below the second sacrificial layer 112.
Referring to fig. 5, after the epitaxial semiconductor layer 131 is formed, functional side walls 132 are formed on the side wall surfaces of the channel holes 130; a channel dielectric layer 133 is formed to cover the functional sidewall 132 and fill the channel hole 130.
The functional side wall 132 includes a charge blocking layer covering the surface of the sidewall of the channel hole, a charge trapping layer covering the charge blocking layer, a tunneling layer covering the charge trapping layer, and a channel layer covering the tunneling layer and connected to the epitaxial semiconductor layer 131. In one embodiment, the material of the charge blocking layer is silicon oxide, the material of the charge trapping layer is silicon nitride, the material of the tunneling layer is silicon oxide, and the material of the channel layer is polysilicon.
The epitaxial semiconductor layer 131, the functional side wall 132 and the channel dielectric layer 133 form a channel hole structure penetrating the stack structure 110.
Referring to fig. 6, after the channel hole structure is formed, a gate line isolation groove 601 penetrating through the stacked structure 110 is formed; the sacrificial layer 112 is removed along the gate line spacer 601 to form openings 602 between adjacent insulating layers.
The sacrificial layer 112 is removed using a wet etch process to form the opening 602.
Referring to fig. 7, a control gate structure layer 702 is formed in the opening 602 (referring to fig. 6).
The source doped region 701 may be formed in the substrate 100 at the bottom of the gate line spacer 601 before the control gate structure layer 702 is formed.
The control gate structure layer 702 includes a gate dielectric layer covering the inner wall surface of the opening and a gate layer located on the surface of the gate dielectric layer and filling the opening 602.
The epitaxial semiconductor layer 131 sidewalls are connected to a first control gate structure layer 702 on the substrate 100. Because the epitaxial semiconductor layer 131 has higher formation quality, and the side wall has no defects such as holes, in the process of forming the control gate structure layer 702, the material of the control gate structure layer 702 cannot enter the epitaxial semiconductor layer 131, so that the interface quality between the control gate structure layer 702 and the epitaxial semiconductor layer 131 is higher, the problem of leakage of the bottom selection transistor formed by the first layer control gate structure layer 702 and the epitaxial semiconductor layer 131 is avoided, and the performance of the formed memory is improved.
Referring to fig. 8, an insulating sidewall 801 is formed on a sidewall surface of the gate line isolation trench 601 (refer to fig. 7), and a conductive layer 802 is filled in the gate line isolation trench 601, where the conductive layer 802 is connected to the source doped region 701.
The insulating sidewall 801 is used to isolate the conductive layer 802 from the control gate structure layer 702, and may be made of dielectric materials such as silicon oxide and silicon nitride. The conductive layer 802 may be made of polysilicon or a metal material such as W, cu, ag, etc.
In the forming process of the memory, the distance between the bottom surface of the formed channel hole and the first surface of the substrate is smaller than a preset value, so that the defects and impurities on the surface of the substrate on the bottom surface and the side wall of the channel hole can be completely removed in the etching post-treatment process, the quality of an epitaxial semiconductor layer formed at the bottom of the channel hole is improved, and the performance of the formed memory is further improved.
The embodiment of the invention also provides a memory.
Please refer to fig. 8, which is a schematic diagram of the structure of the memory. In this embodiment, the memory is a 3D NAND memory.
The memory comprises a substrate 100, wherein a memory stack structure is formed on the surface of the substrate 100, and comprises an insulating layer 111 and a control gate structure layer 702 which are sequentially stacked along the direction perpendicular to the surface of the substrate 100; a channel hole penetrating the storage stack structure; the bottom surface of the epitaxial semiconductor layer 131 is connected with the substrate 100, and the distance between the bottom surface of the epitaxial semiconductor layer 131 and the surface of the substrate 100 is smaller than a preset value, preferably 100nm.
In this embodiment, the bottom surface of the epitaxial semiconductor layer 131 is located in the substrate 100 below the first surface 11 of the substrate 100. The distance between the bottom surface of the epitaxial semiconductor layer 131 and the first surface 11 of the substrate 100 is 50nm to 100nm.
In another embodiment, the epitaxial semiconductor layer 131 is located on the first surface 11 of the substrate 100, and a distance between the bottom surface of the epitaxial semiconductor layer 131 and the first surface 11 of the substrate 100 is 0.
In this embodiment, the top of the epitaxial semiconductor layer 131 is higher than the first control gate structure layer 702 upward from the first surface 11 of the substrate 100, and the top of the epitaxial semiconductor layer 131 is lower than the second control gate structure layer 702 upward from the first surface 11 of the substrate 100. The first control gate structure layer 702 and the epitaxial layer semiconductor 131 constitute a bottom selection transistor of a memory.
The memory further comprises a functional side wall 132 positioned on the side wall surface of the channel hole; and a channel dielectric layer 133 covering the functional side wall 132 and filling the channel hole. The functional side wall 132 includes a charge blocking layer covering the surface of the sidewall of the channel hole, a charge trapping layer covering the charge blocking layer, a tunneling layer covering the charge trapping layer, and a channel layer covering the tunneling layer and connected to the epitaxial semiconductor layer 131. In one embodiment, the material of the charge blocking layer is silicon oxide, the material of the charge trapping layer is silicon nitride, the material of the tunneling layer is silicon oxide, and the material of the channel layer is polysilicon.
The epitaxial semiconductor layer 131, the functional side wall 132 and the channel dielectric layer 133 form a channel hole structure penetrating the stack structure 110.
Since the distance between the bottom surface of the epitaxial semiconductor layer 131 and the first surface 11 of the substrate 100 is small, the distance between the bottom surface of the channel hole to be formed and the first surface 11 is also small. In the process of forming the channel hole by etching, etching defects on the bottom surface of the channel hole are mainly concentrated on the bottom surface of the channel hole, the side wall is fewer, before the epitaxial semiconductor layer 131 is formed, the defects on the substrate at the bottom of the channel hole are easily removed completely through the post-etching treatment process, so that the deposition quality of the epitaxial semiconductor layer 131 is higher, defects such as holes are not easy to occur on the side wall of the epitaxial semiconductor layer 131, the performance of a bottom selection transistor formed by the control gate structure layer 702 of the first layer and the epitaxial layer semiconductor 131 is improved, the problem of electric leakage and the like is not easy to occur, and the performance of the memory is improved.
In this embodiment, the memory further includes: and an array common source extending through the storage stack structure. The array common source is formed in a gate line trench penetrating the storage stack structure, and includes an insulating sidewall 801 covering the gate line trench, and a conductive layer 802 filling the gate line trench. A source doped region 701 is formed in the substrate 100 at the bottom of the array common source, and the conductive layer 802 is connected to the source doped region 701.
The insulating sidewall 801 is used to isolate the conductive layer 802 from the control gate structure layer 702, and may be made of dielectric materials such as silicon oxide and silicon nitride. The conductive layer 802 may be made of polysilicon or a metal material such as W, cu, ag, etc.
The epitaxial semiconductor layer at the bottom of the channel hole structure of the memory is high in quality, defects such as holes and the like are not easy to occur in the side wall, so that the performance of a bottom selection transistor formed by the control gate structure layer and the epitaxial layer semiconductor can be improved, the problems of electric leakage and the like are not easy to occur, and the performance of the memory is further improved.
The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.
Claims (7)
1. A memory, comprising:
a substrate, wherein a storage stack structure is formed on a first surface of the substrate;
The distance between the bottom surface of the channel hole and the first surface of the substrate is 0, impurities and defects on the surface of the substrate at the bottom of the channel hole are removed through post-etching treatment, and the post-etching treatment is to etch the bottom of the channel hole by adopting an anisotropic etching process along an etching direction perpendicular to the first surface of the substrate;
And the bottom surface of the epitaxial semiconductor layer is connected with the substrate, and the distance between the bottom surface of the epitaxial semiconductor layer and the first surface of the substrate is 0.
2. The memory of claim 1, wherein the memory stack structure comprises alternating stacked control gate structure layers and insulating layers, the top of the epitaxial semiconductor layer being higher than the first control gate structure layer upward from the substrate surface.
3. The memory of claim 2 wherein the top of the epitaxial semiconductor layer is lower than the second control gate structure layer upward from the substrate surface.
4. The memory of claim 1, further comprising: the functional side wall is positioned on the surface of the side wall of the channel hole; and the channel dielectric layer covers the functional side wall and fills the channel hole.
5. The memory of claim 4, wherein the functional side wall comprises: the semiconductor device comprises a charge blocking layer covering the side wall of the channel hole, a charge capturing layer covering the charge blocking layer, a tunneling layer covering the charge blocking layer and a channel layer covering the tunneling layer and connected with the epitaxial semiconductor layer.
6. The memory of claim 1, further comprising: and an array common source extending through the storage stack structure.
7. The memory of claim 1, wherein the memory is a 3D NAND memory.
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| WO2020146051A1 (en) * | 2019-01-07 | 2020-07-16 | Sandisk Technologies Llc | Three-dimensional memory device containing a replacement buried source line and methods of making the same |
| CN109786387B (en) * | 2019-01-09 | 2023-10-17 | 长江存储科技有限责任公司 | Memory, forming method thereof and memory cell selection method |
| CN109767807A (en) * | 2019-01-16 | 2019-05-17 | 长江存储科技有限责任公司 | The method for testing resistance of 3D nand memory bit line |
| KR102674860B1 (en) | 2019-01-18 | 2024-06-12 | 양쯔 메모리 테크놀로지스 씨오., 엘티디. | Source contact structure and manufacturing method of 3D memory device |
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