CN109767807A - The method for testing resistance of 3D nand memory bit line - Google Patents
The method for testing resistance of 3D nand memory bit line Download PDFInfo
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- CN109767807A CN109767807A CN201910038841.4A CN201910038841A CN109767807A CN 109767807 A CN109767807 A CN 109767807A CN 201910038841 A CN201910038841 A CN 201910038841A CN 109767807 A CN109767807 A CN 109767807A
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- bit line
- nand memory
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Abstract
A kind of method for testing resistance of 3D nand memory bit line, it include: that failure wafer is provided, the failure wafer includes substrate and the 3D nand memory in substrate face, and the 3D nand memory includes several bit lines and several metal plugs connected corresponding to each bit line；More bit lines are chosen as target bit line, more root object bit lines are connected by metallic circuit；Substrate described in planarized back from substrate, until the exposure metal plug being connect with target bit line；Metal plug corresponding to target bit line is tested, the resistance value of target bit line is obtained.Test method of the invention can reduce the difficulty of test of 3D nand memory bit line resistance, and can guarantee the precision of test.
Description
Technical field
The present invention relates to field of semiconductor fabrication more particularly to a kind of method for testing resistance of 3D nand memory bit line.
Background technique
Nand flash memory is a kind of storage equipment more better than hard disk drive, with people pursue low in energy consumption, light weight and
The non-volatile memory product of excellent performance, is widely used in electronic product.Currently, the nand flash memory of planar structure is
The limit of nearly true extension reduces the carrying cost of every bit to further improve memory capacity, proposes 3D structure
3D nand memory.
In the manufacturing process of 3D nand memory, the parameter estimator of various Primary Components and structure be one very
Important link is even more important for design error correction, processing procedure optimization and failure analysis, however as device and test structure
Size constantly reduces, and is also filled with challenge to the observation of object construction.
The bit line of 3D nand memory is a crucial structure, when carrying out failure testing and analysis, the resistance of bit line
It is an important reference parameter, but the existing bit line to 3D nand memory carries out difficulty when resistance test larger, resistance
Measuring accuracy not can guarantee.
Summary of the invention
The technical problem to be solved by the present invention is to how reduce 3D nand memory bit line resistance difficulty of test,
Improve the precision of test.
The present invention provides a kind of method for testing resistance of 3D nand memory bit line, comprising:
Failure wafer is provided, the failure wafer includes substrate and the 3D nand memory in substrate face, described
3D nand memory includes several bit lines and several metal plugs connected corresponding to each bit line；
More bit lines are chosen as target bit line, more root object bit lines are connected by metallic circuit；
Substrate described in planarized back from substrate, until the exposure metal plug being connect with target bit line；
Metal plug corresponding to target bit line is tested, the resistance value of target bit line is obtained.
Optionally, the metallic circuit is formed using focused ion beam technique.
Optionally, the ion that the focused ion beam technique uses is metal ion.
Optionally, the metal ion is tungsten ion, cobalt ions, titanium ion or copper ion.
Optionally, the 3D nand memory further includes that the separation layer being located in substrate face and control gate are alternately laminated
Stacked structure, the channel hole in stacked structure, the storage organization in channel hole；Cover the medium of stacked structure
Layer.
Optionally, several bit lines are located in the dielectric layer on stacked structure, and several bit lines are parallel to each other, and each
Bit line is connected by a metal plug with corresponding storage organization.
Optionally, when forming metallic circuit by focused ion beam technique, focused-ion-beam lithography dielectric layer, shape are first passed through
At the opening on exposure more root object bit lines surface, focused ion beam then is continued through in open bottom and forms metallic circuit, it will
More root object bit lines are connected.
Optionally, the quantity of the target bit line is more than or equal to 3.
Optionally, metal plug corresponding to target bit line is tested using nano-probe platform.
Optionally, described that metal plug corresponding to target bit line is tested, obtain the resistance process of target bit line
It include: to apply test voltage two-by-two to three root object bit lines to obtain corresponding test resistance；According to test voltage and test resistance
Calculate the resistance for obtaining every root object bit line.
Optionally, chemical mechanical milling tech is used from failure wafer described in planarized back.
Optionally, the length of the bit line is 0.5~8 millimeter, and the width of bit line is 30~80 nanometers, between adjacent bit lines
Away from for 15~25nm.
Compared with prior art, technical solution of the present invention has the advantage that
The method for testing resistance of 3D nand memory bit line of the invention, during the test, by metallic circuit by mesh
The connection of mark line, without grinding to substrate face, thus when can prevent from grinding substrate face, bring bit line is ground
Abrasion wound, and the metal plug that target bit line connects is exposed to by the back side of planarized substrate, this process will not be right
Target bit line brings damage, after exposing metal plug, by testing metal plug, and obtains the electricity of target bit line
Resistance value, thus test method of the invention can reduce the difficulty of test of 3D nand memory bit line resistance, and can guarantee survey
The precision of examination.
Further, it can easy and quickly be realized the electrical connection of more root object bit lines by focused ion beam technique, and
And focused ion beam technique can accurately position the position at the place of target bit line, prevent from causing to damage to target bit line.
Detailed description of the invention
Fig. 1-Fig. 6 is the schematic diagram of the section structure of the resistance test process of 3D of embodiment of the present invention nand memory bit line.
Specific embodiment
As described in the background art, it is larger to carry out difficulty when resistance test for the existing bit line to 3D nand memory, resistance
Measuring accuracy not can guarantee.
The study found that the bit line structure design of existing 3D nand memory belongs to special size structure, the length of bit line
Degree reaches several millimeters, and its width only has tens nanometers, and the space between bit line is smaller, only less than 20 nanometers, when need
When directly observing this structural resistance, existing method is that the sample that will fail is ground to always from top layer metallic layer or dielectric layer
Need target bit line to be tested, then tested, but since bitline length is too long, width is too thin, cause grinding when
It waits, is easy grinding unevenly, extreme situation is exactly that target bit line overgrinding is led to target bit-line failure, is unable to test, and is surveyed
The difficulty of examination is larger, or even if being tested, the precision of test not can guarantee yet.
For this purpose, the present invention provides a kind of method for testing resistance of 3D nand memory bit line, during the test, lead to
It crosses metallic circuit to connect target bit line, without grinding substrate face, thus can prevent from grinding substrate face
When bring bit line grinding damage, and by the back side of planarized substrate be exposed to target bit line connection metal plug, this
One process will not bring damage, after exposing metal plug, by testing metal plug, and obtain to target bit line
The resistance value of target bit line is obtained, thus the testing scheme invented can reduce the difficulty of test of 3D nand memory bit line resistance,
And it can guarantee the precision of test.
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.When describing the embodiments of the present invention, for purposes of illustration only, schematic diagram can disobey general ratio
Example makees partial enlargement, and the schematic diagram is example, should not be limited the scope of the invention herein.In addition, in reality
It should include the three-dimensional space of length, width and depth in the production of border.
Fig. 1-Fig. 6 is the schematic diagram of the section structure of the resistance test process of 3D of embodiment of the present invention nand memory bit line.
With reference to Fig. 1, failure wafer 21 is provided, the failure wafer 21 is including substrate 201 and on 201 front of substrate
3D nand memory, the 3D nand memory include several bit lines 203 and several gold connected corresponding to each bit line 203
Belong to plug 204.
Shown failure wafer 21 is one or more electricity in 3D nand memory manufacturing process or after completing
Parameter is unsatisfactory for the wafer of technique requirement or design requirement or existing defects.Failure testing is carried out to failure wafer 21 or is divided
Analysis carries out error correction with the design to 3D nand memory or optimizes the manufacture craft of 3D nand memory.In the present embodiment,
The failure testing of progress or analysis are the test or analysis to the resistance of the bit line of 3D nand memory.
The failure wafer 21 includes substrate 201, and the front of the substrate 201 is formed with 3D nand memory.3D
Nand memory is made by existing semiconductor fabrication process.
The material of the substrate 201 is monocrystalline silicon (Si), monocrystalline germanium (Ge) or SiGe (GeSi), silicon carbide (SiC)；?
It can be silicon-on-insulator (SOI), germanium on insulator (GOI)；It or can also be other materials, such as GaAs etc. III-
V compounds of group.In the present embodiment, the material of the substrate 201 is monocrystalline silicon (Si).
The 3D nand memory further includes the separation layer and the alternately stacked heap of control gate on 201 front of substrate
Stack structure (not shown), the channel hole (not shown) in stacked structure, the storage organization in channel hole
(not shown)；Cover the dielectric layer 202 of stacked structure.
For the separation layer for mutually isolated between control gate, the material of the separation layer can be silica, nitridation
One of silicon, silicon oxynitride, fire sand.The material of the control gate is metal (such as W, Al, Cu, Ti, Ag, Au, Pt, Ni
It is one of or several) or doping semiconductor material (as doping polysilicon or germanium).
The channel hole exposes the surface of substrate, and storage organization is formed in channel hole, and the storage organization at least wraps
Electric charge capture layer and channel layer are included, in one embodiment, the electric charge capture layer is ONO layer, i.e. silicon oxide-silicon nitride-oxidation
The lamination of silicon, channel layer are polysilicon layer.In a specific embodiment, ONO layer, more can be successively deposited in channel through-hole
Crystal silicon layer and silicon oxide layer, to form storage organization.
In the present embodiment, several bit lines 203 are located at stacked structure (separation layer and the alternately stacked stacking knot of control gate
Structure) on dielectric layer 202 in, several bit lines 203 are parallel to each other, and each bit line 203 by a metal plug 204 with it is corresponding
Storage organization connection.
In the present embodiment, the top surface of the bit line 203 is not covered by dielectric layer 202, the top table of the bit line 203
Face is flushed with the surface of dielectric layer 202, and the dielectric layer 202 can be one or more layers stacked structure.In other embodiments,
The bit line 203 is fully located in dielectric layer 202, and the top surface of the bit line 203 is lower than the surface of dielectric layer 202.At it
In his embodiment, several layers interlayer dielectric layer can also be formed on the bit line 203, it can be with shape in corresponding interlayer dielectric layer
At metal layer and metal plug.
In the present embodiment, every bit line 203 can be connected by a metal connecting structure 205 with corresponding metal plug 204
It connects, the metal connecting structure 205 can be the combination of one or both of via plug, metal layer.In other embodiments
In, every bit line can be connected directly with corresponding metal plug.
The quantity of the bit line 203 is only illustrated using 7 bit lines as example in Fig. 1 at least more than 3.
In one embodiment, the length of the bit line 203 is 0.5~8 millimeter, and the width of bit line 203 is 30~80 nanometers,
The spacing of adjacent bit lines 203 is 15~25nm, and 203 length of bit line formed in the application is longer, width and the equal very little of spacing, existing
Some test methods easily bring grinding damage to bit line 203 when being ground, thus the application is to existing test method
It is improved, to solve the problems, such as this.
With reference to Fig. 2, chooses more bit lines 203 and be used as target bit line (203a, 203b, 203c), by more root object bit lines
(203a, 203b, 203c) is connected by metallic circuit 206.
The target bit line is that tester arbitrarily chooses or rule of thumb chooses.The target bit line
It can be chosen according to corresponding alternative condition, for example select the bit line of intermediate specific region or edge specific region as mesh
Mark line.
In order to carry out the measurement of resistance, the quantity of the target bit line 203 of selection is at least three, and by forming metal
More root object bit lines are electrically connected by route 206.
In the present embodiment, chooses three bit lines 203 in Fig. 2 and be used as target bit line, respectively target bit line 203a, target position
Line 203b, target bit line 203c.
After determining target bit line, according to layout analysis, it can know and connect with target bit line (203a, 203b, 203c)
The corresponding position of metal plug 204.
In the present embodiment, the metal plug that is correspondingly connected with target bit line 203a, target bit line 203b, target bit line 203c
Respectively metal plug 204a, metal plug 204b, metal plug 204c.
Metallic circuit 206 is formed by target bit line 203a, target bit line 203b, the 203c connection of target bit line, the present embodiment
In, the metallic circuit 206 is formed using focused ion beam (Focused Ion beam, FBI) technique.The focused ion beam
For the ion that technique uses for metal ion, the metal ion is tungsten ion, cobalt ions, titanium ion or copper ion, the present embodiment
In, the metal ion is tungsten ion, specifically, the focused ion beam (Focused Ion beam, FBI) technique is by liquid
The ion beam of state metal ion source transmitting is used as incident beam, irradiation failure crystal column surface after accelerating to focus, and then is carved
Erosion and depositing operation.
In one embodiment, when being also formed with multilayer interlayer dielectric layer on the bit line, pass through focused ion beam technique
The interlayer dielectric layer on target bit line (203a, 203b, 203c) is first removed (if being also formed with metal layer on interlayer dielectric layer
And/or if metal plug, the metal layer and/or metal in interlayer dielectric layer are also removed accordingly by focused ion beam technique
Plug), the opening for exposing the surface target bit line (203a, 203b, 203c) is formed in interlayer dielectric layer；After forming opening,
Continue focused ion beam technique to be formed in open bottom by target bit line 203a, target bit line 203b, target bit line 203c
The metallic circuit 206 of connection.Thus the application easy and can be realized quickly by more root objects by focused ion beam technique
Bit line (203a, 203b, 203c) electrical connection, and focused ion beam technique can accurately position target bit line (203a,
203b, 203c) place position, prevent that target bit line (203a, 203b, 203c) is caused to damage.
With reference to Fig. 3, substrate described in the planarized back from substrate 201 (referring to Fig. 2), until exposing described and target bit line
The metal plug (204a, 204b, 204c) of (203a, 203b, 203c) connection.
The planarization uses chemical mechanical milling tech.
In other embodiments, the flatening process can be the combination of chemical mechanical milling tech and etching technics,
Specifically, first planarizing the back side of the substrate 201 using chemical mechanical milling tech；Then part is removed using etching technics
Substrate 201 and the device layer of the bottom metal plug (204a, 204b, 204c), formation expose metal plug (204a, 204b,
Groove 204c).
With reference to Fig. 3 and Fig. 4, to metal plug corresponding to target bit line (203a, 203b, 203c) (204a, 204b,
It 204c) is tested, obtains the resistance value of target bit line.
In one embodiment, to metal plug corresponding to target bit line (203a, 203b, 203c) (204a, 204b,
It 204c) is tested, the resistance process for obtaining target bit line includes: to apply test voltage two-by-two to three root object bit lines to obtain phase
The test resistance answered；The resistance for obtaining every root object bit line is calculated according to test voltage and test resistance.
Specifically, the resistivity measurements of the bit line are carried out using tester table 301, the tester table can be nanometer
Probe station, the tester table include probe 31 and probe 32, and when testing, probe 31 and probe 32 are separately connected metal
Plug 204a and metal plug 204b (referring to Fig. 4), then applies test voltage V1, obtains test electric current I1；Then probe 31
It is separately connected metal plug 204b and metal plug 204c with probe 32, then applies test voltage V2, obtains test electric current I2；
Then probe 31 and probe 32 are separately connected metal plug 204a and metal plug 204c, then apply test voltage V3, obtain
Test electric current I3；It carries out calculating the resistance value for obtaining target bit line.
Calculating process is as follows:
Rbl_01+Rbl_02=V1/I1=R1
Rbl_02+Rbl_03=V2/I2=R2
Rbl_01+Rbl_03=V3/I3=R3
Solving equations obtain: Rbl_01=(R1+R3-R2)/2
Rbl_02=(R1+R2-R3)/2
Rbl_03=(R2+R3-R1)/2
Rbl_01 is the resistance of target bit line 203a in above-mentioned formula, and Rbl_02 is the resistance of target bit line 203b, Rbl_
03 is the resistance of target bit line 203c, and R1 is obtained by V1/I1, and R2 is obtained by V2/I2, and R3 is obtained by V3/I3.
Although above-mentioned measurement result value includes the electricity of metal plug (204a, 204b, 204c) and metal connecting structure 205
Resistance value, but the resistance value (several hundred ohms) of metal plug (204a, 204b, 204c) and metal connecting structure 205 is relative to mesh
Resistance value (hundreds of thousands ohm) very little of mark line (203a, 203b, 203c), can be ignored.
It should be noted that in other embodiments, substrate described in the planarized back from substrate 201 (referring to Fig. 2), directly
To the exposure metal plug (204a, 204b, 204c) being connect with target bit line (203a, 203b, 203c), can use
The resistance of the test method measurement bit line of other resistance.
The method for testing resistance of the 3D nand memory bit line of the embodiment of the present invention passes through metal wire during the test
Road connects target bit line, without being ground to substrate face, thus bring when can prevent from grinding substrate face
Bit line grinding damage, and the metal plug that target bit line connects, this process are exposed to by the back side of planarized substrate
It will not bring damage, after exposing metal plug, by testing metal plug, and obtain target position to target bit line
The resistance value of line, thus the test method of the embodiment of the present invention can reduce the difficulty of test of 3D nand memory bit line resistance,
And it can guarantee the precision of test.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (12)
1. a kind of method for testing resistance of 3D nand memory bit line characterized by comprising
Failure wafer is provided, the failure wafer includes substrate and the 3D nand memory in substrate face, the 3D
Nand memory includes several bit lines and several metal plugs connected corresponding to each bit line；
More bit lines are chosen as target bit line, more root object bit lines are connected by metallic circuit；
Substrate described in planarized back from substrate, until the exposure metal plug being connect with target bit line；
Metal plug corresponding to target bit line is tested, the resistance value of target bit line is obtained.
2. the method for testing resistance of 3D nand memory bit line as described in claim 1, which is characterized in that the metal wire
Road is formed using focused ion beam technique.
3. the method for testing resistance of 3D nand memory bit line as claimed in claim 2, which is characterized in that it is described focus from
The ion that beamlet technique uses is metal ion.
4. the method for testing resistance of 3D nand memory bit line as claimed in claim 3, which is characterized in that the metal from
Son is tungsten ion, cobalt ions, titanium ion or copper ion.
5. the method for testing resistance of 3D nand memory bit line as claimed in claim 3, which is characterized in that the 3D NAND
Memory further includes the separation layer and the alternately stacked stacked structure of control gate in substrate face, in stacked structure
Channel hole, the storage organization in channel hole；Cover the dielectric layer of stacked structure.
6. the method for testing resistance of 3D nand memory bit line as claimed in claim 5, which is characterized in that several positions
Line is located in the dielectric layer on stacked structure, and several bit lines are parallel to each other, and each bit line is by a metal plug and accordingly
Storage organization connection.
7. the method for testing resistance of 3D nand memory bit line as claimed in claim 6, which is characterized in that by focus from
When beamlet technique forms metallic circuit, focused-ion-beam lithography dielectric layer is first passed through, forms exposure more root object bit lines surface
Then opening continues through focused ion beam in open bottom and forms metallic circuit, more root object bit lines are connected.
8. the method for testing resistance of 3D nand memory bit line as described in claim 1, which is characterized in that the target position
The quantity of line is more than or equal to 3.
9. the method for testing resistance of 3D nand memory bit line as claimed in claim 8, which is characterized in that visited using nanometer
Needle platform tests metal plug corresponding to target bit line.
10. the method for testing resistance of 3D nand memory bit line as claimed in claim 9, which is characterized in that described to target
Metal plug corresponding to bit line is tested, and the resistance process for obtaining target bit line includes: to apply two-by-two to three root object bit lines
Test voltage is added to obtain corresponding test resistance；The electricity for obtaining every root object bit line is calculated according to test voltage and test resistance
Resistance.
11. the method for testing resistance of 3D nand memory bit line as described in claim 1, which is characterized in that flat from the back side
Change the failure wafer using chemical mechanical milling tech.
12. the method for testing resistance of 3D nand memory bit line as described in claim 1, which is characterized in that the bit line
Length is 0.5~8 millimeter, and the width of bit line is 30~80 nanometers, and the spacing of adjacent bit lines is 15~25nm.
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