CN111243974B - Method for calibrating short circuit between 3D NAND bit line and word line - Google Patents
Method for calibrating short circuit between 3D NAND bit line and word line Download PDFInfo
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- CN111243974B CN111243974B CN202010047211.6A CN202010047211A CN111243974B CN 111243974 B CN111243974 B CN 111243974B CN 202010047211 A CN202010047211 A CN 202010047211A CN 111243974 B CN111243974 B CN 111243974B
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- 238000000034 method Methods 0.000 title claims abstract description 78
- 239000000523 sample Substances 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 230000008569 process Effects 0.000 claims description 29
- 238000010884 ion-beam technique Methods 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 239000010937 tungsten Substances 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 4
- 230000009471 action Effects 0.000 claims description 3
- 238000007737 ion beam deposition Methods 0.000 claims 1
- 238000012937 correction Methods 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 230000001965 increasing effect Effects 0.000 abstract description 4
- 238000001514 detection method Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 77
- 241000226585 Antennaria plantaginifolia Species 0.000 description 9
- 238000012827 research and development Methods 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 238000011161 development Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
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- 239000011247 coating layer Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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Abstract
The invention provides a method for calibrating short circuit of a 3D NAND bit line and a word line, which comprises the following steps: determining a target address, and determining a target word line layer according to the target address; electrically connecting all word line layers below the target word line layer and applying a voltage capable of opening a channel layer of the channel structure; electrically connecting the first probe with the target word line layer, and electrically connecting the second probe with the conductive layer on the substrate; and applying hot spot grabbing conditions on the first probe and the second probe, and positioning the failure hot spot by using a light emission microscope. The method of the invention opens the channel layer in the channel structure by connecting all the word line layers below the target word line layer and applying a voltage, so that the channel resistance is reduced by several orders of magnitude, the current of the whole loop is increased, the failure signal is enhanced, and the light emission microscope equipment can successfully perform failure positioning. The method of the invention can carry out error correction in advance, shorten the detection period and improve the production efficiency.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a method for calibrating short circuits of a 3D NAND bit line and a word line.
Background
In the development process of semiconductor technology, the research and development of products are very important links, the research and development speed of the products directly determines the market competitiveness of the products, and in the research and development stage, the error correction can be rapidly carried out in advance, so that the research and development period can be greatly shortened, and the market competitiveness of the products can be improved. In recent years, 3D NAND memory technology is developed vigorously and has strong market competition, and whether advanced products can be developed successfully or not before other manufacturers will directly determine enterprise development, so technicians are urgently required to establish various early error correction schemes to shorten the development cycle and improve the product market competitiveness.
The 3D NAND product is special in structural design, compared with other products, the length of the word line is extremely large, even reaches several millimeters, and the product with the structure is of a vertical stacking structure, so that the problem that the word line is short-circuited with the bit line and the source end is very easy to occur. In the prior art, the light emission microscope can perform failure positioning on a short-circuit position with large leakage current, but cannot perform accurate failure positioning on a short-circuit position with small leakage current.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a method for calibrating the short between a 3D NAND bit line and a word line, so as to solve the problem that the conventional method cannot perform failure location for a short position with small leakage current.
To achieve the above and other related objects, the present invention provides a method for calibrating bit line to word line shorts of a 3D NAND, the 3D NAND comprising: a substrate; a plurality of word line layers and a plurality of insulating layers alternately stacked on the substrate; a channel structure extending through the plurality of word line layers and the plurality of insulating layers and electrically coupled to the substrate, the method comprising:
determining a target address, and determining a target word line layer according to the target address;
electrically connecting all word line layers below the target word line layer and applying a voltage capable of opening a channel layer of a channel structure;
electrically connecting a first probe with the target word line layer, and electrically connecting a second probe with the conductive layer of the substrate;
and applying hot spot grabbing conditions on the first probe and the second probe, and positioning the failure hot spot by using a light emission microscope.
As an alternative of the present invention, the 3D NAND further includes a plurality of contact plugs electrically connected to ends of the word line layers of the respective layers, and ends of the corresponding contact plugs of all word line layers below the target word line layer are electrically connected through a conductive structure.
As an alternative of the invention, the conductive structure is a conductive pad deposited by the action of a focused ion beam.
As an alternative to the present invention, the conductive pad is formed by a focused ion beam deposited layer of tungsten conductive material.
As an alternative of the invention, a third pincushion is also provided on the conductive structure.
As an alternative of the present invention, the step of electrically connecting all word line layers below the target word line layer and applying a voltage capable of opening a channel structure includes electrically connecting a third probe to the third pad and applying the voltage capable of opening a channel layer of a channel structure through the third probe.
As an alternative of the present invention, the 3D NAND further includes a plurality of contact plugs electrically connected to the plurality of word line layers, respectively, and the method further includes a process of forming first pin pads on the corresponding contact plugs of the target word line layer.
As an alternative of the present invention, the 3D NAND further includes a contact plug electrically connected to the conductive layer of the substrate, and the method further includes a process of forming a second needle pad on the contact plug of the substrate.
As an alternative to the present invention, the needle pad is grown using a method of wire repair.
As an alternative of the present invention, the 3D NAND further includes a plurality of contact plugs electrically connected to the plurality of word line layers and the substrate, respectively, and the process further includes a process of grinding the target sample until the contact plugs of the respective word line layers and the contact plugs of the substrate are exposed before the target address is found.
As an alternative of the present invention, the 3D NAND further includes a plurality of contact plugs electrically connected to the plurality of word line layers and the substrate, respectively, and the process further includes electrically connecting the first probe to the contact plug of the target word line layer and electrically connecting the second probe to the contact plug of the substrate.
As an alternative of the present invention, a voltage of 6-8V is applied to all word line layers below the target word line layer for opening the channel structure.
As an alternative of the present invention, the process further includes a process of recording the failure location after the failure hotspot is located.
As an alternative of the present invention, the process further comprises a process of slicing the target address after the failed hotspot is located.
As described above, the present invention provides a method for calibrating a 3D NAND bit line to word line short, which opens a channel by electrically connecting all word line layers below a target word line layer and applying a voltage capable of opening a channel layer of a channel structure, so that the channel resistance is reduced by several orders of magnitude, thereby increasing the entire loop current, enhancing a fail signal, and thus a light emission microscope device can smoothly perform fail location. The method of the invention can carry out error correction in advance, shorten the detection period and improve the production efficiency.
Drawings
FIG. 1 is a schematic diagram showing the installation position of a probe when a 3D NAND bit line and word line short circuit position is calibrated by the method of the invention;
FIG. 2 shows yet another perspective view of a failure location f for a 3D NAND;
FIG. 3 is a flow chart of an embodiment of the method of the present invention;
fig. 4 is a schematic diagram showing the installation positions of the first probe 2a and the second probe 2b in the conventional failure calibration method according to the present invention.
Description of the element reference numerals
10. Substrate
20. Channel structure
30/40 contact plug
301. Second needle pad
401. Conductive structure
402. First needle pad
50. Word line layer
501. Target wordline layer
2a first probe
2b second Probe
2c third Probe
f position of failure
Detailed Description
The 3D NAND product is special in structural design, compared with other products, the length of the word line is extremely large, even reaches several millimeters, and the product with the structure is of a vertical stacking structure, so that the problem that the word line is short-circuited with the bit line and the source end is very easy to occur.
For the problem of short circuit of word lines and bit lines of a 3D NAND product, the existing method is to use a nano probe table to measure suspected word lines and a substrate and then use a light emission microscope device to perform failure positioning.
As shown in fig. 4, when the word line and the bit line of the 3D NAND product are shorted at the failure position f, the conventional failure calibration method is to use the first probe 2a and the second probe 2b to respectively contact the contact plug 40 connected to the target word line layer 501 and the contact plug 30 of the substrate 10, and then use the light emission microscope to apply the hot spot capture condition to perform failure positioning. Therefore, the invention provides a method for calibrating short circuit of a 3D NAND bit line and a word line, which is used for solving the problem that the existing method cannot perform failure positioning on a short circuit position with small leakage current.
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 3. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in FIGS. 1-3, the present invention provides a method for calibrating bit line to word line shorting for a 3D NAND product, the 3D NAND comprising: a substrate 10; a plurality of word line layers 50 and a plurality of insulating layers 60 alternately stacked on the substrate; a channel structure 20 extending through the plurality of word line layers 50 and the plurality of insulating layers 60 and electrically coupled to the substrate 10, the method comprising the process of:
determining a target address, and determining a target word line layer 501 according to the target address;
electrically connecting all word line layers below the target word line layer 501 and applying a voltage capable of opening the channel structure 20;
electrically connecting the first probe 2a to the target word line layer 501 and electrically connecting the second probe 2b to a conductive layer on the substrate 10;
and applying a hot spot grabbing condition on the first probe 2a and the second probe 2b, and carrying out failure hot spot positioning by using a light emission microscope.
The invention relates to a method for calibrating a short circuit between a 3D NAND bit line and a word line, which is characterized in that all word line layers below a target word line layer 501 are connected and a voltage capable of opening a channel layer of a channel structure is applied, so that a channel is opened, the channel resistance is reduced by several orders of magnitude, the current of the whole loop is increased, a failure signal is enhanced, and the light emission microscope equipment can be used for successfully positioning failure. The method of the invention can carry out error correction in advance, shorten the detection period and improve the production efficiency.
It should be noted that, the sidewall of the channel structure in the 3D NAND according to the present invention may include, from outside to inside, a barrier layer, a charge trapping layer, a tunneling layer, and a channel layer, which are stacked in sequence, but as a common structure on the existing NAND, no specific description is given here.
As an alternative of the present invention, the 3D NAND in this embodiment further includes a plurality of contact plugs electrically connected to end portions of the word line layers of the respective layers, respectively; the ends of corresponding contact plugs 40 of all word line layers below the target word line layer are electrically connected through conductive structure 401.
As an alternative to the present invention, the conductive structure 401 is a conductive pad deposited under the action of a focused ion beam.
In principle, the conductive structure 401 in the present invention may be any electrical connection structure capable of achieving electrical connection with a word line layer below a target word line layer, and preferably, the material of the conductive structure 401 (conductive pad) in the present invention may be a commonly used conductive layer material capable of achieving needle insertion in the existing semiconductor field, but as an alternative to the present invention, the conductive structure 401 in the present embodiment is formed by the focused ion beam deposited tungsten conductive material layer.
In consideration of convenience of operation, in this embodiment, a third pincushion capable of being pincered is further disposed on the conductive structure 401, and the third pincushion may be a local region of the conductive structure 401, or may be the entire conductive structure 401. In this embodiment, any position on the entire conductive structure 401 can be used for needle insertion. The step of electrically connecting all word line layers below the target word line layer and applying a voltage capable of opening a channel structure further comprises electrically connecting a third probe 2c to the third pad (i.e., conductive structure 401) and applying the voltage capable of opening a channel layer of a channel structure through the third probe 2 c.
The electrical connection manner of the first probe 2a and the target word line layer in the method of the present invention is not limited, but as an alternative of the present invention, the method further includes a process of forming a first pad 402 for the first probe 2a to prick on the corresponding contact plug 40 of the target word line layer in this embodiment. The first probe 2a is pricked on the first probe pad 402 and electrically connected to the contact plug 40 of the target word line layer 501.
The electrical connection manner of the second probe 2b and the conductive layer of the substrate 10 in the method of the present invention is also not limited in principle, but as an alternative of the present invention, the 3D NAND further includes a contact plug 30 electrically connected to the conductive layer of the substrate 10, and the method further includes a process of forming a second pad 301 for the second probe 2b to pin on the contact plug 30 of the substrate 10, and the second probe 2b is pinned on the second pad 301 and electrically connected to the contact plug 30 of the substrate 10.
As an alternative of the present invention, the manufacturing processes of the first pincushion 402, the second pincushion 301 and the third pincushion 401 are not limited, and in this embodiment, the first pincushion 402, the second pincushion 301 and the third pincushion 401 are all formed by using a circuit repairing method.
Considering that the contact plug 40 of each word line layer of the target sample and the contact plug 30 of the substrate 10 may be covered with an insulating layer or other coating layer that affects the electrical connection effect, the process further includes a process of grinding the target sample until the contact plug 40 of each word line layer and the contact plug 30 of the substrate 10 are exposed before the target address is found, as an alternative of the present invention.
The contact plug of each word line layer and the contact plug of the substrate in the present invention may be plug structures capable of electrically contacting with the word line layer and the substrate, such as a tungsten plug, a copper plug, and the like.
The range of the voltage applied to the third probe 2c in the present invention is not limited in principle as long as it can open the channel structure 20, but preferably, the voltage of the channel layer capable of opening the channel structure in this embodiment is 6 to 8V, which may be any value of 6 to 8V, such as 6V, 7V, or 8V. 6-8V can ensure effective opening of the channel and prevent damage to the components caused by overlarge voltage.
In order to facilitate control after the location of the failed hotspot, as an alternative of the present invention, the process further includes a process of recording the failed position f after the location of the failed hotspot and a process of slicing the target address.
It should be noted that the determining process of the target address and the target word line layer in the present invention is not limited, but as an example of the present invention, the target word line layer in this embodiment is obtained by testing with a testing machine, and the testing process of the testing machine and the process of performing the failed hot spot positioning by applying the normal hot spot capturing condition to the first probe and the second probe of the light emission microscope are all the existing means, and are not described herein again.
In summary, the method for calibrating the short circuit between the 3D NAND bit line and the word line of the present invention uses the focused ion beam to connect the contact plugs of all other layers except the failed word line layer with the conductive material tungsten, and then applies a voltage sufficient to open the channel layer of the channel structure on these layers, so that the resistance from the target word line (temperature rise) to the substrate contact plug is reduced, thereby increasing the leakage current, so that the light emission microscope device can calibrate the failure point smoothly. Therefore, the invention effectively overcomes some practical problems in the prior art, thereby having high utilization value and use significance.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (14)
1. A method for calibrating 3D NAND bit line to word line shorting, the 3D NAND comprising: a substrate; a plurality of word line layers and a plurality of insulating layers alternately stacked on the substrate; a channel structure extending through the plurality of word line layers and the plurality of insulating layers and electrically coupled to the substrate, the method comprising:
determining a target address, and determining a target word line layer according to the target address;
electrically connecting all word line layers below the target word line layer and applying a voltage capable of opening a channel layer of a channel structure;
electrically connecting a first probe with the target word line layer and electrically connecting a second probe with the conductive layer of the substrate;
and applying hot spot grabbing conditions on the first probe and the second probe, and positioning the failure hot spot by using a light emission microscope.
2. The method for calibrating 3D NAND bit line to word line shorting of claim 1, wherein: the 3D NAND further comprises a plurality of contact plugs electrically connected with the ends of the word line layers of each layer respectively, and the ends of the corresponding contact plugs of all the word line layers below the target word line layer are electrically connected through a conductive structure.
3. The method for calibrating 3D NAND bit line to word line shorting of claim 2, wherein: the conductive structure is a conductive pad deposited under the action of a focused ion beam.
4. The method for calibrating 3D NAND bit line to word line shorts of claim 3, wherein the conductive pad is formed by focused ion beam deposition of a layer of tungsten conductive material.
5. The method for calibrating 3D NAND bit line to word line shorts of claim 2, wherein: and a third needle pad is also arranged on the conductive structure.
6. The method for calibrating 3D NAND bit line to word line shorting of claim 5 wherein: the step of electrically connecting all word line layers below the target word line layer and applying a voltage capable of opening a channel layer of a channel structure includes electrically connecting a third probe to the third pad and applying the voltage capable of opening the channel layer of the channel structure through the third probe.
7. The method for calibrating 3D NAND bit line to word line shorting of claim 1, wherein: the 3D NAND further includes a plurality of contact plugs electrically connected to the plurality of word line layers, respectively, and the method further includes a process of forming first pin pads on the corresponding contact plugs of the target word line layer.
8. The method for calibrating 3D NAND bit line to word line shorting of claim 1, wherein: the 3D NAND further includes a contact plug electrically connected to the substrate, and the method further includes a process of forming a second pin pad on the contact plug of the substrate.
9. Method for calibrating 3D NAND bit line to word line shorts according to any of claims 5 to 8, characterized in that: the needle pad is formed by using a line repairing method.
10. The method for calibrating 3D NAND bit line to word line shorting of claim 1, wherein: the 3D NAND further comprises a plurality of contact plugs which are respectively and correspondingly electrically connected with the plurality of word line layers and the substrate, and the process further comprises the step of grinding a target sample before a target address is found until the contact plugs of the word line layers and the contact plugs of the substrate are exposed.
11. The method for calibrating 3D NAND bit line to word line shorts of claim 1, wherein the 3D NAND further comprises a plurality of contact plugs electrically connected to the plurality of word line layers and the substrate, respectively, the process further comprising: and electrically connecting the first probe with the contact plug of the target word line layer, and electrically connecting the second probe with the contact plug of the substrate.
12. The method for calibrating 3D NAND bit line to word line shorting according to claim 1, wherein a voltage of 6-8V is applied on all word line layers below the target word line layer for opening the channel structure.
13. The method for calibrating 3D NAND bit line to word line shorting of claim 1, wherein the process further comprises a process of recording the failure location after the failure hot spot location.
14. The method for calibrating 3D NAND bit line to word line shorting of claim 1 wherein the process further comprises a process of slicing the target address after a failed hot spot location.
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