CN109935271A - Memory and its acquisition methods, failure positioning method - Google Patents
Memory and its acquisition methods, failure positioning method Download PDFInfo
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- CN109935271A CN109935271A CN201910250753.0A CN201910250753A CN109935271A CN 109935271 A CN109935271 A CN 109935271A CN 201910250753 A CN201910250753 A CN 201910250753A CN 109935271 A CN109935271 A CN 109935271A
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Abstract
The present invention provides a kind of memory and its acquisition methods, failure positioning method, after the dielectric layer that memory chip is exposed on bit line, two liners are formed on dielectric layer, and be connected respectively to two bit lines that dibit line fails on the two liners by electrical wiring, in this way, the bit line that this two fail just individually to be established to the circuit of analysis of central issue, the two liners are for biasing voltage when analysis of central issue, it is thus possible to grab hot spot, the quick accurate positioning of dibit line failure is realized.
Description
Technical field
The present invention relates to semiconductor devices and its manufacturing field, in particular to a kind of memory and its acquisition methods, failure
Localization method.
Background technique
With the continuous development of integrated circuit and semiconductor technology, memory is widely used, and storage core
The test and failure positioning of piece, are the important means for improving memory chip yield and performance.In the test of memory chip
In, bit line leakage (Bit Line leakage) test item is used to test two adjacent bit lines with the presence or absence of failure, and
When occurring dibit line (TBL, Twin Bit Line) failure in these test items, the specific of this two bit lines how is navigated to
Invalid position is the difficult point in failure analysis.
Summary of the invention
In view of this, being realized the purpose of the present invention is to provide a kind of memory and its acquisition methods, failure positioning method
The quick accurate positioning of dibit line failure.
To achieve the above object, the present invention has following technical solution:
A kind of acquisition methods of memory, comprising:
Memory chip is provided, the memory chip includes memory cell array, along one in the memory cell array
The storage unit of direction arrangement is electrically connected to a bit line, and the memory chip is exposed to the dielectric layer on the bit line, institute
Stating memory chip, there are the failures of dibit line；
The first liner and the second liner are formed on the dielectric layer；
Described first is respectively electrically connected to by two bit lines that the first electrical wiring and the second electrical wiring fail dibit line
Liner and second liner, first liner and second liner are used for the voltage bias of analysis of central issue.
Optionally, first electrical wiring and second electrical wiring and first liner and second liner
It is formed using the circuit mending function of focused ion beam equipment.
Optionally, the analysis of central issue is carried out using photoinduction resistance variations equipment.
Optionally, first liner and second liner and first electrical wiring and second electrical wiring
Material be tungsten or platinum.
Optionally, the storage unit is or/no type flash memory, and the drain electrode along the or/no type flash memory of direction arrangement is connected to
One bit line.
A kind of memory, comprising:
Memory chip, the memory chip include memory cell array, along a direction in the memory cell array
The storage unit of arrangement is electrically connected to a bit line, and the memory chip is exposed to the dielectric layer on the bit line, described to deposit
There are the failures of dibit line for memory chip；
The first liner and the second liner on the dielectric layer；
Two bit lines that dibit line is failed respectively are electrically connected to the first electricity of first liner and second liner
Line and the second electrical wiring, first liner and second liner are used for the voltage bias of analysis of central issue.
Optionally, first liner and second liner and first electrical wiring and second electrical wiring
Material be tungsten or platinum.
Optionally, the storage unit is or/no type flash memory, and the drain electrode along the or/no type flash memory of direction arrangement is connected to
One bit line.
A kind of failure positioning method characterized by comprising
Using any of the above-described memory, apply bias voltage on the first liner and the second liner, and carries out hot spot point
Analysis, to obtain failure positioning.
Optionally, analysis of central issue is carried out using photoinduction resistance variations equipment.
Memory and its acquisition methods provided in an embodiment of the present invention, failure positioning method, by memory chip exposure
After dielectric layer on to bit line, two liners are formed on dielectric layer, and two bit lines that dibit line fails are passed through and are electrically connected
Line is connected respectively on the two liners, in this way, the bit line that this two fail just individually is established to the circuit of analysis of central issue, this
Two liners are for biasing voltage when analysis of central issue, it is thus possible to grab hot spot, realize the quick accurate of dibit line failure
Positioning.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is the present invention
Some embodiments for those of ordinary skill in the art without creative efforts, can also basis
These attached drawings obtain other attached drawings.
Fig. 1 shows the schematic top plan view of memory chip neutrality line according to an embodiment of the present invention；
Figure 1A shows in Fig. 1 AA to schematic cross-section；
Fig. 2 shows the schematic perspective views that dibit line in memory chip according to an embodiment of the present invention fails；
Fig. 3 shows the flow diagram of the acquisition methods of memory according to an embodiment of the present invention；
Fig. 4 shows the overlooking structure diagram of memory according to an embodiment of the present invention；
Fig. 4 A shows the AA in Fig. 4 to schematic cross-section；
Fig. 5 shows the schematic perspective view that positioning analysis is carried out using the memory of the embodiment of the present application；
Fig. 6 shows the microscope photo that positioning analysis is carried out using the memory of the embodiment of the present application；
Fig. 7 shows the microscope photo of the localization method positioning using the embodiment of the present application and the invalid position of acquisition.
Specific embodiment
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, but the present invention can be with
It is different from other way described herein using other and implements, those skilled in the art can be without prejudice to intension of the present invention
In the case of do similar popularization, therefore the present invention is not limited by the specific embodiments disclosed below.
Secondly, combination schematic diagram of the present invention is described in detail, when describing the embodiments of the present invention, for purposes of illustration only, table
Show that the sectional view of device architecture can disobey general proportion and make partial enlargement, and the schematic diagram is example, is not answered herein
Limit the scope of protection of the invention.In addition, the three-dimensional space of length, width and depth should be included in actual fabrication.
As the description in background technique, in the test of memory chip, the test item of bit line leakage is for testing
How two adjacent bit lines navigate to this two with the presence or absence of failure, and when there is TBL (Twin Bit Line) failure
The specific invalid position of bit line is the difficult point in failure analysis.
In order to better understand the technical solution of the application, memory construction and technical problem are done specifically first
It is bright.Storage unit in the embodiment of the present application can be any type of memory device, such as can be or/no type flash memory (NOR
Flash), with NOT-AND flash (NAND flash) or other kinds of storage unit.In memory chip, storage unit is with battle array
Column form is arranged, and the storage unit drain electrode in array on column direction is all connected on certain bit line by interconnection structure, is mutually linked
Structure includes contact plug, connecting line layer and/or via hole.
In one of the application application, with reference to shown in Fig. 1 (top view) and Figure 1A (in Fig. 1 AA to schematic cross-section),
Storage unit is or/no type flash memory (NOR flash), forms storage array by storage unit, the storage in storage array in each column
Unit is connected on a bit line 130, NOR Flash cell include grid 110, source electrode 114 and drain electrode 112, grid 110 include according to
The floating gate and control gate of secondary stacking are isolated between floating gate and control gate by dielectric material, the NOR Flash cell in same row
Drain electrode 112 is all connected on a bit line 130, in this example, is interconnected by one layer, i.e. contact plug 120 is by the leakage of same row
Pole 112 is all connected on bit line 130.NOR storage unit on a bit line 130, by substrate 100 between storage unit
Active area be connected in turn, active area, that is, source electrode 114 and drain electrode 112, and drain and 112 be connected to together further through interconnection structure
On one bit line.It is understood that storage unit can be connected by the interconnection of more layers in different designs and application
It is connected on bit line.
In NOR memory, when there is dibit line TBL failure, short circuit between two usually adjacent bit lines
(bridge) caused by, and the short circuit of any layer between the storage unit on this bit line can all cause dibit line TBL to fail.
In this example, refering to what is shown in Fig. 2, between adjacent bit line 130, any two contact plug 120 or phase on adjacent bit line
The short circuit 140 of any position, can all cause the failure of dibit line TBL, the length of bit line between active area in adjacent substrate 100
Degree is determined that usually 100-300 microns, in the example, the length of bit line has by the memory capacity of a memory block (block)
130 μm, it is difficult to the position of dibit line failure is found in long bit line range and multilayer.Currently, mainly passing through polishing
(polish) manual type of chip combination scanning electron microscope (SEM), carries out the positioning of invalid position, specifically, existing will
The chip of failure is polishing to close to bit line layer, then, using SEM along the dibit line of failure from one end to the other end, see
Whether have leakage point of electricity appearance, if not having, the chip for continuing failure is polishing to contact plug layer, using SEM along the double of failure if examining
Bit line, to the other end, has seen whether leakage point of electricity appearance from one end, if not having, the chip for continuing to fail is polishing to close
Active area, using SEM along the dibit line of failure from one end to the other end, seen whether leakage point of electricity appearance.This method
Viewing area it is big, and failpoint is usually nanoscale size, be easy to cause the omission of failpoint, and observing time is long,
Low efficiency.
For this purpose, being exposed to this application provides memory and its acquisition methods, failure positioning method by memory chip
After dielectric layer on bit line, two liners are formed on dielectric layer, and two bit lines that dibit line is failed pass through electrical wiring
It is connected respectively on the two liners, in this way, the bit line that this two fail just individually to be established to the circuit of analysis of central issue, this two
Voltage of a liner for biasing when analysis of central issue realizes the quick accurate fixed of dibit line failure it is thus possible to grab hot spot
Position.
The technical solution and technical effect of the application in order to better understand, below with reference to flow chart, to specific reality
Example is applied to be described in detail.
Refering to what is shown in Fig. 3, providing memory chip in step S01, the memory chip includes memory cell array,
Storage unit in the memory cell array along direction arrangement is electrically connected to a bit line 130, and the memory chip is sudden and violent
Dew is to the dielectric layer 140 on the bit line 130, and there are the failures of dibit line for the memory chip, (overlooks superposition to show with reference to Fig. 4
Be intended to) and Fig. 4 A (in Fig. 4 AA to schematic cross-section) it is shown.
In the embodiment of the present application, memory cell array is provided in memory chip, memory cell array may include more
A storage unit, multiple storage units can be arranged to multiple rows and multiple column, depositing in such as same column in same direction
Storage unit may be coupled on identical bit line, and different storage units can also include other components, for example, wordline or its
His selection line etc..Memory cell array can be divided into multiple memory blocks (Block), and the length of memory block determines the length of bit line
Degree.
In the particular embodiment, memory chip can also include driving circuit and read/write circuit, and control them
Other necessary circuits such as control circuit, control circuit, which can receive address information from outside and decode the received address of institute, to be believed
Breath, driving circuit, which can choose, is connected in memory cell array corresponding wordline, bit line etc., to select corresponding storage unit
The operation such as read and write, wipe.
It is understood that the memory chip has completed all manufacturing process of device, and carried out chip-scale
It tests (Chip Test), after a test, dibit line TBL failure occurs, by electricity failure analysis, can learn specifically
There is dibit line TBL failure in which two bit line.In turn, the memory chip that this to TBL failure can occur is polished, by it
Processing is to the dielectric layer on bit line, that is to say, that only retain the dielectric layer on bit line, and by other layers on the dielectric layer
All get rid of.
In the embodiment of the present application, storage unit can be any type of memory device, such as can be or/no type flash memory
(NOR flash) and NOT-AND flash (NAND flash) or other kinds of storage unit.In one embodiment, with reference to Fig. 4
With Fig. 4 A, wherein Fig. 4 is bit line and the superimposed schematic top plan view of layer thereon, and in the embodiment, storage unit is that NOR dodges
It deposits, storage unit includes grid 110, source electrode 114 and drain electrode 112, and grid 110 includes the floating gate and control gate stacked gradually, is floated
It is isolated between grid and control gate by dielectric material, the drain electrode 112 of the NOR Flash cell in same row is all connected to a bit line
On 130.In different applications, the drain electrode 112 of NOR Flash cell can be connected to bit line 130 by one or more layers.
The dielectric layer 140 being covered on it, the material of the dielectric layer 140 typically silica are also remained on bit line 130.
In step S02, the first liner 150 and the second liner 152 are formed on the dielectric layer 140, with reference to Fig. 4 and Fig. 4 A
It is shown.
In step S03, two bit line 130F that dibit line is failed by the first electrical wiring 160 and the second electrical wiring 162
It is respectively electrically connected to first liner 150 and second liner 152, first liner 150 and second liner 152
For the voltage bias of analysis of central issue, with reference to shown in Fig. 4 and Fig. 4 A.
The first liner 150 formed on dielectric layer 140 and the second liner 152 are isolated from each other and can't be electrically connected mutually
Connect, then, by two electrical wirings 160,162, two articles of bit line 130F that dibit line is failed respectively with the first liner 150 and the
Two liners 152 are electrically connected, i.e., the two bit line 130F first liner 150 to be failed with dibit line with the first electrical wiring 160
In a bit line be electrically connected, with the second electrical wiring 162 by second liner 152 with dibit line failure two bit line 130F
In another bit line be electrically connected, in this way, two bit line 130F that just dibit line fails by liner 150,152 individually
It draws, the voltage bias of analysis of central issue (hotspot analysis) can be carried out by the two liners 150,152.
In analysis of central issue, voltage bias is carried out by two liners 150,152, the bit line of this two failures will form one
A test loop will will appear hot spot (hotspot) under the voltage bias at failpoint, in turn, can be by hot spot
The position of specific failpoint can be quickly navigated to, and then each relevant layers of failpoint position are observed, is failed
The range of point is usually at some location point of whole bit line, and usually nanoscale range, real without observing whole bit line
The accurate positioning of existing failpoint, improves positioning accuracy and efficiency.
In specific application, first liner 150 and second liner 152 can use arbitrary conductive material
It is formed, such as can be metal materials or other conductive materials such as tungsten or platinum.Similarly, first electrical wiring 160 and institute
Stating the second electrical wiring 162 can also be formed using arbitrary conductive material, for example, can for the metal materials such as tungsten or platinum or its
His conductive material.First liner 150 and second liner 152, first electrical wiring 160 and second electrical wiring
The 162 circuit mending functions of can use focused ion beam (FIB) equipment are formed, and the mending function of focused ion beam can provide
The conductive materials such as tungsten or platinum.Analysis of central issue can use the progress of photoinduction resistance variations (OBIRCH) equipment.
The acquisition methods of the memory of the embodiment of the present application are described in detail above, in addition, the application is implemented
Example additionally provides the memory formed by the above method, with reference to shown in Fig. 4 and Fig. 4 A, comprising:
Memory chip, the memory chip include memory cell array, along a direction in the memory cell array
The storage unit of arrangement is electrically connected to a bit line 130, and the memory chip is exposed to the dielectric layer on the bit line 130
140, there are the failures of dibit line for the memory chip；
The first liner 150 and the second liner 152 on the dielectric layer 140；
Two bit line 130F that dibit line is failed respectively are electrically connected to first liner 150 and second liner
152 the first electrical wiring 160 and the second electrical wiring 162, first liner 150 and second liner 152 are for hot spot point
The voltage bias of analysis.
Wherein, the material of first liner and second liner can be the metal materials such as tungsten or platinum.Described first
Electrical wiring 160 and second electrical wiring 162 can also be with metal materials such as tungsten or platinum.
Storage unit can be or/no type flash memory, and the drain electrode along the or/no type flash memory of direction arrangement is connected to a position
Line.
In addition, the embodiment of the present application also provides the method for carrying out failure positioning using above-mentioned memory, in the first lining
Apply bias voltage on bottom and the second substrate, and analysis of central issue is carried out to above-mentioned memory, to obtain failure positioning.
Refering to what is shown in Fig. 5, to carry out the schematic perspective view of analysis of central issue, in the first liner 150 and the second liner 152
The bit line of upper application bias voltage, this two failures will form a test loop, if any position between two bit lines 130
There is failpoint 20 in the place of setting, in analysis of central issue, hot spot can occurs in the corresponding position of this two bit lines 130 of memory,
In this way, the hot spot is the location point of failure point location, in turn, in physical failure analysis (Physical Failure
Analysis, PFA) in, real invalid position is found according to the hot spot, to find failure cause.
In specific application, analysis of central issue is carried out using photoinduction resistance variations (OBIRCH) equipment.With reference to Fig. 6 institute
Show, wherein figure (A) is 20 times of (20X) enlarged photographs for carrying out analysis of central issue using OBIRCH, figure (B) is 100 times of hot spot
(100X) enlarged photograph.As shown in fig. 6, the biasing stitch of OBIRCH equipment is had an acupuncture treatment using two hold-carryings to the first liner and the second lining
In pad, and the biasing of relevant voltage is carried out, the lines longitudinally extended in figure (B) are bit line, in the bit line of this two TBL failure
Between there is hot spot (hotspot), in turn, can be marked around the hot spot (mark), the label for PFA analyze when
Reference by location, and then can be analyzed with further progress PFA, find real failpoint and failure cause.
Refering to what is shown in Fig. 7, after to carry out positioning analysis using above-mentioned memory, further progress PFA analysis, the mistake found
Imitate reason, wherein figure (A) is in contact plug layer short circuit (CT bridge), and left figure is that processing to the vertical view after contact plug is shone
Piece observes there is exception between two contact plugs under the microscope after positioning to hotspot location, and right figure is to the exception
Contact plug cuts the photo after its cross section, it can be seen that two contacts are plugged with short circuit；Scheme the vertical view that (B) is the layer where bit line to shine
Piece observes that three bit lines have short-circuit (bridge) at the position after positioning to hotspot location under the microscope.As it can be seen that sharp
With the present processes, after carrying out failure positioning, each relevant layers of failpoint position are observed, the model of failpoint
It encloses usually at some location point of whole bit line, usually nanoscale range, without observing whole bit line, realizes failure
The accurate positioning of point improves positioning accuracy and efficiency.
The above is only a preferred embodiment of the present invention, although the present invention has been disclosed in the preferred embodiments as above, so
And it is not intended to limit the invention.Anyone skilled in the art is not departing from technical solution of the present invention ambit
Under, many possible changes and modifications all are made to technical solution of the present invention using the methods and technical content of the disclosure above,
Or equivalent example modified to equivalent change.Therefore, anything that does not depart from the technical scheme of the invention, according to the present invention
Technical spirit any simple modification, equivalent variation and modification made to the above embodiment, still fall within the technology of the present invention side
In the range of case protection.
In addition, all the embodiments in this specification are described in a progressive manner, identical phase between each embodiment
As partially may refer to each other, the highlights of each of the examples are differences from other embodiments.Especially for
For constructive embodiment, since it is substantially similar to the method embodiment, so describing fairly simple, related place is referring to method
The part of embodiment illustrates.
Claims (10)
1. a kind of acquisition methods of memory characterized by comprising
Memory chip is provided, the memory chip includes memory cell array, along a direction in the memory cell array
The storage unit of arrangement is electrically connected to a bit line, and the memory chip is exposed to the dielectric layer on the bit line, described to deposit
There are the failures of dibit line for memory chip；
The first liner and the second liner are formed on the dielectric layer；
First liner is respectively electrically connected to by two bit lines that the first electrical wiring and the second electrical wiring fail dibit line
With second liner, the voltage bias of first liner and second liner for analysis of central issue.
2. acquisition methods according to claim 1, which is characterized in that first electrical wiring and second electrical wiring,
And first liner and second liner are formed using the circuit mending function of focused ion beam equipment.
3. acquisition methods according to claim 1, which is characterized in that the analysis of central issue is set using photoinduction resistance variations
It is standby to carry out.
4. acquisition methods according to claim 1, which is characterized in that it is described first liner and it is described second liner and
The material of first electrical wiring and second electrical wiring is tungsten or platinum.
5. acquisition methods described in any one of -4 according to claim 1, which is characterized in that the storage unit is or/no type sudden strain of a muscle
It deposits, the drain electrode along the or/no type flash memory of direction arrangement is connected to a bit line.
6. a kind of memory characterized by comprising
Memory chip, the memory chip include memory cell array, are arranged in the memory cell array along a direction
Storage unit be electrically connected to a bit line, the memory chip is exposed to the dielectric layer on the bit line, the memory
There are the failures of dibit line for chip；
The first liner and the second liner on the dielectric layer；
Two bit lines that dibit line is failed respectively are electrically connected to the first electrical wiring of first liner and second liner
With the second electrical wiring, the voltage bias of first liner and second liner for analysis of central issue.
7. memory according to claim 6, which is characterized in that first liner and second liner, Yi Jisuo
The material for stating the first electrical wiring and second electrical wiring is tungsten or platinum.
8. memory according to claim 6 or 7, which is characterized in that the storage unit is or/no type flash memory, along a side
A bit line is connected to the drain electrode of the or/no type flash memory of arrangement.
9. a kind of failure positioning method characterized by comprising
Using the memory as described in any one of claim 6-8, apply bias voltage on the first liner and the second liner,
And analysis of central issue is carried out, to obtain failure positioning.
10. localization method according to claim 9, which is characterized in that carry out hot spot using photoinduction resistance variations equipment
Analysis.
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| CN201910250753.0A CN109935271B (en) | 2019-03-29 | 2019-03-29 | Memory and acquisition method and failure positioning method thereof |
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| CN111243974A (en) * | 2020-01-16 | 2020-06-05 | 长江存储科技有限责任公司 | Method for calibrating short circuit between 3D NAND bit line and word line |
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| CN109935271B (en) | 2021-03-23 |
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