CN116454067A - Test structure and test method - Google Patents
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- 238000012360 testing method Methods 0.000 title claims abstract description 444
- 238000010998 test method Methods 0.000 title claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 174
- 229910052751 metal Inorganic materials 0.000 claims abstract description 174
- 230000007547 defect Effects 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 13
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- 101150090280 MOS1 gene Proteins 0.000 description 16
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
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- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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Abstract
The application discloses a test structure and a test method, which are used for solving the problems of lower test efficiency and redundancy of structural arrangement in the prior art. The test structure comprises: a substrate; at least two test metal layers, each of which is provided with a sub-test structure, wherein the sub-test structure comprises a first sub-test structure and a second sub-test structure; the first test electrode is respectively connected with the first sub-test structure in each test metal layer; a second test electrode connected to the second sub-test structure in each test metal layer; and MOS transistors are further arranged between the first test electrode and the first sub-test structure of each test metal layer, and the opening voltages of the MOS transistors between the first sub-test structures of different test metal layers and the first test electrode are different. The test structure can detect a plurality of test metal layers at the same time, can judge whether the test metal layers have short circuit defects and the positions of the short circuit defects, greatly saves the number of the test structures and improves the test efficiency.
Description
Technical Field
The invention relates to the technical field of electrical testing, in particular to a testing structure and a testing method.
Background
The most typical features of integrated circuit development include: the shrinking of front-end device feature sizes and the increasing complexity of back-end metal routing. The back-end metal process mainly provides working power or signal paths for all ports of the front-end device through electric connection. Therefore, the post metal interconnection process is important.
In order to monitor the stability of the back-end metal interconnection process, besides the management and control of the production process data, various electrical characteristics of metals, such as the square resistance of the metals, the connectivity of the metals, and the conditions of short circuits among the metals, are monitored. Because the main function of metal is to serve as an interconnect, shorting between adjacent metal lines due to process anomalies is one of the important electrical test items.
The existing test structure for the rear-section metal short circuit follows the principle of layering and independent setting, namely, one layer of metal is provided with one set of test patterns, so that the design has strong pertinence, the problem tracing can be realized very conveniently, and obvious defects exist. Because the metal layer of the nano-scale semiconductor manufacturing process is usually up to 6-10 layers, if the test structure is set according to the above-mentioned test principle, on one hand, forming the required test pattern will occupy a large amount of scribe line area on the wafer, on the other hand, the electrical test needs to be performed on the test pattern of each layer, which wastes test resources.
Therefore, how to reduce the occupation of test resources, improve the test efficiency and determine the position of the defect in time is a technical problem to be solved by the technicians in the field.
Disclosure of Invention
In view of the foregoing, the present invention provides a test structure and a test method, wherein the test structure can detect a plurality of test metal layers at the same time, and can rapidly determine whether a short circuit defect exists and which test metal layer or layers the defect is located in when the short circuit defect exists.
To achieve the above object, a first aspect of the present invention provides a test structure, comprising: a substrate; at least two test metal layers, each of which is provided with a sub-test structure, wherein the sub-test structure comprises a first sub-test structure and a second sub-test structure; the first test electrode is respectively connected with the first sub-test structure in each test metal layer; a second test electrode connected to the second sub-test structure in each test metal layer; and MOS transistors are further arranged between the first test electrode and the first sub-test structure of each test metal layer, and the opening voltages of the MOS transistors between the first sub-test structures of different test metal layers and the first test electrode are different.
Preferably, each test metal layer is provided with the same or different sub-test structures.
Preferably, the first sub-test structure and the second sub-test structure comprise at least one of a comb-tooth structure and a serpentine structure.
Preferably, the sub-test structures on adjacent test metal layers are arranged in a consistent or mutually perpendicular direction.
Preferably, the first sub-test structure and the second sub-test structure comprise oppositely arranged comb-shaped structures, each comb-shaped structure comprises a comb handle and a plurality of tooth-shaped metal strips connected with the comb handle, and the tooth-shaped metal strips of the first sub-test structure and the tooth-shaped metal strips of the second sub-test structure are mutually inserted.
Preferably, the MOS transistor is located in the substrate.
Preferably, the source electrode of the MOS tube is connected with the first sub-test structure corresponding to the test metal layer, and the grid electrode and the drain electrode of the MOS tube are connected with the first test electrode.
Preferably, the difference of the starting voltages of the MOS transistors corresponding to different test metal layers is not more than 10%.
Preferably, the size of the channel of the MOS tube corresponding to the different test metal layers is different.
Preferably, the on-currents of the MOS transistors between the first sub-test structures of the different test metal layers and the first test electrode are different under the same preset voltage.
Preferably, the preset voltage is 0.9-1 times of the starting voltage of the MOS transistor with the highest starting voltage in the MOS transistors, and the preset voltage enables all the MOS transistors to be started and in a high-resistance state.
According to another aspect of the present invention, there is also provided a test method for testing the test structure as described above, characterized by comprising the steps of: applying a preset voltage between a first test electrode and a second test electrode to the MOS tube to detect leakage current; if the leakage current between the first test electrode and the second test electrode is not greater than the leakage preset value, all the test metal layers of the test structure have no short circuit defect; if the leakage current between the first test electrode and the second test electrode is larger than the leakage preset value, comparing the leakage current with a first abnormal comparison table predetermined according to the method, and positioning the short-circuit defect.
Preferably, the leakage preset value is 10 -10 A。
According to a further aspect of the present invention, there is provided a further test method for testing a test structure as described above, comprising the steps of: applying different starting voltages between the first test electrode and the second test electrode from low to high until a preset voltage; if the leakage current between the first test electrode and the second test electrode is not larger than the leakage preset value in the process, all the test metal layers of the test structure have no short circuit defect; if the leakage current between the first test electrode and the second test electrode is larger than the leakage preset value in the process, comparing the leakage current with a second abnormal comparison table predetermined according to the method, and positioning the short-circuit defect; the preset voltage is 0.9-1 times of the starting voltage of the MOS tube with the highest starting voltage.
Preferably, the leakage preset value is 10 -10 A。
According to the test structure and the test method provided by the invention, the multiple test metal layers are integrated in the same test structure, and each test metal layer is connected in series with one corresponding MOS tube for calibration, so that the multiple reduction of the test number can be realized, the single test is performed under the preset voltage, and whether the short circuit problem exists or not and the position where the short circuit problem occurs can be judged through the leakage current. Furthermore, the specific test metal layer can be detected by adopting a test mode of applying different starting voltages for multiple times, so that the interference of other test metal layers is reduced, the test reliability is improved, the position where the short circuit problem occurs can be locked rapidly through leakage current, the time and test resources required by the test are greatly reduced, the number of test structures is saved, and the test efficiency is remarkably improved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings. Moreover, for the sake of clarity, various parts in the drawings are not drawn to scale.
FIG. 1 is a schematic diagram of a conventional single layer test structure;
FIG. 2 is a schematic diagram of a multi-layer test structure that is simply integrated by the single-layer test structure shown in FIG. 1;
FIG. 3 is a schematic diagram of a first embodiment of a test structure according to the present invention;
FIG. 4 is a schematic diagram of an equivalent circuit of a first embodiment of the test structure of the present invention;
FIG. 5 is a table showing the electrical properties of each MOS transistor in a first embodiment of the test structure of the present invention;
FIG. 6 is a schematic diagram of a first embodiment of the testing method of the present invention;
FIG. 7 is a schematic diagram showing a short circuit occurring in a single test metal layer according to a first embodiment of the test method of the present invention;
FIG. 8 is a schematic diagram showing a plurality of test metal layers having a short circuit according to a first embodiment of the testing method of the present invention;
FIG. 9 is a first anomaly lookup table of a first embodiment of the testing method of the present invention;
FIG. 10 is a schematic diagram of a second embodiment of the testing method of the present invention;
FIG. 11 is a schematic diagram showing a first test metal layer having a short circuit when a voltage Vt1 is applied in a second embodiment of the testing method of the present invention;
FIG. 12 is a schematic diagram showing a short circuit between a first test metal layer and a second test metal layer when a voltage Vt2 is applied in a second embodiment of the testing method of the present invention;
FIG. 13 is a second anomaly lookup table of a second embodiment of the test method of the present invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. The invention is not limited to these embodiments only. In the following detailed description of the present invention, certain specific details are set forth in detail. The present invention will be fully understood by those skilled in the art without the details described herein. Well-known methods, procedures, and flows have not been described in detail so as not to obscure the nature of the invention.
Fig. 1 is a schematic diagram of a conventional single-layer test structure, where the single-layer test structure includes a first test pad 11, a first sub-test structure 13, a second test pad 12 and a second sub-test structure 14, where the first sub-test structure 13 and the second sub-test structure 14 form a sub-test structure, the first sub-test structure 13 is connected to the first test pad 11 through a metal wire, the second sub-test structure 14 is connected to the second test pad 12 through a metal wire, specifically, the first sub-test structure 13 and the second sub-test structure 14 are disposed opposite to each other, the first sub-test structure 13 and the second sub-test structure 14 are, for example, both are similar in shape, and the first sub-test structure 13 includes a comb handle 131 and a plurality of toothed metal strips 132, one end of the plurality of toothed metal strips 132 on the same side is connected to the comb handle 131, the comb handle 131 is connected to the first test pad 11 through a metal wire, the plurality of toothed metal strips of the first sub-test structure 13 and the second sub-test structure 14 are disposed opposite to each other, and all of the toothed metal strips are further disposed between adjacent to each other (the metal strips are not shown in the dielectric layer) by insulating medium layer). A voltage is applied between the first test pad 11 and the second test pad 12, and whether leakage current exists between the first test pad 11 and the second test pad 12 is detected to feed back whether the manufacturing process of the layer where the sub-test structure is located is normal, and under normal conditions, no conductive path exists between the first test pad 11 and the second test pad 12, that is, under ideal conditions, the first test pad 11 and the second test pad 12 are open circuits, and the manufacturing process of the sub-test structure is normal. If there is a conductive path between the first test pad 11 and the second test pad 12, this indicates that there is a defect in the sub-test structure, and the manufacturing process of the sub-test structure may be problematic.
The child test structure is made into a comb-tooth shape so as to increase the area of the test structure and improve the probability of capturing abnormal conditions. The longer the number of teeth, the longer the metallic teeth, the greater the probability of capturing a short defect, with the processed scribe line width and test pad spacing allowed. To further increase the sensitivity of the subtest structure, the width of the toothed metal strips and the spacing between adjacent toothed metal strips in the subtest structure should be selected to be the minimum value that meets the physical design rules of the corresponding process platform. When the sub-test structure is shorted, bridging defects are likely to occur in the layer manufacturing process on the circuit in the wafer where the sub-test structure is located.
Because each test metal layer in the test structure and the metal layer of the circuit in the wafer where the test metal layer is positioned are formed synchronously, whether the manufacturing process of the circuit metal layer corresponding to the test structure is stable and normal can be fed back through the test structure and the detection of the test structure, so that problems can be found in time, and the generation of defective products is reduced.
FIG. 2 is a schematic diagram of a multi-layer test structure in which the single-layer metal test structure shown in FIG. 1 is simply integrated; in fig. 2, there are three test metal layers M1, M2, M3, and a first test electrode 21 and a second test electrode 22, and a first sub-test structure 23 and a second sub-test structure 24 for forming sub-test structures in each test metal layer, insulation is achieved between adjacent test metal layers by dielectric layers, and fig. 2 is different from fig. 1 in that three test metal layers M1, M2, M3 are included, and the sub-test structures in each test metal layer are similar to those in fig. 1, for example, wherein the first sub-test structure 23 and the second sub-test structure 24 are respectively connected to test metal pads in the same layer, and the metal pads on the same side in the test metal layers M1, M2, M3 are electrically connected to the first test electrode 21 and the second test electrode 22 located on the top layer through longitudinal metal and through holes. Although the testing structure simply integrates the sub-testing structures of all layers into the same testing structure through longitudinal metal and through holes, and achieves the aim of reducing the detection times, the design can only distinguish two conditions that all the testing metal layers have no short circuit and some testing metal layers have short circuits, and can not accurately position which layer or layers the short circuit is positioned on, once the short circuit condition is detected, the manufacturing processes of all the metal layers need to be checked one by one, and the problem tracing and the problem checking are not facilitated.
FIG. 3 is a schematic diagram of a first embodiment of a test structure according to the present invention; the test structure of this embodiment includes: a substrate M0, a test metal layer M1, a test metal layer M2, a test metal layer M3, and a first test electrode 31 and a second test electrode 32 on the top layer. The test structure of this first embodiment is similar to that of fig. 2, and also has three test metal layers, each of which also has a first sub-test structure 33 and a second sub-test structure 34 disposed opposite to each other, and the first sub-test structure 33 and the second sub-test structure 34 on each test metal layer constitute sub-test structures, i.e., three groups of sub-test structures are vertically distributed on different test metal layers in a longitudinal space, and the first sub-test structure 33 and the second sub-test structure 34 on each test metal layer may be arranged in parallel or vertically.
The difference between the first embodiment and fig. 2 is that the test structure of the first embodiment has a substrate M0, and the lateral lead-out metal lines of the first sub-test structures 33 of each test metal layer are staggered in the Y direction, so that the first sub-test structures 33 of each test metal layer are respectively connected with the substrate M0, the first sub-test structures 33 of the test metal layers M1, M2, M3 respectively pass through the MOS transistors on the substrate M0, and the MOS1, MOS2, MOS3 are then connected with the first test electrode 31 through the longitudinal metal and the through holes, specifically, taking the test metal layer M1 as an example, the first sub-test structures 33 of the test metal layer M1 are respectively connected with the body electrode B and the source electrode S of the MOS transistor MOS1 on the substrate M0 through two connected and juxtaposed longitudinal metal and through holes; the gate G and the drain D of the MOS1 are connected to the first test electrode 31 upwards through the vertical metal and the via, and the electrical connection of the first test electrode 31 to the first sub-test structure 33 can be achieved when the MOS1 is turned on. Similarly, the test metal layer M2 is connected to the body electrode B and the source electrode S of the MOS2 on the substrate M0, and the gate G and the drain electrode D of the MOS2 are connected to the first test electrode 31; the test metal layer M3 is connected to the body electrode B and the source electrode S of the MOS3 on the substrate M0, and the gate electrode G and the drain electrode D of the MOS3 are connected to the first test electrode 31. Namely, each test metal layer is connected in series with one MOS tube, the starting voltage of the MOS tube corresponding to each test metal layer is different, and further, the starting voltage difference of the three MOS tubes MOS1, MOS2 and MOS3 is controlled within 10%, so that the three MOS tubes can be simultaneously started under the preset voltage and are all in a high-resistance state. In order to increase the sensitivity and resolution of the test structure, the larger and better the difference of the on-current of the grid electrodes of the three MOS tubes under the preset voltage, the process of the three MOS tubes is basically the same, the difference only exists in the length L or the width W of the channel, the channel effect is utilized by controlling the size of the channel, the difference of the on-voltage of the MOS tubes is within 10%, and the difference of orders of magnitude can be realized by the on-current under the same preset voltage. By applying a preset voltage between the first test electrode 31 and the second test electrode 32 and detecting the current between the first test electrode 31 and the second test electrode 32, which test metal layer or layers are shorted (i.e. metal bridging occurs) can be quickly locked by the current value, so that problems can be traced and checked.
Of course, although only three embodiments of the test metal layers are shown in fig. 3, more test metal layers and corresponding MOS transistors may be provided based on the design of the embodiments; although the first sub-test structure 33 and the second sub-test structure 34 are both comb-shaped structures in the above description, they may be configured into other shapes such as serpentine structures according to actual needs, and further, the sub-test structures in the above test metal layers may be different, for example, the sub-test structure in the test metal layer M1 is comb-shaped, and the sub-test structure in the test metal layer M2 is serpentine.
Fig. 4 is an equivalent circuit schematic diagram of a first embodiment of the test structure of the present invention, omitting the substrate M0 and part of the longitudinal metal and through holes in fig. 3, simplifying the same into an equivalent circuit schematic diagram as shown in fig. 4, and as can be seen from fig. 4, the gate G and the drain D of the MOS transistor MOS1 are connected to each other and connected to the first test electrode 31 through metal connection lines and the longitudinal metal and through holes, and the source S and the body electrode B of the MOS transistor MOS1 are connected to the comb handle of the first sub-test structure of the sub-test structure; i.e. for each MOS transistor, its drain voltage V D And gate voltage V G Equal source voltage V S And body electrode voltage V B Equal; the MOS2 and MOS3 are similar to the MOS1, and are not described herein again, in the simplified equivalent schematic diagram, the first sub-test structures of the test metal layer M1, the test metal layer M2 and the test metal layer M3 are respectively connected with the MOS1, the MOS2 and the MOS3 in series, specifically, referring to the electrical performance tables of the three MOS transistors shown in FIG. 5, the opening voltages of the three MOS transistors are Vt1, vt2 and Vt3, wherein, for example, vt1 < Vt2 < Vt3. The three MOS tubes can be opened under the preset voltage V (V=vt3) and are in a high-resistance state, and the corresponding conduction currents are respectively I 31 、I 32 、I 33 。
The above-mentioned opening of the MOS transistor represents that a conductive channel exists between the source S and the drain D of the device, and the source S and the drain D may be considered to be connected together by a resistor. However, even if the device is in an on state, two conditions are required for current to flow between the source S and the drain D, one is that a potential difference (voltage) exists between the source S and the drain D to guide the directional movement of carriers; the other is that the source S and the drain D are located in a closed conductive loop.
During the test, a forward voltage of Vt3 is applied to the first test electrode 31 and the second test electrode 32 is grounded. As previously described, threeV of MOS tube G ＝V D =vt3, and source S and body B are connected to the second test electrode 32 through three sub-test structures, respectively. If the three sub-test structures have no short circuit problem at this time, the source S and the body B of the three MOS transistors are disconnected from the second test electrode 32 and a closed conductive loop cannot be formed although the three MOS transistors are all in an on state and the drain D has a high voltage. The first test electrode 21 and the second test electrode 32 remain disconnected. At this time, the current flowing in the whole test structure is less than 10 -10 A。
The calibration of current values can be realized for each layer by connecting different MOS transistors in series for different test metal layers, and because the MOS transistors connected in series for each layer have different on-currents at the same preset voltage V, the fault location is rapidly performed by applying the preset voltage Vt (vt=vt3) between the first test electrode 31 and the second test electrode 32, determining which one or more test metal layers the short circuit is located in, and checking the process of the corresponding test metal layer.
FIG. 6 is a schematic diagram of a first embodiment of the testing method of the present invention; as shown in fig. 6, a first embodiment of the test method of the present invention includes the steps of:
in step S10, a preset voltage is applied between the first test electrode and the second test electrode to detect leakage current; for example, the applied voltage is 0.9-1 times of the starting voltage of the MOS tube with the highest starting voltage in the MOS tubes connected in series, and the first test electrode and the second test electrode are not conducted under normal conditions, although the MOS is started, the leakage current between the two electrodes is very small and should not be larger than the leakage preset value I 0 Specifically, I 0 ＝10 -10 A。
If the leakage current is greater than the leakage preset value, step S20 is executed, and in step S20, the leakage current is compared with a first abnormal comparison table predetermined according to the method, so as to locate the short-circuit defect. Specifically, the processes of the three MOS tubes are basically the same, the difference only exists in the length L or the width W of the channel, the difference of the starting voltages of the MOS tubes is within 10% by controlling the size of the channel, and the on-current under the same preset voltage can realize the difference of orders of magnitude.
If the leakage current is not greater than the leakage preset value, the test structure shows that all the test metal layers have no short circuit defect, and the manufacturing process for forming each test metal layer is stable and normal.
Specifically, a preset voltage Vt is applied between the first test electrode and the second test electrode, where the preset voltage Vt is, for example, an on voltage of a MOS transistor with the largest on voltage among the three MOS transistors, and the voltage value can enable all of MOS1, MOS2, and MOS3 to be turned on;
if the three test metal layers have no short circuit problem, although the three MOS transistors are all turned on, a conductive loop cannot be formed between the first test electrode 31 and the second test electrode 32, and at this time, the leakage current I between the first test electrode and the second test electrode is not greater than the leakage preset value I 0 (10 -10 A)。
If the leakage current is greater than the preset leakage value I 0 It indicates that a short circuit exists in the multi-layer sub-test structure.
In the following, it will be illustrated how to determine the position of the short circuit after the short circuit occurs for the test structure according to the first embodiment of the present invention, wherein fig. 7 is a schematic diagram of the short circuit point occurring in the test metal layer M1, fig. 8 is a schematic diagram of the short circuit point occurring in the test metal layers M1 and M3 at the same time, and fig. 9 is a corresponding first anomaly comparison table. The resistance of the metal lines, metals and vias in the test structure is typically m omega, with negligible effect on current flow.
As shown in fig. 7, assuming that a short-circuit point occurs in the sub-test structure of the test metal layer M1, a closed conductive loop is formed between the first test electrode 31 and the second test electrode 32, a first leakage path 101 is generated as shown by a dotted line in the figure, only MOS1 is connected in series in the first leakage path 101, the source S and the bulk electrode B of the MOS1 are connected to the second test electrode, and although MOS2 and MOS3 are also turned on at a preset voltage vt=vt3, a corresponding conductive loop cannot be formed because the second test metal layer M2 and the third test metal layer M3 have no short-circuit point, and at this time, the current in the whole test structure is I 31 Due to the resistance of metal lines and metal and vias in generalIn the same way, when the short circuit problem occurs in the test metal layers M2 and M3 independently, the corresponding leakage currents are I respectively 32 、I 33 。
As shown in fig. 8, assuming that a short-circuit point occurs in each of the subtest structures of the test metal layers M1 and M3, two closed conductive loops are formed between the first test electrode 31 and the second test electrode 32, including a first leakage path 101 shown by a dotted line and a second leakage path 102 shown by a dash-dot line, and similarly, an equivalent circuit of the two leakage paths is equivalent to MOS1 and MOS3 connected in parallel in a circuit, and a calculation formula of a leakage current I in the parallel circuit is: i=i 31 +I 33 ，
When the leakage current I between the first test electrode 31 and the second test electrode 32 is the result of the calculation of the above equation, it can be inferred that the test metal layer M1 and the test metal layer M3 are shorted at the same time. Similarly, the test metal layer M1 and the test metal layer M2 are shorted together, and the test metal layer M2 and the test metal layer M3 are shorted together, so that detection and judgment modes are similar, and are not repeated.
The other extreme is that the test metal layers M1 to M3 are shorted together (not shown), and can be inferred from the equivalent circuit of the leakage path, for example, the leakage current I is a value i=i calculated by the following formula 31 +I 32 +I 33 It is indicated that the test metal layers M1 to M3 are shorted together.
According to the equivalent circuit of the leakage path under different conditions, a first abnormal comparison table which is predetermined according to the method and shown in fig. 9 can be obtained through calculation, and when the detection is actually carried out, the detection conclusion can be rapidly obtained by comparing the value of the leakage current I with the value in the table, and the position of the short circuit is determined.
FIG. 10 is a schematic diagram of a second embodiment of the testing method of the present invention; as shown in fig. 10, a second embodiment of the test method of the present invention includes the steps of:
in step S11, different turn-on voltages are applied between the first test electrode and the second test electrode from low to high until a preset voltage Vt; the turn-on voltages V of the three MOS transistors respectively connected in series with the three test metal layers are Vt1, vt2, and Vt3, respectively, wherein Vt1 < Vt2 < Vt3, and vt=vt3.
If the leakage current between the first test electrode and the second test electrode is not larger than the leakage preset value in the process, all the test metal layers of the test structure have no short circuit defect;
if the leakage current between the first test electrode and the second test electrode is greater than the leakage preset value in the process, step S21 is executed, the leakage current is compared with a second abnormal comparison table predetermined according to the method, and the short circuit defect is located.
Specifically, as shown in fig. 11 and 12, fig. 11 and 12 respectively show schematic diagrams of the occurrence of a short circuit in the single test metal layer M1. As shown in fig. 11, a short-circuit point occurs in the test metal layer M1, and different turn-on voltages V are applied from low to high between the first test electrode and the second test electrode until a preset voltage Vt.
Specifically, the test is performed by applying the turn-on voltages V1, V2, V3 three times between the first test electrode and the second test electrode, for example, vt1=v1 < vt2=v2 < vt3=v3; the preset voltage Vt is, for example, equal to V3. As shown in fig. 11, when the turn-on voltage V1 is applied, only MOS1 is turned on at this time, and the other two devices MOS2 and MOS3 are still in an open state between the source S and the drain D because the gate G is not sufficiently voltage. Under this condition, the circuit is equivalent to the short circuit condition of only selecting the test metal layer M1, and the interference of other test metal layers is eliminated.
Since the test metal layer M1 is shorted, the first test electrode and the second test electrode are conducted through the first conductive path 101, v1=vt1, MOS1 is turned on, and a leakage current I is formed in the first conductive path 101 11 ，I 11 Greater than 10 -10 A, detecting leakage current I=I between the first test electrode and the second test electrode 11 And then the test metal layer M1 has a short circuit problem.
Continuing to boost the voltage, as shown in fig. 12, when the turn-on voltage is increased to V2, only MOS1 and MOS2 are turned on and MOS3 is turned off at this time, which corresponds to only test metal layers M1 and M2 being connected to the circuit, test metal layersThe short-circuit condition of M1 is known when the turn-on voltage is V1, and when the voltage is raised to V2, the short-circuit condition is mainly used for feedback testing the condition of the metal layer M2, so that the leakage current i=i between the first test electrode and the second test electrode is detected 21 The test metal layer M2 is indicated to have no short circuit problem;
by the above, when the turn-on voltage rises to V3, the leakage current I=I 31 The test structure is completed after the test of the metal layer M3, and only the metal layer M1 is tested for short circuit.
Further, since three different voltages are required to be applied, three different leakage currents can be obtained, and the three results can be respectively compared with the second abnormal comparison table shown in fig. 13, so as to judge the short circuit condition of the whole test structure,
by applying different voltage levels to the test structure, the directional test of a certain test metal layer or certain test metal layers can be realized.
The three test metal layers are used for the example to explain in detail, but more test metal layers can be arranged according to the scheme of the invention, namely, the detection of the multi-layer metal layers can be realized by the test method provided by the invention, if a short circuit occurs, the specific position of the short circuit can be determined, and then the manufacturing process of the metal layer of the short circuit is traced and regulated, so that the problem point is positioned in time, the test efficiency is improved, and the time and the resource are saved.
According to the test structure and the test method provided by the invention, the plurality of metal layers are integrated in the same test structure to serve as the test metal layers, each test metal layer is connected in series with a corresponding MOS tube to calibrate, the multiple reduction of the test number can be realized, the single test is performed under the preset voltage, and whether the short circuit problem exists or not and the position where the short circuit problem occurs can be judged through the leakage current. Furthermore, the specific test metal layer can be detected by adopting a test mode of applying different starting voltages for multiple times, so that the interference of other test metal layers is reduced, the test reliability is improved, the position where the short circuit problem occurs can be locked rapidly through leakage current, the time and test resources required by the test are greatly reduced, the number of test structures is saved, and the test efficiency is remarkably improved.
It should be noted that in the description of the present invention, the terms "first," "second," and the like are merely used for convenience in describing different orientations, components, and assemblies and are not to be construed as indicating or implying a sequential relationship, relative importance, or implicitly indicating the number of technical features indicated.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, and various modifications and variations may be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (15)
1. A test structure, comprising:
a substrate;
at least two test metal layers, each of which is provided with a sub-test structure, wherein the sub-test structure comprises a first sub-test structure and a second sub-test structure;
the first test electrode is respectively connected with the first sub-test structure in each test metal layer;
a second test electrode connected to the second sub-test structure in each test metal layer;
and MOS transistors are further arranged between the first test electrode and the first sub-test structure of each test metal layer, and the opening voltages of the MOS transistors between the first sub-test structures of different test metal layers and the first test electrode are different.
2. The test structure of claim 1, wherein the same or different sub-test structures are provided on each test metal layer.
3. The test structure of claim 1, wherein the first sub-test structure and the second sub-test structure comprise at least one of a comb-tooth structure, a serpentine structure.
4. The test structure of claim 1, wherein the sub-test structures on adjacent test metal layers are aligned in a uniform or perpendicular direction.
5. The test structure of claim 1, wherein the first sub-test structure and the second sub-test structure comprise oppositely disposed comb-tooth structures, the comb-tooth structures comprising a comb handle and a plurality of toothed metal strips connected to the comb handle, the toothed metal strips of the first sub-test structure and the toothed metal strips of the second sub-test structure being interspersed with each other.
6. The test structure of claim 1, wherein the MOS transistor is located in the substrate.
7. The test structure of claim 6, wherein a source of the MOS transistor is connected to a first sub-test structure of a corresponding test metal layer, and a gate and a drain of the MOS transistor are connected to the first test electrode.
8. The test structure of claim 1, wherein the difference in turn-on voltages of the MOS transistors corresponding to different test metal layers is no more than 10%.
9. The test structure of claim 8, wherein the MOS transistors corresponding to different test metal layers belong to the same MOS transistor, and the respective channels are different in size.
10. The test structure of claim 9, wherein the on-currents of the MOS transistors between the first sub-test structures of different test metal layers and the first test electrode at the same preset voltage are different.
11. The test structure of claim 10, wherein the preset voltage is 0.9-1 times the turn-on voltage of the MOS transistor with the highest turn-on voltage among the MOS transistors, and the preset voltage turns on all the MOS transistors and is still in a high-resistance state.
12. A test method for testing a test structure according to any one of claims 1-11, comprising the steps of:
applying a preset voltage to the diode between the first test electrode and the second test electrode to detect leakage current;
if the leakage current between the first test electrode and the second test electrode is not greater than the leakage preset value, all the test metal layers of the test structure have no short circuit defect;
if the leakage current between the first test electrode and the second test electrode is larger than the leakage preset value, comparing the leakage current with a first abnormal comparison table predetermined according to the method, and positioning the short-circuit defect.
13. The method according to claim 12, wherein the leakage preset value is 10 -10 A。
14. A test method for testing a test structure according to any one of claims 1-11, comprising the steps of:
applying different starting voltages between the first test electrode and the second test electrode from low to high until a preset voltage;
if the leakage current between the first test electrode and the second test electrode is not larger than the leakage preset value in the process, all the test metal layers of the test structure have no short circuit defect;
if the leakage current between the first test electrode and the second test electrode is larger than the leakage preset value in the process, comparing the leakage current with a second abnormal comparison table predetermined according to the method, and positioning the short-circuit defect;
the preset voltage is 0.9-1 times of the starting voltage of the MOS tube with the highest starting voltage.
15. The method according to claim 13, wherein the leakage preset value is 10 -10 A。
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