CN116666359A - Test structure and test method - Google Patents
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- 238000012360 testing method Methods 0.000 title claims abstract description 587
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Abstract
The invention discloses a test structure and a test method. The test structure includes a substrate; each test metal layer comprises a serpentine metal wire and a comb-tooth-shaped structure which are arranged in a penetrating manner; the first test electrode is connected with the first end and the second end of each serpentine metal wire, and the third test electrode is connected with each comb-tooth-shaped structure, so that a first test branch circuit to a third test branch circuit is formed among the first test electrode, the second test electrode, the first test electrode, the third test electrode and the second test electrode; the first and second test electrodes are also connected in series with first and second preset MOS tubes between each serpentine metal wire; the current of each first test branch circuit under the same test voltage is different, the current of each second test branch circuit under the same test voltage is different, and the current of each third test branch circuit under the same test voltage is different. The test structure of the invention can save occupied wafer area and test times in multiple times.
Description
Technical Field
The present invention relates to the field of electrical testing technology in integrated circuit design and manufacturing processes, and in particular, to a testing structure and a testing method.
Background
The most typical features of integrated circuit development include: the reduction of the feature size of the front-end devices and the subsequent metal wiring is increasingly complex. The back-end metal process mainly provides working power or signal paths for all ports of the front-end device through electric connection, so that the back-end metal interconnection process is important.
In order to monitor the stability of the back-end metal interconnect process, various electrical characteristics of the metal, such as sheet resistance of the metal, connectivity of the metal lines, and shorts between the metal lines, are monitored in addition to the management of the process data. Because the main function of metal is as an interconnect, metal line shorts and opens due to process anomalies are important electrical test items therein.
The existing test structure for the back-end metal open circuit and short circuit follows the principle of layering and independent setting, namely, a set of test patterns are correspondingly arranged for a layer of metal interconnection layer, so that the arrangement has strong pertinence, the problem tracing can be realized very conveniently, and obvious defects exist. Because the metal interconnection layer of the nano-scale integrated circuit manufacturing process is usually 6-10 layers or more, if the test structure is set according to the principle, on one hand, the required test patterns are formed, a large amount of dicing area is required, on the other hand, each test pattern needs to be electrically tested one by one, and test resources are wasted.
Therefore, how to reduce the occupation of test resources, improve the test efficiency and determine the position of the defect in time is a technical problem to be solved by the technicians in the field.
Disclosure of Invention
In view of the above problems, the present invention aims to provide a test structure and a test method, which can save the occupied wafer area by times, and simultaneously has the advantages of convenient use, simple test, and accurate reflection of the problem of the back-end metal interconnection process.
To achieve the above object, a first aspect of the present invention provides a test structure, including:
a substrate;
at least two test metal layers positioned on the substrate, wherein each test metal layer comprises a serpentine metal wire and a comb-shaped structure which are arranged alternately;
the first test electrode is connected with the first end of the serpentine metal wire in each test metal layer respectively, the second test electrode is connected with the second end of the serpentine metal wire in each test metal layer respectively, the third test electrode is connected with the comb-shaped structure in each test metal layer, at least two first test branches are formed between the first test electrode and the second test electrode, at least two second test branches are formed between the first test electrode and the third test electrode, and at least two third test branches are formed between the second test electrode and the third test electrode;
A first preset MOS tube is connected in series between the first test electrode and the first end of the serpentine metal wire in each test metal layer, and a second preset MOS tube is connected in series between the second test electrode and the second end of the serpentine metal wire in each test metal layer; the current of each first test branch circuit under the same test voltage is different, the current of each second test branch circuit under the same test voltage is different, and the current of each third test branch circuit under the same test voltage is different.
Preferably, the first preset MOS transistor and the second preset MOS transistor in the same first test branch are the same.
Preferably, the first preset MOS transistor and the second preset MOS transistor in the same first test branch can be connected in series in a forward direction through a serpentine metal wire.
Preferably, in the test structure, the difference between the turn-on voltages of all the first preset MOS transistors and the second preset MOS transistors is not more than 10%, and preferably not more than 5%.
Preferably, the first preset MOS transistor and the second preset MOS transistor are each formed based on the substrate.
Preferably, the third test electrode is located between the first test electrode and the second test electrode;
the serpentine metal wire comprises two parts which are connected, wherein one part is positioned between the first test electrode and the third test electrode, and the other part is positioned between the third test electrode and the second test electrode.
Preferably, the comb-shaped structure comprises a first comb-shaped structure and a second comb-shaped structure, and the first comb-shaped structure and the second comb-shaped structure are respectively penetrated with the serpentine metal wire from two sides of the serpentine metal wire.
Preferably, the comb-like structure comprises a comb handle and a plurality of comb-like metal strips connected to the comb handle, and the comb handle of the first comb-like structure and the comb handle of the second comb-like structure are connected at a position bypassing one end of the serpentine metal wire.
Preferably, the source electrode and the body electrode of the first preset MOS tube are connected with the first end of the serpentine metal wire corresponding to the test metal layer, and the grid electrode and the drain electrode of the first preset MOS tube are connected with the first test electrode; the drain electrode and the grid electrode of the second preset MOS tube are connected with the second end of the serpentine metal wire corresponding to the test metal layer, and the source electrode and the body electrode of the second preset MOS tube are connected with the second test electrode.
A second aspect of the present invention provides a test method using the test structure of the first aspect, the test method comprising the steps of:
applying a first preset voltage between the first test electrode and the second test electrode, detecting a first current value between the first test electrode and the second test electrode, wherein the first preset voltage can enable a first preset MOS tube and a second preset MOS tube in a first test branch to be forward conducted;
Applying a second preset voltage between the first test electrode and the third test electrode, detecting a second current value between the first test electrode and the third test electrode, wherein the second preset voltage can enable the first preset MOS tube in the second test branch to be conducted in the forward direction;
applying a third preset voltage between the second test electrode and the third test electrode, detecting a third current value between the second test electrode and the third test electrode, wherein the third preset voltage can enable a second preset MOS tube in a third test branch to be conducted in the forward direction;
and judging and positioning the defect according to the first current value, the second current value and the third current value.
Preferably, the method further comprises: establishing a judging comparison table, wherein the judging comparison table comprises mapping relations between different combinations of the first current value to the third current value and defects; and judging and positioning the defects according to the comparison results of the first current value to the third current value and the judging comparison table.
Preferably, the voltage value of the first preset voltage is twice the voltage value of the second preset voltage, the voltage value of the third preset voltage is the same as the voltage value of the second preset voltage, and the voltage value of the second preset voltage is 0.9-1 times of the highest starting voltage in the first preset MOS tube and the second preset MOS tube.
The test structure provided by the invention comprises a plurality of test metal layers, wherein each test metal layer comprises a test unit which is integrated with the prior test unit for testing short circuits and open circuits, and each test metal layer corresponds to one metal interconnection layer. A pair of MOS tubes are connected in series between the test metal layer and the test electrode, so that various short circuit or open circuit abnormal conditions and current values form a one-to-one mapping relation. Compared with the prior art, the wafer area occupied by the test structure is equivalent to that of the existing single composite test structure, so that the wafer area occupied by the test structure is reduced to 1/(N-1) of the existing test structure, wherein N is the total number of layers of the metal interconnection layer, and the wafer area occupied by the test structure is effectively saved.
In the actual test process, compared with the prior compound test structure which is arranged in a layered way and needs to be tested layer by layer, the test structure can determine and position the defects only by one test; in particular, by using the determination look-up table, it is possible to quickly lock in which test metal layer or layers the short circuit and open circuit problem occur, and it is also possible to determine the relative positions of the short circuit and open circuit abnormality in the same test metal layer. Therefore, compared with the existing test method, the test method can greatly reduce the test times, remarkably improve the test efficiency, and the test result can also provide an important clue for subsequent failure analysis and positioning.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings. Moreover, for the sake of clarity, various parts in the drawings are not drawn to scale.
FIG. 1 is a top view of a test structure of a prior art layered design;
FIG. 2 is a schematic perspective view of a test structure according to a first embodiment of the present invention;
FIG. 3a is a schematic diagram of an equivalent circuit of a test structure according to a first embodiment of the present invention;
FIG. 3b is a chart showing electrical performance of each MOS transistor according to the first embodiment of the present invention;
FIG. 3c is a flow chart of a testing method according to a first embodiment of the invention;
FIG. 3d is a comparison table of the test structure according to the first embodiment of the present invention;
FIG. 4 is a schematic perspective view of a test structure according to a second embodiment of the present invention;
FIG. 5a is an equivalent circuit diagram of a test structure according to a second embodiment of the present invention;
FIG. 5b is a chart showing electrical performance of each MOS transistor according to the second embodiment of the present invention;
FIG. 5c is a comparison table I of a test structure according to a second embodiment of the present invention;
FIG. 6a is a schematic diagram of an equivalent circuit of a test structure according to a second embodiment of the present invention;
FIG. 6b is a second comparison table of the test structure according to the second embodiment of the present invention;
FIG. 7a is a schematic diagram of an equivalent circuit of a test structure with open circuit abnormality according to a second embodiment of the present invention;
FIG. 7b is a third comparison table of the test structure according to the second embodiment of the present invention;
FIG. 8a is a schematic diagram of an equivalent circuit of a test structure according to a second embodiment of the present invention with both short and open anomalies;
fig. 8b is a decision comparison table IV of the test structure according to the second embodiment of the invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. The invention is not limited to these embodiments only. In the following detailed description of the present invention, certain specific details are set forth in detail. The present invention will be fully understood by those skilled in the art without the details described herein. Well-known methods, procedures, and flows have not been described in detail so as not to obscure the nature of the invention.
FIG. 1 is a top view of a prior art test structure; as shown in fig. 1, the conventional test structure includes a first sub-test pad 111, a second sub-test pad 121, and a third sub-test pad 131. According to current industry design rules, three sub-test PADs (PADs) are arranged in sequence along the direction of the scribe line extension and the spacing between adjacent sub-test PADs is generally consistent. Wherein the first sub-test pad 111 and the second sub-test pad 121 are connected by a serpentine metal line 160 to form a test unit capable of detecting an open circuit; the third sub-test pad 131 is connected to a comb-like structure, and specifically, the comb-like structure includes, for example, a first comb-like structure 170 and a second comb-like structure 180 that are disposed opposite to each other, and the two comb-like structures are disposed opposite to each other and are respectively inserted into the serpentine metal wire 160 from two sides of the serpentine metal wire 160, so as to form a test unit capable of detecting a short circuit.
The first comb-shaped structure 170 is similar to the second comb-shaped structure 180, taking the first comb-shaped structure 170 as an example, the first comb-shaped structure 170 includes a comb handle 171 and a plurality of tooth-shaped metal strips 172, one ends of the plurality of tooth-shaped metal strips 172 on the same side are all connected with the comb handle 171, and the comb handle 171 of the first comb-shaped structure 170 bypasses the second sub-test pad 121 and then is connected with the comb handle of the second comb-shaped structure 180 to realize the same-layer connection; of course, the first comb-like structure 170 may also bypass the first sub-test pad 111 and be connected to the second comb-like structure 180.
In fig. 1, the serpentine wire 160 is divided into two connected sections, the two sections of serpentine wire are connected by the same layer wire, the third sub-test pad 131 is located between the two sections of serpentine wire 160, and the third sub-test pad 131 is also located between the first sub-test pad 111 and the second sub-test pad 121, and the third sub-test pad 131 is connected to the comb handle 171 of the first comb-like structure 170. Of course, the third sub-test pad 131 may be disposed at other positions, for example, the third sub-test pad 131 is disposed on the right side of the second sub-test pad 121 and connected to the comb-shaped structure.
In fact, the existing test structure shown in fig. 1 is a composite test structure, and can be used to detect short-circuit and open-circuit conditions, wherein dielectric layers (not shown) are disposed between all the toothed metal strips, and between the toothed metal strips and the serpentine metal wires, and adjacent conductive structures are insulated by the dielectric layers.
In the testing process, a first preset voltage is applied between the first sub-test pad 111 and the second sub-test pad 121, and the current value between the first sub-test pad 111 and the second sub-test pad 121 is detected; applying a second preset voltage between the first sub-test pad 111 and the third sub-test pad 131, and detecting a current value between the first sub-test pad 111 and the third sub-test pad 131; a third preset voltage is applied between the second sub-test pad 121 and the third sub-test pad 131, and the current value between the second sub-test pad 121 and the third sub-test pad 131 is detected, and whether a short circuit and/or an open circuit occurs can be determined according to the three current values.
It will be appreciated that the length of the serpentine wire and the number of toothed metal strips in the comb-like structure are positively correlated with the susceptibility of the test structure to wire open and short anomalies. The longer the serpentine wire, the more the number of teeth of the comb-like structure, and the longer the wire comb, the greater the probability of a short/open defect being trapped, with the dicing lane width and test pad spacing allowed. To further increase the sensitivity of the test structure, the width of the toothed metal strips in the test structure and the spacing between adjacent toothed metal strips, as well as the spacing between the toothed metal strips and serpentine metal lines, should be selected to be the minimum value that meets the physical design rules of the corresponding process platform.
When the test structure is open and/or shorted, the integrated circuit representing the device area of the wafer where it is located also has a high probability of having similar defects in the metal interconnect layer corresponding to the test structure. Specifically, because each test metal layer in the test structure and the metal interconnection layer of the device region are formed synchronously, whether the manufacturing process of the metal interconnection layer of the device region corresponding to the test structure is stable and normal can be fed back through detection of the test structure, so that problems can be found in time, and the generation of defective products is reduced.
As can be seen from the above description, in order to realize the monitoring of the back-end metal process, in the prior art, a set of test structures needs to be separately set for each metal interconnection layer, wherein the top metal lines are generally thicker, the distance is larger, and no monitoring pattern is required to be set, so that N-1 test structures as shown in fig. 1 need to be set for the back-end process, wherein N is the total number of layers of the metal interconnection layers; accordingly, the sum of the wafer areas occupied by the N-1 test structures is approximately S× (N-1), where S is the wafer area occupied by each test structure. In addition, when the test is performed, N-1 test structures are required to be tested one by one according to the test method, and the test times are also N-1 times. Therefore, on the premise of ensuring defect judgment and positioning accuracy, the conventional test structure is optimized to reduce the wafer area occupied by the test structure and improve the test efficiency, and has very important significance in the integrated circuit design and test process.
FIG. 2 is a schematic perspective view of a test structure according to a first embodiment of the present invention; as shown in fig. 2, the test structure includes, for example, a substrate 100, two test metal layers M1 and M2 disposed above the substrate 100 and stacked in the Z direction, and a first test electrode 110, a second test electrode 120, and a third test electrode 130 disposed above the test metal layers. Wherein, the test metal layer M1 and the test metal layer M2 each include a serpentine metal wire and a comb-shaped structure that are interposed, and the structure, the relative positional relationship, and the connection relationship with the test electrode of the serpentine metal wire and the comb-shaped structure refer to the foregoing and fig. 1, and are not described again.
The test structure provided in this embodiment includes four preset MOS transistors, which are all formed based on the substrate 100, and the preset MOS transistors may be, for example, different MOS transistors in an integrated circuit, or may be the same MOS transistor, and the performance parameters may be adjusted by changing the channel length or width of the device. Preferably, the four preset MOS transistors formed based on the substrate 100 are the same MOS transistor, that is, the formation process of the preset MOS transistor and other parameters except the channel are kept consistent, so that the turn-on voltage of the device can be finely tuned by the length and/or width of the channel, and the difference of the turn-on voltage is finely tuned and the significant difference of the turn-on current under the same bias is realized. For convenience of description, among the four preset MOS transistors, the MOS transistor 141 and the MOS transistor 142 are collectively referred to as a first preset MOS transistor 140, and are located between the first test electrode 110 and the third test electrode 130; the MOS transistor 151 and the MOS transistor 152 are collectively referred to as a second preset MOS transistor 150, and are located between the third electrode 130 and the second electrode 120.
With further reference to fig. 1, the test metal layer M1 includes a first sub-test pad 111, a second sub-test pad 121, and a third sub-test pad 131 in addition to the serpentine metal lines and the comb-tooth structure. One end of a serpentine metal wire in the test metal layer M1 is connected with a body electrode B and a source electrode S of the MOS tube 141 through a longitudinal metal plug; the gate G and the drain D of the MOS transistor 141 are connected to the first test electrode 110 through the first sub-test pads 111 and 112 by the longitudinal metal plugs, and when the MOS transistor 141 is turned on, the first test electrode 110 is electrically connected to the serpentine metal line in the test metal layer M1. Similarly, the other end of the serpentine metal wire in the test metal layer M1 is connected to the drain electrode D and the gate electrode G of the MOS transistor 151 through a longitudinal metal plug, and the source electrode S and the body electrode B of the MOS transistor 151 are connected to the second test electrode 120 through the second sub-test pads 121 and 122 through the longitudinal metal plug, so that the second test electrode 120 can be electrically connected to the serpentine metal wire in the test metal layer M1 when the MOS transistor 151 is turned on.
Test metal layer M2 is similar to M1 in that test metal layer M2 includes first sub-test pad 112, second sub-test pad 122, and third sub-test pad 132 in addition to serpentine metal lines and comb-like structures. The transverse leading-out metal wires at two ends of the serpentine metal wire in the test unit of the test metal layer M2 are staggered with the test metal layer M1 in the Y direction, so that the test units of the test metal layers are respectively connected with the corresponding MOS tubes.
One end of a serpentine metal wire in the test metal layer M2 is respectively connected with a body electrode B and a source electrode S of the MOS tube 142 through two longitudinal metal plugs; the gate G and the drain D of the MOS transistor 142 are connected to the first test electrode 110 through the first sub-test pads 111 and 112 by the vertical metal plugs, and when the MOS transistor 142 is turned on, the first test electrode 110 is electrically connected to the serpentine metal line in the test metal layer M2. Similarly, the other end of the serpentine metal wire of the test metal layer M2 is connected to the drain D and the gate G of the MOS transistor 152 through two longitudinal metal plugs, respectively, and the source S and the body B of the MOS transistor 152 are connected to the second test electrode 120 through the second sub-test pads 121 and 122 through the longitudinal metal plugs, so that the second test electrode 120 can be electrically connected to the serpentine metal wire in the test metal layer M2 when the MOS transistor 152 is turned on.
The test structure of the first embodiment includes two test metal layers, corresponding to form two parallel first test branches between the first test electrode 110 and the second test electrode 120, two parallel second test branches between the first test electrode 110 and the third test electrode 130, and two parallel third test branches between the second test electrode 120 and the third test electrode 130. One of the first test branches comprises a serpentine metal wire in the test metal layer M1, and a MOS tube 141 and a MOS tube 151 connected to two ends of the serpentine metal wire; the other first test branch includes a serpentine metal line in the test metal layer M2, and MOS transistors 142 and 152 connected to two ends of the serpentine metal line. One of the second test branches comprises a comb-tooth-shaped structure, a snake-shaped metal wire and a MOS tube 141, wherein the comb-tooth-shaped structure and the snake-shaped metal wire are arranged in the test metal layer M1, are positioned between the first test electrode 110 and the third test electrode 130 and are arranged in an interpenetration manner; the other second test branch includes a comb-shaped structure and a serpentine metal wire, which are disposed between the first test electrode 110 and the third test electrode 130 and are inserted into the test metal layer M2, and a MOS tube 142. One of the third test branches comprises a comb-tooth-shaped structure, a snake-shaped metal wire and a MOS tube 151, wherein the comb-tooth-shaped structure and the snake-shaped metal wire are arranged in the test metal layer M1, are positioned between the second test electrode 120 and the third test electrode 130 and are arranged in an inserted manner; the other third test branch includes a comb-tooth structure and a serpentine metal wire, which are disposed between the second test electrode 120 and the third test electrode 130 and are inserted into the test metal layer M2, and a MOS tube 152.
Under normal conditions, under the condition that the MOS transistor 141 and the MOS transistor 151 are both turned on, there should be a conductive path between the first sub-test pad 111 and the second sub-test pad 121, i.e. a current flows, there should be no conductive path between the first sub-test pad 111 and the third sub-test pad 131, and there should be no conductive path between the second sub-test pad 121 and the third sub-test pad 131, i.e. no current flows. Also, in the case where both MOS transistor 142 and MOS transistor 152 are on, there should be a conductive path between first sub-test pad 112 and second sub-test pad 122, i.e., a current flow, there should be no conductive path between first sub-test pad 112 and third sub-test pad 132, and there should be no conductive path between second sub-test pad 122 and third sub-test pad 132, i.e., no current flow. If the actual detection result is different from the above, it is indicated that the test structure has defects, and it is inferred that the manufacturing process of the corresponding metal interconnection layer may have problems.
Further, the currents of the two parallel first test branches under the same test voltage are different, the currents of the two parallel second test branches under the same test voltage are different, and therefore the current situation between the test electrodes is detected to feed back whether the manufacturing process of each metal interconnection layer is normal. Of course, although only two embodiments of the test metal layers are shown in fig. 2, and two ends of the serpentine metal line are respectively connected in series with one MOS tube, based on the design scheme of this embodiment, more test metal layers may be provided, and more MOS tubes may be provided correspondingly.
Further, the test units in the test metal layers may be different. In addition, the connection relation of the test units in each test metal layer is unchanged, but the arrangement directions can be mutually perpendicular; for example, the comb-shaped structures of the test metal layers M1 and M2 in fig. 2 have the tooth-shaped metal strips extending along the Y direction, so that the arrangement directions of the test units in the two test metal layers can be regarded as parallel; alternatively, the extension directions of the comb-shaped metal strips of the comb-shaped structures in the test metal layers M1 and M2 may be perpendicular to each other, that is, the arrangement directions of the test units in the two test metal layers are perpendicular.
Fig. 3a is an equivalent circuit schematic diagram of a test structure according to a first embodiment of the present invention. In order to simplify the subsequent defect analysis, the comb-tooth-shaped structures at two sides of the serpentine metal line are simplified to be illustrated in a single-side mode, and MOS tubes connected in series at two ends of the same test metal layer are identical, specifically, MOS tube 141 is identical to MOS tube 151 and is MOS1, MOS tube 142 is identical to MOS tube 152 and is MOS2, so that an internal mapping relation is set between a specific MOS tube and a specific test metal layer. In order to enable the MOS transistors to be turned on simultaneously and any one of the MOS transistors is not broken down, the difference of the turn-on voltages of the MOS1 and the MOS2 is preferably controlled to be 10%, preferably, the difference of the turn-on voltages of the MOS1 and the MOS2 is controlled to be 5%, so that all the MOS transistors in the circuit can be turned on simultaneously under the test voltage and are in a high-resistance state. Wherein the "difference" refers to the percentage of the absolute value of the maximum difference value in all the preset MOS transistors in the test structure to the larger one of the two.
It will be understood that, in order to increase the sensitivity and resolution of the test structure, the larger and better the difference of the on-current of the preset MOS transistor under the same test voltage is in the measurable range, in order to meet the above requirements, in the specific implementation process, the manufacturing process of the preset MOS transistor in the test structure is basically the same, the difference only exists in the length L and/or the width W of the channel, by controlling the size of the channel, the difference of the on-voltage of the preset MOS transistor can be within 10% or even 5% by utilizing the channel effect, and the difference of the orders of magnitude of the currents of the test branches can be realized under the same test voltage.
As can be seen from fig. 3a, one end of the serpentine metal wire in the test metal layer M1 is connected to the first test electrode 110 through the MOS1 on one side, the other end is connected to the second test electrode 120 through the MOS1 on the other side, and the comb-like structure in the test metal layer M1 is connected to the third test electrode 130; one end of the serpentine metal wire in the test metal layer M2 is connected to the first test electrode 110 through the MOS2 on one side, and the other end is connected to the second test electrode 120 through the MOS2 on the other side, and the comb-tooth structure in the test metal layer M2 is connected to the third test electrode 130.
FIG. 3b is a table showing the electrical properties of each MOS transistor in the test structure according to the first embodiment of the present invention, wherein MOS1The turn-on voltage of (C) is denoted as V t1 The turn-on voltage of MOS2 is denoted as V t2 MOS1 and MOS2 have different turn-on voltages, e.g. V t1 ＜V t2 The method comprises the steps of carrying out a first treatment on the surface of the As described above, the two MOS transistors can realize the regulation of the turn-on voltage by changing the channel size, and utilize the narrow channel or short channel effect of the device to make the turn-on voltage V t1 And V t2 The difference in (2) is controlled to be within 10%, preferably within 5%. The MOS transistor is turned on, which means that a conductive channel exists between a source electrode and a drain electrode of the device, and the source electrode and the drain electrode can be considered to be connected together through a resistor.
For each of the MOS transistors, the drain D and the gate G are shorted, and the source S and the body B are shorted, so that the drain voltage V D And gate voltage V G Equal source voltage V S And body electrode voltage V B Equal.
When the test structure is used for testing, a preset voltage is required to be applied between the first test electrode 110, the second test electrode 120 and the third test electrode 130 to measure the conduction current of the test structure under different biases. For open circuit testing, a first preset voltage V is applied between the first test electrode 110 and the second test electrode 120 1 The potential of the first test electrode is higher than that of the second test electrode, and the first preset voltage V 1 ＝2V 2 Wherein V is 2 Is a second preset voltage with a value of 0.9V t2 <V 2 <V t2 So as to ensure that four MOS tubes in the circuit can be opened or in a quasi-opened state.
A first preset voltage V on the first test electrode 1 Applied to the drain D and the gate G of the left MOS1, the MOS1 connected in series across the serpentine metal line of the test metal layer M1 is turned on, and the branch current is denoted as I 1-1 . Similarly, the first test branch where the test metal layer M2 is located is also in a conducting state, and its current is denoted as I 1-2 . Short-circuit condition of main feedback line of test between the first test electrode and the third test electrode, and between the second test electrode and the third test electrode is applied between the first test electrode and the third test electrodeA second preset voltage V 2 If the test metal layer M1 is shorted, the left MOS1 is turned on, and the current of the second test branch where the MOS1 is located is I 2-1 . Similarly, if the test metal layer M2 is shorted, the left MOS2 is turned on, and the current of the test branch where the MOS2 is located is I 2-2 . Similarly, a third preset voltage V is applied between the second test electrode and the third test electrode 3 Specifically, V 3 ＝V 2 If the test metal layer M1 is shorted, the right MOS1 is turned on, and the current of the third test branch where the MOS1 is located is I 2-1 . Similarly, if the test metal layer M2 is shorted, the right MOS2 is turned on, and the current of the test branch where the MOS2 is located is I 2-2 。
Fig. 3c is a flow chart of a testing method according to a first embodiment of the invention, as shown in fig. 3c, the testing method comprises the following steps:
in step S10, a first preset voltage is applied between the first test electrode and the second test electrode, and a first current value between the first test electrode and the second test electrode is detected; wherein, the first preset voltage V 1 The preset MOS tubes connected in series in each first test branch can be positively conducted, such as V 1 ＝2V 2 ，0.9V t2 <V 2 <V t2 And V is t2 ＞V t1 Referring to fig. 3a, if all the test metal layers are abnormal, the first current value ix=i 1-1 +I 1-2 。
In step S20, a second preset voltage is applied between the first test electrode and the third test electrode, and a second current value between the first test electrode and the third test electrode is detected; wherein the voltage value of the second preset voltage is 0.9-1 times of the highest starting voltage of all the preset MOS tubes in the two test branches, such as the second preset voltage V t2 ＞V t1 ，0.9V t2 <V 2 <V t2 As shown in fig. 3a, if all the test metal layers are abnormal, the second current value iy=0.
In step S30, a third preset voltage is applied between the second test electrode and the third test electrode to detect a second testA third current value between the test electrode and the third test electrode; wherein the third preset voltage V 3 Is equal to the second preset voltage V 2 As shown in fig. 3a, if all the test metal layers are abnormal, the third current value iz=0.
In step S40, the defect is determined and located according to the first current value, the second current value, and the third current value. Specifically, a determination reference table as shown in fig. 3d may be previously established according to the test structure of the present application, wherein the determination reference table includes mapping relationships between different combinations of the first current value Ix, the second current value Iy, and the third current value Iz and defects; judging the defects of the test structure and positioning the defects according to the comparison results of the first current value Ix, the second current value Iy and the third current value Iz and the judging comparison table; and if one or more test metal layers have short circuit and open circuit at the same time, the relative position relationship of the short circuit and the open circuit can be judged.
Fig. 3d shows a comparison table of the test structure according to the first embodiment of the present application, where a plurality of short circuit points and open circuit points occur simultaneously in the same test metal layer, i.e. at most one short circuit point in the same test metal layer, and at most one open circuit point in the same test metal layer, so that the situation of each test metal layer can be determined by comparing according to the comparison table.
FIG. 4 is a schematic perspective view of a test structure according to a second embodiment of the present invention; as shown in fig. 4, the second embodiment is similar to the first embodiment, except that the test structure of the second embodiment has three test metal layers M1, M2, M3; correspondingly, the first sub-test pads 111, 112, 113 in the three test metal layers are all connected with the first test electrode 110 on the top layer, the second sub-test pads 121, 122, 123 in the three test metal layers are all connected with the second test electrode 120 on the top layer, the third sub-test pads 131, 132, 133 in the three test metal layers are all connected with the third test electrode 130 on the top layer, three pairs of six preset MOS tubes are respectively MOS tubes 141-143 and MOS tubes 151-153 based on the substrate 100, wherein the MOS tubes 141-143 are collectively called first preset MOS tubes 140, and the MOS tubes 151-153 are collectively called second preset MOS tubes 150. In addition, the on-currents of the three MOS transistors 141-143 of the first preset MOS transistor 140 under the same bias are different, the on-currents of the three MOS transistors 151-153 of the second preset MOS transistor 150 under the same bias are also different, and in addition, the currents of each first test branch circuit under the same test voltage are also different.
FIG. 5a is an equivalent circuit diagram of a test structure according to a second embodiment of the present invention; for the sake of simplicity in subsequent defect analysis, MOS tube 141 and MOS tube 151 are both set to MOS1, MOS tube 142 and MOS tube 152 are both set to MOS2, and two MOS tubes 143 and 153 are both set to MOS3, i.e. the pair of MOS tubes corresponding to the same test metal layer are the same, and comb-tooth-shaped structures on both sides of the serpentine metal line are simplified to form a single side for illustration. Preferably, the manufacturing processes of the MOS1, the MOS2 and the MOS3 are the same, and the only difference is that the channel sizes of the MOS tubes are different, such as the channel widths and/or lengths are different, so that the fine adjustment of the starting voltages of the MOS tubes is realized, and the difference of forward conduction currents is obvious under the same bias.
Since the test structure of the second embodiment includes three test metal layers, which correspond to more abnormal conditions and the complete determination reference table is too lengthy, a partial situation is selected from the complete determination reference table to be described and described in detail, wherein fig. 5c, fig. 6b, fig. 7b and fig. 8b are all partial contents of the complete determination reference table.
FIG. 5b is a chart showing electrical performance of each MOS transistor according to the second embodiment of the present invention; similar to FIG. 3b, where the turn-on voltage of MOS1 is denoted as V t1 The turn-on voltage of MOS2 is denoted as V t2 The turn-on voltage of MOS3 is denoted as V t3 The opening voltages of the three MOS transistors are different, such as V t1 ＜V t2 ＜V t3 The method comprises the steps of carrying out a first treatment on the surface of the First preset voltage V 1 ＝2V 2 A second preset voltage V 2 And a third preset voltage V 3 Equal, V 2 ＝V 3 The method comprises the steps of carrying out a first treatment on the surface of the Wherein V is 2 The value is 0.9V t3 <V 2 <V t3 The rest of the information is not described here again, and reference is made to fig. 3b.
Fig. 5c is a decision comparison table of a test structure according to a second embodiment of the present invention. According to the equivalent circuit schematic diagram in fig. 5a, when all the test metal layers are not abnormal, i.e. the test metal layers M1, M2 and M3 are not abnormal in short circuit and open circuit, at this time, three first test branches are parallel connected in the circuit between the first test electrode 110 and the second test electrode 120, the first test branch where the test metal layer M1 is located includes two MOS1, the first test branch where the test metal layer M2 is located includes two MOS2, the first test branch where the test metal layer M3 is located includes two MOS3, the comb-tooth structure in the three test metal layers and the serpentine metal wire are not connected (shorted), and the second test branch between the first test electrode 110 and the third test electrode 130, and the third test branch between the second test electrode 120 and the third test electrode 130 are not conductive.
Applying a first preset voltage V between the first test electrode 110 and the second test electrode 120 1 At a first preset voltage V 1 Under, all of MOS1, MOS2 and MOS3 are opened, and all of three first test branches are conducted, and at this time, the first current value Ix of the circuit is: ix=i 1-1 +I 1-2 +I 1-3 ；
Applying a second preset voltage V between the first test electrode 110 and the third test electrode 130 2 Since none of the three second test branches is turned on, there is no conductive loop between the first test electrode 110 and the third test electrode 130, so the second current value iy=0 between the first test electrode 110 and the third test electrode 130;
applying a third preset voltage V between the second test electrode 120 and the third test electrode 130 3 ，V 3 ＝V 2 Since none of the three third test branches is turned on, there is no conductive loop between the second test electrode 120 and the third test electrode 130, so the third current value iz=0 between the second test electrode 120 and the third test electrode 130.
FIG. 6a is a schematic diagram of an equivalent circuit of a test structure according to a second embodiment of the present invention, wherein only a short circuit abnormality occurs; specifically, for example, the test metal layer M1 and the test metal layer M2 are short-circuited at the same time, and have no open-circuit abnormality.
Applying a first preset voltage V between the first test electrode 110 and the second test electrode 120 1 The potential of the first test electrode 110 is higher than that of the second test electrode 120, at a first preset voltage V 1 Under the condition that MOS1, MOS2 and MOS3 are all on, the first current value Ix=I of the circuit 1-1 +I 1-2 +I 1-3 ；
Applying a second preset voltage V between the first test electrode 110 and the third test electrode 130 2 The potential of the first test electrode 110 is higher than that of the third test electrode 130, and since the test metal layers M1 and M2 are shorted together, a via is formed in both the test metal layers M1 and M2, the MOS1 on the left side of the test metal layer M1 is turned on, the MOS2 on the left side of the test metal layer M2 is turned on, and at this time, the second current value iy=i of the circuit 2-1 +I 2-2 ；
Applying a third preset voltage V between the second test electrode 120 and the third test electrode 130 3 ，V 3 ＝V 2 The potential of the third test electrode 130 is higher than that of the second test electrode 120, and since the test metal layers M1 and M2 are shorted together, a via is formed in both the test metal layers M1 and M2, the MOS1 on the right side of the test metal layer M1 is turned on, the MOS2 on the right side of the test metal layer M2 is turned on, and at this time, the second current value iz=i of the circuit 2-1 +I 2-2 。
By analogy, when there is only a short-circuit abnormality, the determination and localization of the defect can be performed according to the determination map two shown in fig. 6 b.
FIG. 7a is a schematic diagram of an equivalent circuit of a test structure according to a second embodiment of the present invention, wherein only open-circuit anomalies occur; specifically, for example, the test metal layer M1 and the test metal layer M2 are open at the same time, where the first test electrode 110 and the second test electrode 120 are equivalent to only two MOS3 connected in series in the circuit, and no via is formed between the first test electrode 110 and the third test electrode 130, and between the second test electrode 120 and the third test electrode 130, which are the same as those shown in fig. 5 a.
Applying a first preset voltage V between the first test electrode 110 and the second test electrode 120 1 Both MOS3 are on, when the first current value ix=i of the circuit 1-3 The method comprises the steps of carrying out a first treatment on the surface of the To between the first test electrode 110 and the third test electrode 130Applying a second preset voltage V 2 The corresponding second current value iy=0; applying a third preset voltage V between the second test electrode 120 and the third test electrode 130 3 The corresponding third current value iz=0.
By analogy, when there is only an open abnormality, the determination and localization of the defect can be performed according to the determination map three shown in fig. 7 b.
FIG. 8a is a schematic diagram of an equivalent circuit of a test structure according to a second embodiment of the present invention with both short and open anomalies; specifically, assuming that the test metal layer M1 has a short circuit and an open circuit at the same time, the test metal layer M2 has a short circuit and an open circuit at the same time, and the test metal layer M3 has no abnormality.
Analyzing such a situation, it is also necessary to consider the relative positions of the short-circuit abnormality and the open-circuit abnormality in the same layer in the test structure, as shown in fig. 8a, in which the short-circuit point in the test metal layer M1 is located at the left side of the open-circuit point, and neither MOS1 is connected to the circuit between the first test electrode 110 and the second test electrode 120 due to the presence of the open-circuit abnormality. Since the short-circuit abnormality exists and the short-circuit point is located to the left of the open-circuit point, a second preset voltage V is applied between the first test electrode 110 and the third test electrode 130 2 In this case, the left MOS1 is connected to the circuit between the first test electrode 110 and the third test electrode 130, and the left MOS1 and the right MOS1 are not connected to the circuit between the second test electrode 120 and the third test electrode 130.
The abnormal condition of the test metal layer M2 is similar to that of the test metal layer M1, and only the relative positions of the open-circuit point and the short-circuit point are different. At this time, a first preset voltage V is applied between the first test electrode 110 and the second test electrode 120 1 The third test electrode 130 is grounded at a first predetermined voltage V 1 Next, the two MOS3 are turned on, and at this time, the first current value ix=i of the circuit 1-3 The method comprises the steps of carrying out a first treatment on the surface of the Applying a second preset voltage V between the first test electrode 110 and the third test electrode 130 2 Corresponding second current value iy=i 2-1 The method comprises the steps of carrying out a first treatment on the surface of the Applying a third preset voltage V between the second test electrode 120 and the third test electrode 130 3 Corresponding third current value iz=i 2-2 。
By analogy, in the case where the same test metal layer has both a short circuit and an open circuit, the defect can be judged and located according to the judgment reference table four shown in fig. 8 b. Moreover, by adopting the test structure, the specific abnormal conditions of different test metal layers can be determined, and the relative positions of the short-circuit abnormal points and the open-circuit abnormal points can be qualitatively given, so that the failure analysis and positioning are very facilitated.
The above embodiments do not consider the situation that a plurality of short circuit points and open circuit points occur in the same test metal layer at the same time, and the judging and comparing tables one to four show only partial abnormal situations, but can analogically obtain a complete judging and comparing table according to the above embodiments, and directly compare the first current value, the second current value and the third current value obtained by testing with the complete judging and comparing table during actual testing, so as to obtain the abnormal situations of short circuit and open circuit of each test metal layer, and judge whether the corresponding metal wiring layer (metal interconnection layer) of the die area (device area) is abnormal or not according to the abnormal situations, and infer the specific situations such as abnormal positions. In addition, if the statistics of each comparison table is carried out, when one or a plurality of test metal layers have short circuit and open circuit abnormality at the same time, the structure can also provide the relative position relation of the short circuit and open circuit abnormal points, and the position information has important guiding significance for the development of subsequent failure analysis.
According to the test structure provided by the invention, the short circuit and open circuit compound test units which are arranged in a layered manner are integrated in the same test structure, and each compound test unit and the corresponding sub-test pad and the like form a test metal layer. A pair of MOS tubes are connected in series between the test metal layer and the test electrode, so that various short circuit or open circuit abnormal conditions and current values form a one-to-one mapping relation. Compared with the prior art, the wafer area occupied by the test structure is reduced to 1/(N-1) of the prior test structure, wherein N is the total number of metal interconnection layers in the integrated circuit, so that the wafer area occupied by the test structure is effectively saved.
In the actual test process, compared with the prior test structure which is arranged in a layered manner, the test structure provided by the invention only needs one test, namely the test times are reduced to 1/(N-1) of the prior test times, so that the test times can be greatly reduced, and the test efficiency is obviously improved; particularly, by means of the judging comparison table provided by the invention, the problem of short circuit and open circuit can be rapidly locked in which one or more test metal layers are specific, the relative positions of short circuit and open circuit abnormality in the same test metal layer can be judged, and the test result can provide an important clue for subsequent failure analysis and positioning. Furthermore, the difference of the starting voltages of the MOS tubes of each test metal layer can be utilized to conduct the MOS tube of the corresponding test metal layer through a specific voltage so as to eliminate the interference of other test metal layers.
It should be noted that in the description of the present invention, the terms "first," "second," and the like are merely used for convenience in describing different orientations, components, and assemblies and are not to be construed as indicating or implying a sequential relationship, relative importance, or implicitly indicating the number of technical features indicated.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, and various modifications and variations may be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (11)
1. A test structure, comprising:
a substrate;
at least two test metal layers positioned on the substrate, wherein each test metal layer comprises a serpentine metal wire and a comb-shaped structure which are arranged alternately;
the first test electrode is connected with the first end of the serpentine metal wire in each test metal layer respectively, the second test electrode is connected with the second end of the serpentine metal wire in each test metal layer respectively, the third test electrode is connected with the comb-shaped structure in each test metal layer, at least two first test branches are formed between the first test electrode and the second test electrode, at least two second test branches are formed between the first test electrode and the third test electrode, and at least two third test branches are formed between the second test electrode and the third test electrode;
A first preset MOS tube is connected in series between the first test electrode and the first end of the serpentine metal wire in each test metal layer, and a second preset MOS tube is connected in series between the second test electrode and the second end of the serpentine metal wire in each test metal layer; the current of each first test branch circuit under the same test voltage is different, the current of each second test branch circuit under the same test voltage is different, and the current of each third test branch circuit under the same test voltage is different.
2. The test structure of claim 1, wherein the first preset MOS transistor and the second preset MOS transistor in the same first test leg are the same.
3. The test structure of claim 1 or 2, wherein the first preset MOS transistor and the second preset MOS transistor in the same first test branch are capable of achieving forward series connection through a serpentine metal wire.
4. A test structure according to any one of claims 1-3, wherein in the test structure, the difference in turn-on voltages of all the first preset MOS transistors and the second preset MOS transistors is not more than 10%.
5. The test structure of claim 4, wherein the first preset MOS transistor and the second preset MOS transistor are each formed based on the substrate.
6. The test structure of claim 1 or 2, wherein the third test electrode is located between the first test electrode and the second test electrode;
the serpentine metal wire comprises two parts which are connected, wherein one part is positioned between the first test electrode and the third test electrode, and the other part is positioned between the third test electrode and the second test electrode.
7. The test structure of claim 6, wherein the comb-like structure comprises a first comb-like structure and a second comb-like structure that are interspersed with the serpentine metal wire from both sides of the serpentine metal wire, respectively.
8. The test structure of claim 7, wherein the comb-like structure comprises a comb handle and a plurality of comb-like metal strips connected to the comb handle, the comb handle of the first comb-like structure and the comb handle of the second comb-like structure being connected at a location that bypasses one end of the serpentine metal wire.
9. A test method, characterized in that a test structure according to any one of claims 1-8 is used, the test method comprising the steps of:
applying a first preset voltage between the first test electrode and the second test electrode, and detecting a first current value between the first test electrode and the second test electrode, wherein the first preset voltage can enable a first preset MOS tube and a second preset MOS tube in a first test branch to be conducted forward;
Applying a second preset voltage between the first test electrode and the third test electrode, and detecting a second current value between the first test electrode and the third test electrode, wherein the second preset voltage can enable a first preset MOS tube in a second test branch to be conducted in a forward direction;
applying a third preset voltage between the second test electrode and the third test electrode, and detecting a third current value between the second test electrode and the third test electrode, wherein the third preset voltage can enable a second preset MOS tube in a third test branch to be conducted in the forward direction;
and judging and positioning the defect according to the first current value, the second current value and the third current value.
10. The method of testing of claim 9, further comprising:
establishing a judging comparison table, wherein the judging comparison table comprises mapping relations between different combinations of the first current value and the third current value and defects;
and judging and positioning the defects according to the comparison results of the first current value to the third current value and the judging comparison table.
11. The test method according to claim 9 or 10, wherein the voltage value of the first preset voltage is twice the voltage value of the second preset voltage; the voltage value of the third preset voltage is the same as the voltage value of the second preset voltage ， IA23000075 of the second preset voltage
The voltage value is 0.9-1 times of the highest starting voltage in the first preset MOS tube and the second preset MOS tube.
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