CN116266579A - Test structure and test method - Google Patents
Test structure and test method Download PDFInfo
- Publication number
- CN116266579A CN116266579A CN202310198529.8A CN202310198529A CN116266579A CN 116266579 A CN116266579 A CN 116266579A CN 202310198529 A CN202310198529 A CN 202310198529A CN 116266579 A CN116266579 A CN 116266579A
- Authority
- CN
- China
- Prior art keywords
- test
- sub
- test structure
- electrode
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 362
- 238000010998 test method Methods 0.000 title claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 141
- 229910052751 metal Inorganic materials 0.000 claims abstract description 141
- 230000007547 defect Effects 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 16
- 238000002513 implantation Methods 0.000 claims description 11
- 230000002159 abnormal effect Effects 0.000 claims description 8
- 244000126211 Hericium coralloides Species 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 claims description 5
- WYTGDNHDOZPMIW-RCBQFDQVSA-N alstonine Natural products C1=CC2=C3C=CC=CC3=NC2=C2N1C[C@H]1[C@H](C)OC=C(C(=O)OC)[C@H]1C2 WYTGDNHDOZPMIW-RCBQFDQVSA-N 0.000 claims description 4
- 229910021332 silicide Inorganic materials 0.000 claims description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 3
- 239000007943 implant Substances 0.000 claims 4
- 239000010410 layer Substances 0.000 description 105
- 238000010586 diagram Methods 0.000 description 15
- 238000004519 manufacturing process Methods 0.000 description 11
- 238000001514 detection method Methods 0.000 description 6
- 239000002356 single layer Substances 0.000 description 5
- 238000013461 design Methods 0.000 description 4
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004832 voltammetry Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The application discloses a test structure and a test method, which are used for solving the problems of lower test efficiency and redundancy of structural arrangement in the prior art. The test structure comprises: a substrate; at least two test metal layers, each of which is provided with a sub-test structure, wherein the sub-test structure comprises a first sub-test structure and a second sub-test structure; the first test electrode is respectively connected with the first sub-test structure in each test metal layer; a second test electrode connected to the second sub-test structure in each test metal layer; and a preset resistor is further arranged between the first test electrode and the first sub-test structure of each test metal layer, and the resistance values of the preset resistors between the first sub-test structures of different test metal layers and the first test electrode are different. The test structure can detect a plurality of metal layers at the same time, and can judge whether the test structure has short circuit defects and the positions of the defects by a single test, so that the number of the test structures is greatly reduced, and the test efficiency is improved.
Description
Technical Field
The invention relates to the technical field of electrical testing, in particular to a testing structure and a testing method.
Background
The most typical features of integrated circuit development include: the shrinking of front-end device feature sizes and the increasing complexity of back-end metal routing. The back-end metal process mainly provides working power or signal paths for all ports of the front-end device through electric connection. Therefore, the post metal interconnection process is important.
In order to monitor the stability of the back-end metal interconnect process, various electrical characteristics of the metal, such as sheet resistance of the metal, connectivity of the metal, and shorting between metals, are monitored in addition to the management of the process data. Because the main function of metal is to serve as an interconnect, shorting between adjacent metal lines due to process anomalies is one of the important electrical test items.
The existing test structure for the rear-section metal short circuit follows the principle of layering and independent setting, namely, one layer of metal is provided with one set of test patterns, so that the design has strong pertinence, the problem tracing can be realized very conveniently, and obvious defects exist. Because the metal layer of the nano-scale semiconductor manufacturing process is usually up to 6-10 layers, if the test structure is set according to the principle, on one hand, the required test pattern is formed, a large amount of dicing area on the wafer is occupied, and on the other hand, each test pattern of each layer needs to be electrically tested, so that the test resources are wasted.
Therefore, how to reduce the occupation of test resources, improve the test efficiency and determine the position of the defect in time is a technical problem to be solved by the technicians in the field.
Disclosure of Invention
In view of the foregoing, the present invention provides a test structure and a test method, wherein the test structure can detect a plurality of test metal layers at the same time, and a single test can determine whether a short circuit defect exists and which test metal layer or layers the defect is located in when the short circuit defect exists.
To achieve the above object, a first aspect of the present invention provides a test structure, comprising: a substrate; at least two test metal layers, each of which is provided with a sub-test structure, wherein the sub-test structure comprises a first sub-test structure and a second sub-test structure; the first test electrode is respectively connected with the first sub-test structure in each test metal layer; a second test electrode connected to the second sub-test structure in each test metal layer; and a preset resistor is further arranged between the first test electrode and the first sub-test structure of each test metal layer, and the resistance values of the preset resistors between the first sub-test structures of different test metal layers and the first test electrode are different.
Preferably, each test metal layer is provided with the same or different sub-test structures.
Preferably, the first sub-test structure and the second sub-test structure comprise at least one of a comb-tooth structure and a serpentine structure.
Preferably, the sub-test structures on adjacent test metal layers are arranged in a consistent or mutually perpendicular direction.
Preferably, the first sub-test structure and the second sub-test structure comprise oppositely arranged comb-shaped structures, each comb-shaped structure comprises a comb handle and a plurality of tooth-shaped metal strips connected with the comb handle, and the tooth-shaped metal strips of the first sub-test structure and the tooth-shaped metal strips of the second sub-test structure are mutually inserted.
Preferably, the preset resistor is located in the substrate, and the preset resistor is a diffusion resistor.
Preferably, the preset resistor is formed by at least one implantation mode of well implantation, vt implantation, light doping implantation and source/drain implantation.
Preferably, the difference in resistance between the different preset resistances is achieved by at least one of changing the diffusion region size, using different implantation processes, and covering the silicide.
Another aspect of the present invention provides a testing method for testing a test structure as described in any one of the preceding claims, comprising the steps of: applying a voltage between the first test electrode and the second test electrode to detect leakage current; if the leakage current between the first test electrode and the second test electrode is not greater than the leakage preset value, all the test metal layers of the test structure have no short circuit defect; if the leakage current between the first test electrode and the second test electrode is larger than a preset value, detecting the resistance between the first test electrode and the second test electrode to obtain a test resistance value; and comparing the test resistance with an abnormal comparison table predetermined according to the method, and positioning the short-circuit defect.
Preferably, the leakage preset value is 10 -10 And A, the resistance value of the preset resistor is far larger than the maximum resistance value of any sub-test structure when communicated.
According to the test structure and the test method, the plurality of metal layers are integrated in the same test structure to serve as the test metal layers, and each test metal layer in the test structure is connected in series with one corresponding preset resistor to calibrate, so that the problem that whether the plurality of test metal layers have short circuits or not can be rapidly detected through single test, meanwhile, the problem of short circuits can be rapidly positioned on one or more test metal layers, multiple tests are not needed, monitoring of all the test metal layers, namely manufacturing processes of all the corresponding metal layers on a wafer can be achieved through single test, time and test resources required by the test are greatly reduced, and the test efficiency is remarkably improved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings. Moreover, for the sake of clarity, various parts in the drawings are not drawn to scale.
FIG. 1 is a schematic diagram of a conventional single layer test structure;
FIG. 2 is a schematic diagram of a multi-layer test structure that is simply integrated from the single-layer test structure shown in FIG. 1;
FIG. 3 is a schematic diagram of a test structure according to a first embodiment of the present invention;
FIG. 4 is an equivalent schematic diagram of a test structure according to a first embodiment of the present invention;
FIG. 5 is a schematic diagram of a testing method of a testing structure according to a first embodiment of the present invention;
FIG. 6 is a schematic diagram showing a short circuit occurring in a single test metal layer in a test structure according to a first embodiment of the present invention;
FIG. 7 is a schematic diagram showing a plurality of test metal layers in a test structure according to a first embodiment of the present invention;
FIG. 8 is an anomaly lookup table of a test structure according to a first embodiment of the present invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. The invention is not limited to these embodiments only. In the following detailed description of the present invention, certain specific details are set forth in detail. The present invention will be fully understood by those skilled in the art without the details described herein. Well-known methods, procedures, and flows have not been described in detail so as not to obscure the nature of the invention.
Fig. 1 is a schematic diagram of a conventional single-layer test structure, where the single-layer test structure includes a first test pad 11, a first sub-test structure 13, a second test pad 12 and a second sub-test structure 14, where the first sub-test structure 13 and the second sub-test structure 14 form a sub-test structure, the first sub-test structure 13 is connected to the first test pad 11 through a metal wire, the second sub-test structure 14 is connected to the second test pad 12 through a metal wire, specifically, the first sub-test structure 13 and the second sub-test structure 14 are disposed opposite to each other, the first sub-test structure 13 and the second sub-test structure 14 are, for example, both are similar in shape, and the first sub-test structure 13 includes a comb handle 131 and a plurality of toothed metal strips 132, one end of the plurality of toothed metal strips 132 on the same side is connected to the comb handle 131, the comb handle 131 is connected to the first test pad 11 through a metal wire, the plurality of toothed metal strips of the first sub-test structure 13 and the second sub-test structure 14 are disposed opposite to each other, and all of the toothed metal strips are further disposed between adjacent to each other (the metal strips are not shown in the dielectric layer) by insulating medium layer). A voltage is applied between the first test pad 11 and the second test pad 12, and whether leakage current exists between the first test pad 11 and the second test pad 12 is detected to feed back whether the manufacturing process of the layer where the sub-test structure is located is normal, and under normal conditions, no conductive path exists between the first test pad 11 and the second test pad 12, that is, under ideal conditions, the first test pad 11 and the second test pad 12 are open circuits, and the manufacturing process of the sub-test structure is normal. If there is a conductive path between the first test pad 11 and the second test pad 12, this indicates that there is a defect in the sub-test structure, and the manufacturing process of the sub-test structure may be problematic.
The child test structure is made into a comb-tooth shape so as to increase the area of the test structure and improve the probability of capturing abnormal conditions. The longer the number of comb teeth, the longer the metal comb teeth, and the greater the probability of capturing a short defect, with the dicing street width and test pad spacing allowed. To further increase the sensitivity of the subtest structure, the width of the toothed metal strips and the spacing between adjacent toothed metal strips in the subtest structure should be selected to be the minimum value that meets the physical design rules of the corresponding process platform. When the sub-test structure is shorted, bridging defects are likely to occur in the layer manufacturing process on the circuit in the wafer where the sub-test structure is located.
Because each test metal layer in the test structure and the metal layer in the device are synchronously formed, whether the manufacturing process of the device metal layer corresponding to the test structure is stable and normal can be fed back through the test structure and the detection of the test structure, so that problems can be found in time, and the generation of defective products is reduced.
FIG. 2 is a schematic diagram of a multi-layer test structure in which the single-layer metal test structure shown in FIG. 1 is simply integrated; in fig. 2, there are three test metal layers M1, M2, M3, and a first test electrode 21 and a second test electrode 22, and a first sub-test structure 23 and a second sub-test structure 24 for forming sub-test structures in each test metal layer, insulation is achieved between adjacent test metal layers by dielectric layers, and fig. 2 is different from fig. 1 in that three test metal layers M1, M2, M3 are included, and the sub-test structures in each test metal layer are similar to those in fig. 1, for example, wherein the first sub-test structure 23 and the second sub-test structure 24 are respectively connected to test metal pads in the same layer, and the metal pads on the same side in the test metal layers M1, M2, M3 are electrically connected to the first test electrode 21 and the second test electrode 22 located on the top layer through longitudinal metal and through holes. Although the testing structure simply integrates the sub-testing structures of all layers into the same testing structure through longitudinal metal and through holes, and achieves the aim of reducing the detection times, the design can only distinguish two conditions that all the testing metal layers have no short circuit and some testing metal layers have short circuits, and can not accurately position which layer or layers the short circuit is positioned on, once the short circuit condition is detected, the manufacturing processes of all the metal layers need to be checked one by one, and the problem tracing and the problem checking are not facilitated.
FIG. 3 is a schematic diagram of a test structure according to a first embodiment of the present invention; the test structure of this embodiment includes: a substrate, a test metal layer M1, a test metal layer M2, a test metal layer M3, and a first test electrode 31 and a second test electrode 32 on the top layer. The test structure of this first embodiment is similar to that of fig. 2, and also has three test metal layers, each of which also has a first sub-test structure 33 and a second sub-test structure 34 disposed opposite to each other, in which the lateral lead-out metal lines of the first sub-test structures 33 of each test metal layer are staggered in the Y direction, so that the first sub-test structures 33 of each test metal layer are connected to one ends of preset resistors R1, R2, R3 on the substrate (as shown in the region a of fig. 3), the first sub-test structures 33 of the test metal layers M1, M2, M3 are connected to the first test electrode 31 through the longitudinal metal and through holes in the substrate after passing through the preset resistors R1, R2, R3, and specifically, the first sub-test structures 33 of the test metal layers M1 are connected to the first test electrode 31 through the preset resistor R1, and the first sub-test structures 33 of the test metal layers M2 are connected to the first test electrode 31 through the preset resistor R3. Namely, each test metal layer is connected in series with a preset resistor, the resistance value of the preset resistor corresponding to each test metal layer is different, voltage is applied between the first test electrode 31 and the second test electrode 32, the resistor between the first test electrode 31 and the second test electrode 32 is detected, and then the test metal layer or the test metal layers which are short-circuited (namely, have metal bridging) can be rapidly locked through the resistance value, so that problems can be traced and examined.
Specifically, the three preset resistors R1 to R3 are diffusion resistors, for example, and the resistivity thereof is 10 to 10, for example 3 The ohmic/square block is formed by ion implantation on the substrate, including N/P well implantation, voltage modulation (Vt) implantation, lightly doped implantation (Lightly Doped Drain, LDD) and source/drain implantation. The larger the difference of the resistance values of the three preset resistors is, the better the sensitivity and the signal-to-noise ratio of the test structure are. The difference between the preset resistances can be calculated by: setting different diffusion region sizes under the same injection process condition; different injection processes are adopted; or whether silicide is covered or not, the resistance value of the preset resistor can be obviously adjusted. Each test metal layer is provided with a sub-test structure consisting of a first sub-test structure 33 and a second sub-test structure 34, namely, three groups of sub-test structures are respectively positioned on the three test metal layers in the longitudinal direction, and the arrangement directions of the sub-test structures on the adjacent test metal layers are consistent or mutually perpendicular.
Of course, although only three embodiments of the test metal layers are shown in fig. 3, more test metal layers and corresponding preset resistors may be provided based on the design of the embodiments; although the first sub-test structure 33 and the second sub-test structure 34 are both comb-shaped structures in the above description, they may be configured into other shapes such as serpentine structures according to actual needs, and further, the sub-test structures in the above test metal layers may be different, for example, the sub-test structure in the test metal layer M1 is comb-shaped, and the sub-test structure in the test metal layer M2 is serpentine.
Fig. 4 is an equivalent schematic diagram of a test structure according to a first embodiment of the present invention, and as can be seen from fig. 4, one end of a preset resistor R1 is connected to a first test electrode 31 through a metal connection line and a through hole, and the other end of the preset resistor R1 is connected to a comb handle of a first sub-test structure of the sub-test structure; the preset resistor R2 and the preset resistor R3 are similar to the preset resistor R1, and will not be described herein. In the simplified equivalent schematic diagram, the first sub-test structures of the test metal layer M1, the test metal layer M2 and the test metal layer M3 are respectively connected in series with the preset resistor R1, the preset resistor R2 and the preset resistor R3. Through the preset resistors with different resistance values connected in series with different test metal layers, the calibration of the resistance value can be realized, fault location can be rapidly carried out through the measured resistance value when the test is carried out in the later period, which one or more test metal layers the short circuit is positioned in is determined, and the process corresponding to the test metal layers is checked.
FIG. 5 is a schematic diagram of a testing method of a testing structure according to a first embodiment of the present invention; as shown in fig. 5, the test method of the test structure according to the first embodiment of the present invention includes the following steps:
in step S10, a voltage is applied between the first test electrode and the second test electrode to detect leakage current; for example, the voltage is 5V, and the leakage current is lower than the preset leakage value of 10 due to the fact that the first test electrode and the second test electrode are not conducted under normal conditions -10 A。
If the leakage current is greater than the leakage preset value, executing step S20, in step S20, calculating the resistance between the first test electrode and the second test electrode by using a simple voltammetry to obtain a test resistance value, and executing step S30;
in step S30, the test resistance is compared with an abnormal comparison table, and the short circuit defect is located by the abnormal comparison table, so as to determine the position of the short circuit, so as to facilitate the subsequent investigation.
If the leakage current is not greater than the leakage preset value, the test structure shows that all the test metal layers have no short circuit defect, and the manufacturing process for forming each test metal layer is stable and normal.
In the following, it will be illustrated how the position of a short circuit is determined after the occurrence of a short circuit for the test structure according to the first embodiment of the present invention. Fig. 6 is a schematic diagram of a short circuit point occurring in the test metal layer M1, fig. 7 is a schematic diagram of a short circuit point occurring in both the test metal layers M1 and M3, and fig. 8 is a corresponding abnormal comparison table. The resistance of each preset resistor is usually much larger than the maximum resistance when any sub-test structure in the test structure is communicated, so the resistance (generally mΩ level) of the metal wire itself is negligible.
As shown in fig. 6, assuming that a short circuit point occurs in the sub-test structure of the test metal layer M1, a closed loop is formed between the first test electrode 31 and the second test electrode 32, so as to generate a first leakage path 101, at this time, only a preset resistor R1 is connected in series into the first leakage path 101, and in the case of neglecting the self resistance of the metal wire, the equivalent resistance of the first leakage path 101 is approximately equal to R1, that is, the test resistor R between the first test electrode 31 and the second test electrode 32 is detected, and then r=r1 is detected, and according to the abnormal comparison table shown in fig. 8, it is indicated that the test metal layer M1 of the test structure has a short circuit. Similarly, for example, when the test metal layers M2/M3 are short-circuited, the equivalent resistance of the circuit should be R2/R3. Therefore, when a short circuit occurs in a certain test metal layer, by measuring the resistance of the leakage path, it is possible to quickly determine which test metal layer has a short circuit.
As shown in fig. 7, assuming that short-circuit points appear in the subtest structures of the test metal layer M1 and the test metal layer M3, two closed loops are formed between the first test electrode 31 and the second test electrode 32, including a first leakage path 101 and a second leakage path 102, and similarly, an equivalent circuit of the two leakage paths is equivalent to a preset resistor R1 and a preset resistor R3 connected in parallel in a circuit, and a calculation formula of the equivalent resistor R in the parallel circuit is as follows:
when the resistance value of the test resistor R between the first test electrode 31 and the second test electrode 32 is the result of the calculation of the above formula, it can be inferred that the test metal layer M1 and the test metal layer M3 are shorted at the same time.
Similarly, the test metal layer M1 and the test metal layer M2 are shorted together, and the test metal layer M2 and the test metal layer M3 are shorted together, so that detection and judgment modes are similar, and are not repeated.
The other extreme case is that the test metal layers M1 to M3 are shorted together (not shown), and it can be inferred from the equivalent circuit of the leakage path, for example, the resistance of the test resistor R is calculated by the following formula,
it is indicated that the test metal layers M1 to M3 are shorted at the same time.
According to the equivalent circuit of the leakage path under different conditions, an abnormal comparison table as shown in fig. 8 can be obtained through calculation, and when the detection is actually carried out, the detection conclusion can be rapidly obtained by comparing the resistance value of the test resistor R with the content in the table, and the position of the short circuit is determined.
Further, the above description is made by taking three test metal layers as examples, but according to the scheme of the invention, more test metal layers can be provided, namely, the detection of the multi-layer test metal layers can be realized through a single test, if a short circuit occurs, the specific position of the short circuit can be determined, and then the manufacturing process of the test metal layer where the short circuit is located is traced and adjusted, so that the problem point is located in time, the test efficiency is improved, and the time and the resource are saved.
According to the test structure and the test method, the plurality of metal layers are integrated in the same test structure, and the corresponding preset resistor is connected in series to each test metal layer in the test structure for calibration, so that the problem that whether the plurality of test metal layers are short-circuited or not can be rapidly detected by single test, meanwhile, the problem of short-circuited can be rapidly positioned on one or more test metal layers, multiple tests are not needed, the monitoring of the manufacturing process of all the metal layers can be realized by single test, the time and the test resources required by the test are greatly reduced, and the test efficiency is remarkably improved.
It should be noted that in the description of the present invention, the terms "first," "second," and the like are merely used for convenience in describing different orientations, components, and assemblies and are not to be construed as indicating or implying a sequential relationship, relative importance, or implicitly indicating the number of technical features indicated.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, and various modifications and variations may be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A test structure, comprising:
a substrate;
at least two test metal layers, each of which is provided with a sub-test structure, wherein the sub-test structure comprises a first sub-test structure and a second sub-test structure;
the first test electrode is respectively connected with the first sub-test structure in each test metal layer;
a second test electrode connected to the second sub-test structure in each test metal layer;
and a preset resistor is further arranged between the first test electrode and the first sub-test structure of each test metal layer, and the resistance values of the preset resistors between the first sub-test structures of different test metal layers and the first test electrode are different.
2. The test structure of claim 1, wherein the same or different sub-test structures are provided on each test metal layer.
3. The test structure of claim 1, wherein the first sub-test structure and the second sub-test structure comprise at least one of a comb-tooth structure, a serpentine structure.
4. The test structure of claim 1, wherein the sub-test structures on adjacent test metal layers are aligned in a uniform or perpendicular direction.
5. The test structure of claim 1, wherein the first sub-test structure and the second sub-test structure comprise oppositely disposed comb-tooth structures, the comb-tooth structures comprising a comb handle and a plurality of toothed metal strips connected to the comb handle, the toothed metal strips of the first sub-test structure and the toothed metal strips of the second sub-test structure being interspersed with each other.
6. The test structure of claim 1, wherein the predetermined resistance is located in the substrate, the predetermined resistance being a diffused resistance.
7. The test structure of claim 6, wherein the pre-set resistance is formed by at least one of well implant, vt implant, lightly doped implant, source/drain implant.
8. The test structure of claim 6, wherein the difference in resistance between different preset resistances is achieved by at least one of changing diffusion dimensions, using different implantation processes, and covering the silicide.
9. A test method for testing a test structure according to any one of claims 1-8, comprising the steps of:
applying a voltage between the first test electrode and the second test electrode to detect leakage current;
if the leakage current between the first test electrode and the second test electrode is not greater than the leakage preset value, all the test metal layers of the test structure have no short circuit defect;
if the leakage current between the first test electrode and the second test electrode is larger than a preset value, detecting the resistance between the first test electrode and the second test electrode to obtain a test resistance value;
and comparing the test resistance with an abnormal comparison table predetermined according to the method, and positioning the short-circuit defect.
10. The method according to claim 9, wherein the leakage preset value is 10 -10 And A, the resistance value of the preset resistor is far larger than the maximum resistance value of any sub-test structure when communicated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310198529.8A CN116266579A (en) | 2023-03-01 | 2023-03-01 | Test structure and test method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310198529.8A CN116266579A (en) | 2023-03-01 | 2023-03-01 | Test structure and test method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116266579A true CN116266579A (en) | 2023-06-20 |
Family
ID=86744485
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310198529.8A Pending CN116266579A (en) | 2023-03-01 | 2023-03-01 | Test structure and test method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116266579A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116884956A (en) * | 2023-09-06 | 2023-10-13 | 合肥晶合集成电路股份有限公司 | Capacitor test structure, manufacturing method and test method |
-
2023
- 2023-03-01 CN CN202310198529.8A patent/CN116266579A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116884956A (en) * | 2023-09-06 | 2023-10-13 | 合肥晶合集成电路股份有限公司 | Capacitor test structure, manufacturing method and test method |
| CN116884956B (en) * | 2023-09-06 | 2023-12-26 | 合肥晶合集成电路股份有限公司 | Capacitor test structure, manufacturing method and test method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4395158B2 (en) | Wiring test structure and method (wiring test structure for determining open circuit and short circuit in a semiconductor device) | |
| US7749778B2 (en) | Addressable hierarchical metal wire test methodology | |
| CN116266579A (en) | Test structure and test method | |
| CN113224035B (en) | Semiconductor test structure and test method | |
| US7365529B2 (en) | Test structure design for reliability test | |
| JP2004085247A (en) | Probe card | |
| KR100295916B1 (en) | Test Structure and Method for Measuring Minimum Area Design Rule | |
| CN112986772B (en) | Dielectric breakdown test circuit and test method thereof | |
| CN113506755A (en) | Checking graph structure for automatically detecting test channel and test method | |
| CN116403992A (en) | Test structure and test method | |
| CN116705768A (en) | Test structure and test method | |
| US6894513B2 (en) | Multipoint plane measurement probe and methods of characterization and manufacturing using same | |
| JPH11101841A (en) | Conductive paste through hole type double-sided printed wiring board and its electric characteristics inspection equipment | |
| CN116454067A (en) | Test structure and test method | |
| TW201732309A (en) | Substrate inspection apparatus and substrate inspection method | |
| CN113391181A (en) | Equipment, wafer structure and method for detecting state of wafer test probe card | |
| JPS6348185B2 (en) | ||
| CN112367050A (en) | Electrical performance testing method suitable for large-size solar cell | |
| CN116540048B (en) | Semiconductor test method and test structure | |
| CN116666359A (en) | Test structure and test method | |
| CN108169664A (en) | Board failure detection method and device, computer equipment and storage medium | |
| CN116666360A (en) | Test structure and test method | |
| JP5463198B2 (en) | Probe card inspection method and inspection system | |
| US7233152B2 (en) | Short detection circuit and short detection method | |
| TW200913819A (en) | Method for testing printed circuit board |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |