CN113224035B - Semiconductor test structure and test method - Google Patents
Semiconductor test structure and test method Download PDFInfo
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- CN113224035B CN113224035B CN202110103680.XA CN202110103680A CN113224035B CN 113224035 B CN113224035 B CN 113224035B CN 202110103680 A CN202110103680 A CN 202110103680A CN 113224035 B CN113224035 B CN 113224035B
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- 238000012360 testing method Methods 0.000 title claims abstract description 117
- 239000004065 semiconductor Substances 0.000 title claims abstract description 71
- 238000010998 test method Methods 0.000 title claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 142
- 239000002184 metal Substances 0.000 claims abstract description 142
- 150000002739 metals Chemical class 0.000 claims abstract description 34
- 239000000463 material Substances 0.000 claims description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 9
- 239000010949 copper Substances 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 3
- 238000010884 ion-beam technique Methods 0.000 claims description 3
- 239000011159 matrix material Substances 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 230000007797 corrosion Effects 0.000 abstract description 3
- 238000005260 corrosion Methods 0.000 abstract description 3
- 239000000523 sample Substances 0.000 description 7
- 238000005259 measurement Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 238000010894 electron beam technology Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
- G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
Abstract
The invention provides a semiconductor test structure and a semiconductor test method. The semiconductor test structure includes: the first metal layer comprises a plurality of first metals which are distributed at intervals; the second metal layer comprises a plurality of second metals which are arranged at intervals and are arranged above the first metal in a staggered manner, the first metal and the second metal are connected end to end through metal through holes and are electrically connected with each other to form a plurality of chain-shaped structures which are parallel to each other and connected end to end; and the electric contacts are correspondingly arranged above the second metal. According to the semiconductor test structure and the test method, the electric contact piece is arranged above the second metal layer, so that the sectional test of the resistance value of the semiconductor test structure is realized, the corrosion of the second metal caused by contact air or other reasons due to direct resistance value test through the second metal is avoided, the stability and the service life of the semiconductor test structure are further improved, and the test error is reduced.
Description
Technical Field
The present invention relates to the field of semiconductor testing technologies, and in particular, to a semiconductor testing structure and a testing method.
Background
Contact resistances (Contact Resistance, RC) exist at the junctions between different levels in the IC circuit, and the contact resistances are required to have low and stable resistance. If the resistance of the contact resistor is higher, a large voltage drop exists at the high resistance, so that the operation condition of the whole circuit is affected. Contact resistance testing is a common test item for wafer reliability testing (Wafer Acceptance Test, WAT). Because the resistance value of the single contact resistor is smaller, the direct measurement error is larger, and therefore, a repeated Chain-shaped structure (Chain) which is convenient to test is formed by taking the single contact resistor as a unit in the WAT test. Referring to fig. 1 and 2, a common chain structure measures the current passing through the chain structure by applying a voltage VH to the a end and grounding the B end, so as to calculate the resistance of the whole chain structure, and then obtains the size of a single contact resistance according to the number of the contact resistances in the chain structure, so as to determine whether the contact resistance is higher.
If the problem of high contact resistance occurs, a failure analysis means is required to find out the high resistance point and deduce the root cause of the high contact resistance. The positioning of the high point of the resistor is a very critical step. The existing problem of high contact resistance includes open-circuit high-resistance Failure and non-open-circuit high-resistance Failure, and Failure Analysis technology (FA) can only locate the Failure point (i.e. the area indicated by the circle in fig. 3 and 4) where the open-circuit Failure occurs in the contact resistance by means of passive voltage contrast (Passive Voltage Contrast, PVC), active voltage contrast (Active Voltage Contrast, AVC) or electron beam absorption current (Electron Beam Absorbed Current, EBAC), but the above method cannot effectively locate the contact resistance where the non-open-circuit high-resistance occurs only.
In the prior art, the point-by-point measurement of the nano probe equipment can be utilized to determine the failure point of the non-broken high-resistance failure. However, since the nano probe needs to perform surface treatment on the test sample during measurement, the conductive layer with metallic copper as the main material in the test structure is exposed, so that copper diffusion phenomenon (see fig. 5) easily occurs during measurement, which brings great difficulty to the test.
Disclosure of Invention
The invention aims to provide a semiconductor test structure and a semiconductor test method, which are used for improving the stability and the service life of a chain-shaped test structure and reducing the error of a test result.
In order to achieve the above object, the present invention provides a semiconductor test structure, comprising:
the first metal layer comprises a plurality of first metals which are distributed at intervals;
the second metal layer comprises a plurality of second metals which are arranged at intervals, the second metals are arranged above the first metals in a staggered mode, the first metals and the second metals are connected end to end through metal through holes and are electrically connected with each other to form a plurality of chain-shaped structures which are parallel to each other and connected end to end;
and the electric contacts are correspondingly arranged above the second metal.
Optionally, the semiconductor device further comprises a first dielectric layer, wherein the first dielectric layer is located between the first metal layer and the second metal layer, and the metal through hole penetrates through the first dielectric layer to connect the first metal and the second metal.
Optionally, a second dielectric layer is disposed on the second metal layer, and the electrical contact penetrates through the second dielectric layer and exposes at least a portion of the upper surface.
Optionally, the first metals are distributed in a matrix.
Optionally, one end of the second metal layer is connected with the first pad, and the other end is connected with the second pad.
Optionally, the materials of the first metal, the second metal and the metal through hole all comprise metal copper or copper alloy, and the material of the electric contact comprises metal copper or metal tungsten.
Optionally, the materials of the first dielectric layer and the second dielectric layer include silicon oxide and silicon oxynitride.
Correspondingly, the invention also provides a semiconductor test method, which adopts the semiconductor test structure to perform high-resistance failure positioning, and comprises the following steps:
respectively testing the resistance value of each chain structure, and setting the chain structure with the highest resistance value as a target structure;
testing the resistance between any two adjacent electric contacts in the target structure in a sectional manner to determine a high-resistance node in the target structure; and
and slicing the chain-shaped test structure at the position of the high-resistance node to determine a high-resistance failure mechanism through TEM.
Optionally, before testing the resistance of each chain structure, the resistance of the semiconductor test structure is tested to determine that the semiconductor test structure is a non-broken structure.
Optionally, a focused ion beam is used to prepare the TEM section.
Optionally, the resistance test is performed using a nanoprobe apparatus.
In summary, the present invention provides a semiconductor test structure and a test method. Wherein, the semiconductor test structure includes: the first metal layer comprises a plurality of first metals which are distributed at intervals; the second metal layer comprises a plurality of second metals which are arranged at intervals, the second metals are arranged above the first metals in a staggered mode, the first metals and the second metals are connected end to end through metal through holes and are electrically connected with each other to form a plurality of chain-shaped structures which are parallel to each other and connected end to end; and the electric contacts are correspondingly arranged above the second metal. According to the invention, the electric contact piece is arranged above the second metal layer, so that the sectional test of the resistance value of the semiconductor test structure is realized, the corrosion of the second metal caused by contact air or other reasons due to direct resistance value test through the second metal is avoided, the stability and the service life of the semiconductor test structure are further improved, and the test error is reduced.
Drawings
FIG. 1 is a top view of a semiconductor test structure;
FIG. 2 is a cross-sectional view of the chain test structure shown in FIG. 1 along the direction PP';
FIG. 3 is a schematic diagram of a circuit breaking failure for VC positioning;
FIG. 4 is a schematic diagram of an EBAC localized open circuit failure;
FIG. 5 is a schematic diagram showing copper diffusion phenomenon on the surface of a test sample;
FIG. 6 is a top view of a semiconductor test structure according to one embodiment of the present invention;
FIG. 7 is a cross-sectional view of the semiconductor test structure shown in FIG. 6 along the QQ' direction;
FIG. 8 is a flow chart of a semiconductor testing method according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of a semiconductor test structure in the semiconductor test method according to the embodiment;
FIG. 10 is a TEM section of the semiconductor test method according to the embodiment at the position of the high-resistance node;
FIG. 11 is a TEM section of a normal node in the semiconductor test method according to the embodiment;
wherein, the reference numerals are as follows:
100-a first metal layer; 200-a first dielectric layer; 300-a second metal layer; 400-a second dielectric layer;
1-a first metal; 2-metal vias; 3-a second metal; 4-electrical contacts.
Detailed Description
Specific embodiments of the present invention will be described in more detail below with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
The invention provides a semiconductor test structure and a semiconductor test method. Fig. 6 is a top view of a semiconductor test structure according to the present embodiment, and fig. 7 is a cross-sectional view of the semiconductor test structure shown in fig. 6 along the QQ' direction. Referring to fig. 6 and 7, the semiconductor test structure includes a first metal layer 100 and a second metal layer 300, wherein the first metal layer 100 includes a plurality of first metals 1 arranged at intervals; the second metal layer 300 includes a plurality of second metals 3 arranged at intervals, the second metals 3 are arranged above the first metal 1 in a staggered manner, the first metal 1 and the second metal 3 are connected end to end through metal through holes 2 and are electrically connected with each other, so as to form a plurality of chain structures which are parallel to each other and connected end to end; the semiconductor test structure further comprises a plurality of electric contacts 4 correspondingly arranged above the second metal 3.
Referring to fig. 6 and 7, an insulating material (not labeled in the drawings) is disposed between the first metals 1 and between the second metals 3 in the second metal layer 300 in the first metal layer 100 for isolation, such as silicon oxide, silicon dioxide, or silicon oxynitride. The semiconductor test structure further comprises a first dielectric layer 200 and a second dielectric layer 400, wherein the first dielectric layer 200 is positioned between the first metal layer 100 and the second metal layer 300, and the metal through hole 2 penetrates through the first dielectric layer 200 to connect the first metal 1 and the second metal 3; the second dielectric layer 400 is located on the second metal layer 300, and the electrical contact 4 penetrates through the second dielectric layer 400 and exposes at least a portion of the upper surface, so that the semiconductor test structure can be tested by using the nano-probe. Meanwhile, the first metal 1 and the second metal 3 in the semiconductor test structure are not exposed in the air, so that metal diffusion phenomenon of a metal layer is effectively prevented, the semiconductor test structure is prevented from being corroded or polluted in the test process, and the accuracy of a resistance test result is further ensured.
In this embodiment, the first metal 1 is distributed in a matrix of 5×5, and in other embodiments of the present invention, the distribution manner of the first metal 1 may be adjusted according to actual needs, which is not limited in the present invention. Optionally, one end of the second metal layer 300 is connected to a first pad (not shown in the figure), and the other end is connected to a second pad (not shown in the figure), where the first pad and the second pad serve as connection points of a test resistor of the probe device so as to test the overall resistance of the semiconductor test structure, and detect whether the semiconductor structure has an unbroken high-resistance failure.
In this embodiment, the materials of the first metal 1, the second metal 3 and the metal through hole 2 all include metal copper or copper alloy, and the material of the electrical contact 4 includes metal copper or metal tungsten. The materials of the first dielectric layer 200 and the second dielectric layer 400 include silicon oxide and silicon oxynitride. In other embodiments of the present invention, the materials of the first metal 1, the second metal 3, the metal via 2, the electrical contact 4, the first dielectric layer 200, and the second dielectric layer 400 may be selected according to the actual situation, which is not limited by the present invention. It should be noted that, since the first metal layer 100 and the second metal layer 300 are both metal layers, the Chain structure in this embodiment is mx+1-via-Mx Chain structure, that is, a Chain structure of metal layer-via-metal layer, it can be understood that the present embodiment is based on the Chain structure of the existing metal layer-via-metal layer, and the electrical contact 4 is disposed on the metal layer (second metal layer) located on the top layer, so that the electrical contact 4 realizes the segment test of the semiconductor test structure. Correspondingly, the design of the electric contact is carried out on the metal layer of the top layer, and the method can also be applied to other Chain structures such as M1-CT-AA Chain, M1-CT-Poly Chain, M0-CT-AA Chain, M0-CT-Poly Chain and the like, and the details are not repeated here.
Correspondingly, the embodiment also provides a semiconductor test method, and the semiconductor test structure is adopted for high-resistance failure positioning. Referring to fig. 8, the semiconductor test method includes:
step S01: respectively testing the resistance value of each chain structure, and setting the chain structure with the highest resistance value as a target structure;
step S02: testing the resistance between any two adjacent electric contacts in the target structure in a sectional manner to determine a high-resistance node in the target structure; and
step S03: and slicing the chain-shaped test structure at the position of the high-resistance node to determine a high-resistance failure mechanism through TEM.
The semiconductor testing method according to the present embodiment is described in detail below with reference to fig. 6 and 9 to 11.
First, referring to fig. 6 and 9, step S01 is performed to test the resistance of each chain structure, and set the chain structure with the highest resistance as the target structure. In this embodiment, the semiconductor test structure includes five parallel interconnected chain-like test structures Y1-Y5. Referring to fig. 9, the portion from the electrical contact D1 to the electrical contact D2 is a first segment of chain structure Y1, the portion from the electrical contact D2 to the electrical contact D3 is a second segment of chain structure Y2, and the chain structures Y3, Y4 and Y5 are the same, which is not described in detail herein. The present embodiment uses a nanoprobe apparatus for resistance measurement. Specifically, the process of testing the resistance value of the chain test structure Y1 includes: connecting the nanoprobe of the nanoprobe device with the electric contact pieces D1 and D2 at two ends of the chain-shaped test structure Y1, applying a voltage on the electric contact piece D1 at one end, grounding the electric contact piece D2 at the other end, measuring the current in the chain-shaped test structure Y1, and calculating the resistance value of the chain-shaped test structure Y1 (the resistance value test process of the chain-shaped structures Y2-Y4 is the same, and the invention is not repeated). Comparing the resistance values of the chain-like structures Y1-Y5, and setting the chain-like test structure with the highest resistance value as a target structure (for example, the chain-like test structure with the highest resistance value is Y1 in the embodiment). Alternatively, the chain test structure with the highest resistance value can be found by drawing the relation curves of the current and the voltage in all the chain test structures.
Next, step S02 is executed to test the resistance between any two adjacent electrical contacts in the target structure in a segmented manner, so as to determine a high-resistance node in the target structure. Specifically, the target structure comprises six electric contacts, the resistance between every two adjacent electric contacts is tested by using the nano probe, and the high-resistance node is positioned between two adjacent electric contacts with the highest resistance.
Subsequently, step S03 is performed to slice the chain-like test structure at the high-resistance node position to determine the mechanism causing high-resistance failure by TEM. Specifically, TEM slicing is performed on the semiconductor structure along a direction perpendicular to the second dielectric layer 400, so as to expose a cross section of the chain-like test structure; and analyzing the reasons for high-resistance failure through the section of the chain-shaped test structure. Optionally, a focused ion beam machine (FIB machine) is used to prepare TEM sections of the chain test structures.
Optionally, since the high-resistance failure is divided into open-circuit failure and non-open-circuit high-resistance failure, before executing step S01, the resistance value of the semiconductor test structure needs to be tested to determine that the semiconductor test structure is a non-open-circuit structure, so as to eliminate the possibility of open-circuit failure of the semiconductor test structure and avoid erroneous judgment.
Fig. 10 is a TEM sectional view of a high resistance node in the semiconductor test method according to the present embodiment, and fig. 11 is a TEM sectional view of a normal node in the semiconductor test method according to the present embodiment. As can be seen from comparing fig. 10 and fig. 11, an abnormality occurs at the bottom of the metal via hole at the position of the high-resistance node, and there may be an interface reaction that causes the resistance to rise. In addition, when the semiconductor test structure in fig. 10 and 11 is M0-CT-AA Chain, the bottom of the metal via is connected to an Active Area (AA), and a heavily doped region with a certain thickness is present in the active area, and referring to fig. 11, the metal via is etched into the heavily doped region in the active area in a normal node, it can be presumed that the metal via and the active area are in ohmic contact at this time; referring to fig. 10, the metal via hole at the high-resistance node is etched deeper into the active region than the heavily doped region, so that it is presumed that schottky contact occurs between the metal via hole and the active region at this time, thereby causing the resistance at the high-resistance node to be higher than that of the normal node.
In summary, the present invention provides a semiconductor test structure and a test method. Wherein, the semiconductor test structure includes: the first metal layer comprises a plurality of first metals which are distributed at intervals; the second metal layer comprises a plurality of second metals which are arranged at intervals, the second metals are arranged above the first metals in a staggered mode, the first metals and the second metals are connected end to end through metal through holes and are electrically connected with each other to form a plurality of chain-shaped structures which are parallel to each other and connected end to end; and the electric contacts are correspondingly arranged above the second metal. According to the invention, the electric contact piece is arranged above the second metal layer, so that the sectional test of the resistance value of the semiconductor test structure is realized, the corrosion of the second metal caused by contact air or other reasons due to direct resistance value test through the second metal is avoided, the stability and the service life of the semiconductor test structure are further improved, and the test error is reduced.
The foregoing is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any person skilled in the art will make any equivalent substitution or modification to the technical solution and technical content disclosed in the invention without departing from the scope of the technical solution of the invention, and the technical solution of the invention is not departing from the scope of the invention.
Claims (10)
1. A method of testing a semiconductor test structure, comprising:
providing a test structure, wherein the test structure comprises a first metal layer, a plurality of first metals and a plurality of second metal layers, the first metals are arranged at intervals, the second metals are arranged above the first metals at intervals in a staggered manner, the first metals and the second metals are connected end to end through metal through holes and are electrically connected with each other to form a plurality of parallel interconnected chain structures which are connected end to end, and a plurality of electric contacts are correspondingly arranged above the second metals;
testing the resistance of the semiconductor test structure to determine that the semiconductor test structure is a non-circuit breaking structure;
respectively testing the resistance value of each chain structure, and setting the chain structure with the highest resistance value as a target structure;
testing the resistance between any two adjacent electric contacts in the target structure in a sectional manner to determine a high-resistance node in the target structure; and
and slicing the chain-shaped test structure at the position of the high-resistance node to determine a high-resistance failure mechanism through TEM.
2. A method of testing a semiconductor test structure as recited in claim 1, wherein the TEM section is prepared using a focused ion beam.
3. The method of testing a semiconductor test structure of claim 1, wherein the resistive test is performed using a nanoprobe apparatus.
4. The semiconductor test structure of claim 1, further comprising a first dielectric layer between the first metal layer and the second metal layer, the metal via connecting the first metal and the second metal through the first dielectric layer.
5. The semiconductor test structure of claim 1, further comprising a second dielectric layer on the second metal layer, the electrical contact extending through the second dielectric layer and exposing at least a portion of an upper surface.
6. The semiconductor test structure of claim 1, wherein the first metals are distributed in a matrix.
7. The semiconductor test structure of claim 1, wherein one end of the second metal layer is connected to the first pad and the other end is connected to the second pad.
8. The semiconductor test structure of claim 1, wherein the material of the first metal, the second metal, and the metal via each comprises metallic copper or a copper alloy, and the material of the electrical contact comprises metallic copper or metallic tungsten.
9. The semiconductor test structure of claim 4, wherein the material of the first dielectric layer comprises silicon oxide and silicon oxynitride.
10. The semiconductor test structure of claim 5, wherein the material of the second dielectric layer comprises silicon oxide and silicon oxynitride.
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| US11876024B2 (en) | 2021-10-08 | 2024-01-16 | Nanya Technology Corporation | Method for operating a benchmark device on a semiconductor wafer with fuse element |
| TWI799041B (en) * | 2021-10-08 | 2023-04-11 | 南亞科技股份有限公司 | Benchmark device on a semiconductor wafer with fuse element and method for operating the same |
| CN116153797A (en) * | 2021-11-19 | 2023-05-23 | 上海华力微电子有限公司 | Method for positioning breaking failure point of test structure |
| CN115881696A (en) * | 2023-01-31 | 2023-03-31 | 广州粤芯半导体技术有限公司 | Test structure and test method for detecting metal bottom internal cutting defects |
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| CN201017877Y (en) * | 2007-03-06 | 2008-02-06 | 中芯国际集成电路制造(上海)有限公司 | Staged thru hole chain structure easy to test reliability |
| CN102446901A (en) * | 2010-10-14 | 2012-05-09 | 中芯国际集成电路制造(上海)有限公司 | Failure analysis structure, formation method of failure analysis structure and failure analysis method |
| TW201301418A (en) * | 2011-06-16 | 2013-01-01 | 矽品精密工業股份有限公司 | Process monitor circuit element for monitoring manufacturing process |
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