CN111276416B - Method for detecting alignment of semiconductor structure alignment and method for manufacturing 3D memory device - Google Patents
Method for detecting alignment of semiconductor structure alignment and method for manufacturing 3D memory device Download PDFInfo
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- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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Abstract
The invention provides a method for detecting alignment of semiconductor structure overlay and a method for manufacturing a 3D memory device. The through structure may be a channel hole, a through hole, a gate line slit, or the like. According to the method, the first filling layer and the first opening are directly detected through imaging, so that the detection is more visual, and the detection result is more accurate. The method is particularly suitable for the stacking structure of the non-transparent film layer, is easy to operate and has wide application range.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a method for detecting alignment of semiconductor structure alignment and a method for manufacturing a 3D memory device.
Background
As the feature size of devices in integrated circuits continues to shrink, 3D memory technologies that stack multiple planes of memory cells to achieve greater storage capacity and achieve lower cost per bit are becoming more and more popular. Forming a vertical trench hole in a stacked structure becomes a critical step in fabricating a 3D memory.
As the number of stacked layers of a stacked structure increases, for example, a stacked structure with 192 layers or more, a step-by-step method of forming a lower channel hole and then forming an upper channel hole is generally required to form a complete channel hole. Such a method generally requires monitoring of the fill layers of the upper and lower channel holes in order to ensure alignment of the upper and lower channel holes, as well as dimensional uniformity. In the prior art, the filling layer is usually monitored in a line drawing area on a mask plate of the filling layer. However, this method is not accurate enough or can not be monitored at all for stacked structures with a large number of stacked layers or opaque film layers.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for inspecting alignment of semiconductor structures and a method for manufacturing a 3D memory device, the method for inspecting alignment of semiconductor structures includes forming a first through structure in a first semiconductor structure on a substrate and a first filling layer in the first through structure, then forming a second semiconductor structure above the first semiconductor structure and a second through structure in the second semiconductor structure, the second through structure forming a first opening on top of the first filling layer, then removing the second semiconductor structure and imaging the top of the structure exposing the first filling layer and the first opening, obtaining offset information of the first through structure and the second through structure, and adjusting or compensating parameters of subsequent etching according to the offset information. The through structure may be a channel hole, a through hole, a gate line slit, or the like. According to the method, the first through structure and the second through structure are directly detected through imaging, so that the detection is more visual, and the detection result is more accurate. And adjusting the parameters of the next through structure etching process according to the offset information to obtain the through structure with consistent line width and no offset.
To achieve the above and other related objects, the present invention provides a method for detecting alignment of semiconductor structures, comprising:
providing a substrate, and forming a first semiconductor structure on the substrate;
etching the first semiconductor structure to form a first through structure;
filling a first filling layer in the first through structure;
forming a second semiconductor structure over the first semiconductor structure and the first fill layer;
etching the second semiconductor structure to form a second through structure above the first through structure, wherein the second through structure forms a first opening at the top of the first filling layer;
removing the second semiconductor structure to expose the first filling layer;
imaging the structure with the second semiconductor structure removed to obtain offset information of the first through structure and the second through structure;
and adjusting etching parameters according to the offset information.
Optionally, imaging the structure after removing the second semiconductor structure to obtain information of the first through structure and the second through structure, further comprising:
and scanning and imaging the top of the structure after the second semiconductor structure is removed.
Optionally, imaging the structure after removing the second semiconductor structure, and acquiring offset information of the first through structure and the second through structure, further comprising the following steps:
measuring the cross-sectional dimension of the first filling layer to obtain the cross-sectional dimension of the first through structure;
measuring a cross-sectional dimension of the first opening of the first filling layer to obtain a cross-sectional dimension of the second through structure.
Optionally, imaging the structure after removing the second semiconductor structure, and acquiring offset information of the first through structure and the second through structure, further comprising the following steps:
respectively determining the center of the first filling layer as a first center, and the center of the first opening as a second center;
and measuring the distance between the first center and the second center to obtain the offset distance and/or the offset angle of the first through structure and the second through structure.
Optionally, the first semiconductor structure and the second semiconductor structure comprise a stacked structure.
Optionally, the first semiconductor structure comprises a stacked structure and the second semiconductor structure comprises a sacrificial insulating layer.
Optionally, the substrate comprises a test wafer.
Optionally, the first through structure and the second through structure are the same structure, and the first through structure and the second through structure include a channel hole and/or a gate slit.
The invention also provides a 3D memory manufacturing method, which comprises the following steps:
obtaining adjusted etching parameters according to the detection method for the alignment of the semiconductor structure alignment provided by the invention;
providing a substrate for manufacturing the 3D memory device, and forming a lower stack structure on the substrate;
etching the lower stack structure to form a lower channel hole;
and forming an upper stack structure above the lower stack structure, etching the upper stack structure based on the adjusted etching parameters, and forming an upper channel hole corresponding to the lower channel hole, wherein the upper channel hole and the lower channel hole form a channel hole which is communicated with the upper stack structure and the lower stack structure.
Optionally, the etching the lower stack structure to form the lower channel hole includes:
and etching the first semiconductor structure in the detection method for the alignment of the semiconductor structure provided by the invention, wherein the etching parameters are unchanged when the first through structure is formed, etching the lower stack structure, simultaneously partially etching the substrate, and forming a lower channel hole in the substrate and the lower stack structure.
Optionally, the 3D memory manufacturing method further includes the steps of:
forming an epitaxial structure at the bottom of the channel hole;
forming a blocking layer, a charge trapping layer and a tunneling layer in sequence from the side wall of the channel hole to the center;
and forming a channel layer in the center of the channel hole, wherein the channel layer is communicated with the epitaxial structure.
Optionally, the 3D memory manufacturing method further includes the steps of:
etching the upper stack structure and the lower stack structure to form a grid line gap;
etching and removing the sacrificial layers of the upper stack structure and the lower stack structure to form a gate groove;
and filling a metal layer in the grid groove to form a metal grid.
Optionally, the 3D memory manufacturing method further includes the steps of:
forming a dielectric isolation layer on the side wall of the grid line gap;
and filling a conductive material in the gate line gap to form a common source contact.
As described above, the method for detecting alignment of semiconductor structure overlay and the method for manufacturing 3D memory device provided by the present invention have the following advantages:
the method for detecting the alignment of the semiconductor structure overlay comprises the steps of forming a first through structure in a first semiconductor structure on a substrate, forming a first filling layer in the first through structure, forming a second semiconductor structure above the first semiconductor structure, forming a second through structure in the second semiconductor structure, forming a first opening on the top of the first filling layer by the second through structure, removing the second semiconductor structure, scanning and imaging the top of the structure which exposes the first filling layer and the first opening after the second semiconductor structure is removed, and directly measuring information such as the line width of the first filling layer and the first opening, the offset distance and the offset angle of the centers of the first filling layer and the first opening in the scanned image, thereby obtaining the offset information of the first through structure and the second through structure. The through structure may be a channel hole, a through hole, a gate line slit, or the like. According to the method, the first through structure and the second through structure are directly detected through imaging, so that the detection is more visual, and the detection result is more accurate. Especially for a stacked structure in which the film layers are opaque, the method can obtain accurate through structure (such as channel holes, gate line gaps, etc.) data. The line width and the offset information can be used as a reference of a subsequent etching process to adjust or compensate parameters of the subsequent etching process.
The offset information of the through structure is obtained by the semiconductor overlay alignment detection method, and the offset information can be used for reference data of the next through structure etching process to adjust or compensate etching parameters, so that the etched through structures, such as the aperture of a channel hole is consistent, the vertical size of a grid line gap is consistent, offset cannot occur, and the like, thereby improving the quality of the channel hole and the grid line gap and improving the yield of subsequent devices.
The method for detecting the alignment of the semiconductor overlay is suitable for detecting holes or grooves with high aspect ratios such as grid line gaps, contact holes and the like in the stacked structure, and is particularly suitable for the stacked structure comprising the opaque film layer. The method has the advantages of easy operation, wide application range, accurate detection result and the like.
Drawings
Fig. 1 is a flowchart illustrating a method for detecting alignment of a semiconductor structure according to the present invention.
Fig. 2 is a schematic structural diagram of a first stacked structure formed on a substrate in a preferred embodiment of the first embodiment.
Fig. 3 is a schematic view illustrating a structure of forming a first channel hole in the first stacked structure shown in fig. 2.
Fig. 4 is a schematic structural view illustrating a first filling layer filled in the first trench hole shown in fig. 3.
Fig. 5 is a schematic diagram of a structure in which a second stacked structure is formed over the structure shown in fig. 4.
Fig. 6 is a schematic view illustrating a structure of forming a second channel hole in the second stacked structure shown in fig. 5.
Fig. 7 is a schematic structural view illustrating the second stack structure shown in fig. 6 is removed.
Fig. 8 and 9 show electronic scan images at different magnifications for the top of the structure shown in fig. 7, where fig. 8 shows a scan image at 7 ten thousand times and fig. 9 shows a scan image at 15 ten thousand times.
Fig. 10 is a schematic structural view illustrating a first filling layer formed in the first trench hole and the second trench hole according to another preferred embodiment of the present invention.
Fig. 11 is a schematic diagram of a sacrificial insulating layer formed over the structure shown in fig. 10.
Fig. 12 is a schematic view showing a structure of forming a via hole in the sacrificial insulating layer shown in fig. 11.
Fig. 13 is a schematic structural view illustrating the removal of the sacrificial insulating layer shown in fig. 12.
Fig. 14 shows an electronically scanned image of the top of the structure shown in fig. 13.
Fig. 15 is a flowchart illustrating a method for manufacturing a 3D memory device according to a second embodiment of the present invention.
Fig. 16 is a schematic view showing a structure of forming a channel hole in an upper stack structure and a lower stack structure of a substrate.
Fig. 17 is a schematic view illustrating a structure of forming a channel structure in the channel hole shown in fig. 16.
Fig. 18 is a view illustrating a structure of forming a gate trench in the channel hole of fig. 17.
Fig. 19 is a schematic diagram illustrating a structure of a gate trench fill metal layer formed in fig. 18.
Description of the element reference numerals
100 substrate
101 first stack structure
1011 insulating layer of a first stacked structure
1012 sacrificial layer of first stacked structure
102 first trench hole
103 first filling layer
1031 first opening on top of first filling layer
104 second stack structure
1041 insulating layer of second stacked structure
1042 sacrificial layer of second stack structure
105 second trench hole
106 sacrificial insulating layer
107 through hole
108 second opening
200 substrate
201 lower stack structure
202 stacking structure
203 channel hole
2031 lower channel hole
2032 upper channel hole
204 gate trench
205 channel structure
2051 Barrier layer
2052 Charge trapping layer
2053 tunneling layer
2054 channel layer
206 metal layer
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity, position relationship and proportion of the components in actual implementation can be changed freely on the premise of implementing the technical solution of the present invention, and the layout form of the components may be more complicated.
In the prior art, in order to detect the alignment degree of the overlay, the following methods are generally adopted: the line-area overlay mark monitoring method uses an X-ray tool to detect the overlay and a surface imaging (FA image) measurement method. However, these methods have certain limitations or drawbacks. For example, the drawn line area overlay mark monitoring method cannot show the characteristics of the actual hole-to-hole overlay in the central area, cannot obtain the characteristics of the overlay in such a very limited area of an exposure field, and cannot obtain the overlay mark by the inspection tool when the multi-layer stack structure is an opaque structure; when an X-ray tool is adopted to detect the covering layer, a large amount of data is needed to carry out machine calibration, in addition, the reference data detected for the first time is not accurate, and the process is very complicated; FA image measurements have very large sample and data limitations and require very large tools and a lot of manual work.
In view of the above disadvantages and drawbacks of the conventional methods, the present invention provides a method for detecting alignment of a semiconductor structure and a method for fabricating a 3D memory. The present invention will be described in detail with reference to the following examples and the accompanying drawings.
Example one
The present embodiment provides a method for detecting alignment of semiconductor structure overlay, as shown in fig. 1, the method includes the following steps:
step S101: providing a substrate, and forming a first semiconductor structure on the substrate;
step S102: etching the first semiconductor structure to form a first through structure;
step S103: filling a first filling layer in the first through structure;
step S104: forming a second semiconductor structure over the first semiconductor structure and the first fill layer;
step S105: etching the second semiconductor structure to form a second through structure above the first through structure, wherein the second through structure forms a first opening at the top of the first filling layer;
step S106: removing the second semiconductor structure to expose the first filling layer;
step S107: imaging the structure with the second semiconductor structure removed to obtain offset information of the first through structure and the second through structure;
step S108: and adjusting etching parameters according to the offset information.
In this embodiment, the first semiconductor structure and the second semiconductor structure may have the same structure, for example, both may be stacked structures of multiple layers of films, and the first through structure and the second through structure may have the same structure, for example, high aspect ratio structures such as a trench hole, a gate line slit, or a through hole. Or the first semiconductor structure and the second semiconductor structure may be different structures, and the first through structure and the second through structure are also different structures, for example, the first semiconductor structure may be a stacked structure of a plurality of film layers, and the second semiconductor structure may use a sacrificial insulating layer for detecting alignment of the first semiconductor structure, the first through structure being a channel hole formed in the first semiconductor structure, and the second through structure being a via hole formed in the sacrificial insulating layer.
In an embodiment of the present invention, the method for detecting the overlay alignment of the semiconductor structure in this embodiment is described in detail by taking an example that the first semiconductor structure and the second semiconductor structure are both stacked structures and the first through structure and the second through structure are formed as channel holes.
In a preferred embodiment of the present invention, the first and second semiconductor structures are first and second stacked structures, respectively, and the first and second through structures are first and second channel holes formed in the first and second stacked structures, respectively.
First, as shown in fig. 2, a substrate 100 is provided, and the substrate 100 may be a test wafer for semiconductor process testing, such as a silicon wafer, a silicon-on-single-crystal-insulator wafer, or other suitable material.
A first stacked structure 101 is formed on a substrate 100, the first stacked structure 101 comprising an insulating layer 1011 and a sacrificial layer 1012 alternately formed over the substrate 100, the insulating layer 1011 may be silicon oxide and the sacrificial layer 1012 may be silicon nitride, i.e. the stacked structure 101 forms an ONO stacked structure of alternating silicon oxide and silicon nitride, which may comprise 64, 128 or even more layers. More preferably, the surface of the substrate 100 may be formed with an oxide layer 101 (e.g., SiO)2) As an etch stop layer.
Then, as shown in fig. 3, after the first stacked structure is formed, as described in step S102, the first stacked structure 101 is etched, for example, a plasma dry etching may be adopted to etch the first stacked structure 101 to form the first channel hole 102 shown in fig. 3. In the preferred embodiment, the first channel hole 102 is formed in a portion of the substrate at the same time, as shown in fig. 3.
Thereafter, as shown in fig. 4, after the first channel hole 102 is formed, the first filling layer 103 is filled in the first channel hole 102, and in a preferred embodiment of the present embodiment, the first filling layer 103 may be a material such as polysilicon that is not corroded by an acid solution such as HF acid for removing the stacked structure. For example, polysilicon may be deposited on the sidewalls and bottom of the first trench hole, and then the polysilicon above the first stacked structure is removed to planarize the polysilicon and form the first filling layer 103. The first fill layer 103 may support the entire stack structure during subsequent etching.
As shown in fig. 5, after forming the first filling layer 103 in the first channel hole 102, a second stacked structure 104 is formed above the first stacked structure 101, the second stacked structure 104 also includes an insulating layer 1041 and a sacrificial layer 1042 that are alternately arranged, and the insulating layer 1041 and the sacrificial layer 1042 may be the same material or different materials from the insulating layer 1011 and the sacrificial layer 1012 in the first stacked structure 101. In the preferred embodiment, the insulating layer 1041 and the sacrificial layer 1042 are made of the same material as the insulating layer 1011 and the sacrificial layer 1012 in the first stacked structure 101, i.e. the insulating layer 1041 may be silicon oxide, the sacrificial layer 1042 may be silicon nitride, and the second stacked structure 104 also forms an ONO stacked structure with alternating silicon oxide and silicon nitride, and the second stacked structure also may include 64 layers, 128 layers or more.
As shown in fig. 6, after the second stacked structure 104 is formed, the second stacked structure is etched, and in the preferred embodiment, in order to obtain the same structure as the first channel hole, the same etching mask and etching method as those used for forming the first channel hole are used. Therefore, when etching the second stacked structure, the plasma dry etching is also adopted, and the etching parameters are kept the same as those of the stackable structure. The second stack structure 104 is etched until a portion of the first filling layer 103, forming second channel holes 105 corresponding to the upper and lower portions of the first channel holes 102.
As shown in fig. 6, a portion of the first filling layer 103 is etched at the same time when the second stack structure 104 is etched, so that a bottom opening of the second channel hole 105 is formed at the top of the first filling layer 103, and a first opening 1031 is formed at the top of the first filling layer. The first filling layer is etched by adopting the same etching parameters and etching masks while the second stacking structure is etched, so that the bottom opening of the second channel hole is formed by the first opening formed in the first filling layer, and the appearance of the first opening can describe the appearance of the bottom opening of the second channel hole.
As shown in fig. 7, after the second channel hole 105 is formed, the second stacked structure is removed, in the preferred embodiment, in order to prevent damage to the first filling layer when the second stacked structure is removed, an etching method different from a plasma dry etching method for etching the second stacked structure is adopted, for example, in the preferred embodiment, a wet etching method is adopted to remove the second stacked structure. More preferably, the second stacked structure 104 is removed by HF acid etching, and since the first filling layer 103 is formed of a material that is not etched by HF acid, such as polysilicon, the first filling layer 103 is not damaged by etching when the second stacked structure is etched by HF acid, and good morphology can be maintained.
In order to obtain the offset information of the first channel hole and the second channel hole, the structure after the second stacked structure is removed is imaged, specifically, the top of the structure is subjected to electronic scanning imaging, and an image of the top is obtained. The image obtained after electronically scanning the structure shown in fig. 7 is shown in fig. 8, and in the scanned image of 7 ten thousand magnifications shown in fig. 8, the first filling layer 103 and the first opening 1031 therein can be clearly observed, and at this magnification, the outer diameter d of the first filling layer 103 can be completely obtained1And diameter d of first opening 10312. In the formation of the first filling-up layer 103, the polysilicon above the first stacked structure is removed and the polysilicon is processedPlanarized so that the first filling-up layer is formed only in the first channel hole, and thus, the outer diameter d of the first filling-up layer 1031Equivalent to the aperture of at least the upper opening of the first channel hole 102, and thus can be used to characterize the aperture information of the first channel hole 102.
Similarly, when forming the second channel hole 105 as described above, the second stacked structure and the first filling layer are etched using the same etching parameters and etching mask, so that the first opening formed in the first filling layer forms the bottom opening of the second channel hole, and thus the diameter d of the first opening 10312Equivalent to the bottom aperture of the second trench 105.
In addition, since the same etching method and etching mask are also used in the etching process of the first stacked structure and the second stacked structure, the first channel hole and the second channel hole formed have the same structure, and theoretically, the first channel hole and the second channel hole are completely identical and completely aligned up and down, but due to environmental or human factors, the alignment of the first channel hole and the second channel hole is deviated. Based on the above discussion, it can be seen from FIG. 7 that the outer diameter d of the first filling-up layer 1031Can be used to characterize the aperture of the upper openings of the first channel hole 102 and the second channel hole 105, the diameter d of the first opening 10312May be used to characterize the pore diameter of the bottom opening of the second channel hole 105 or the first channel hole 102. Comparison d in the electronically scanned image shown in FIG. 81And d2The difference in the upper and lower pore diameters of the first channel hole and the second channel hole can be obtained, and thus the pore diameters of the first channel hole and the second channel hole can be evaluated.
To obtain more information, the top of the structure shown in fig. 7 can be imaged by electronic scanning at a higher magnification, as shown in fig. 9, at 15 ten thousand times, whereby the center of the first filling layer 103 can be accurately determined: first center O1And center of the first opening 1031 therein: second center O2. See also above regarding the outer diameter d of the first filler layer 1031And diameter d of first opening 10312The first center O1And a second center O2The first channel hole 102 and the second channel hole 1 may be represented, respectively05 in the center. The first center O can be further obtained in the electronic scanned image shown in fig. 91And a second center O2A distance d between3The distance may represent an offset distance d of the second channel hole with respect to the first channel hole3。
In addition, the first center O can also be obtained from the scanned image shown in fig. 91And a second center O2With respect to the horizontal direction, from which the offset direction of the second channel hole 105 with respect to the first channel hole 102 can be determined.
The offset distance and the offset direction of the second channel hole 105 relative to the first channel hole 102 are used as references to adjust or compensate the relevant parameters of the etching process, so as to ensure the alignment of the upper and lower structures in the subsequent etching process. For example, the offset may be compensated by adjusting parameters such as gas flow, flow rate, and/or etching time of the dry etching process.
In another preferred embodiment of the present embodiment, the first semiconductor structure and the second semiconductor structure are different structures, and the first through structure and the second through structure are also different structures, for example, the first semiconductor structure may be a stacked structure of multiple film layers, and the second semiconductor structure may use a sacrificial insulating layer for detecting alignment of the first semiconductor structure, the first through structure is a channel hole formed in the first semiconductor structure, and the second through structure is a via hole formed in the sacrificial insulating layer.
In the present preferred embodiment, as shown in fig. 10, the first semiconductor structure includes a first stacked structure 101 and a second stacked structure 104 formed by stacking, and a first channel hole 102 and a second channel hole 105 are formed in the first stacked structure and the second stacked structure, whereby channel holes penetrating the first and second stacked structures are formed, and a first filling layer 103 is formed in each of the first and second channel holes. The processes of forming the first trench hole and the second trench hole and filling the first filling layer in the preferred embodiment are all described with reference to the method of the preferred embodiment shown in fig. 2 to 6, and will not be described in detail herein.
Then, as shown in FIG. 11, a channel structure is formedA sacrificial insulating layer 106, which may be SiO, is formed over the stacked structure of (a)2And the like. Then, as shown in fig. 12, the sacrificial insulating layer 206 is etched by using the same mask and the same etching method and etching parameters as those used in forming the trench hole, a via hole 107 corresponding to the trench hole is formed in the sacrificial insulating layer 206, and a bottom opening of the via hole 107 is formed in the first filling layer 103. As shown in fig. 13, the via 107 in this embodiment is formed by forming a second opening 108 in the first filling layer. Sacrificial insulating layer 106 is then removed and the top of the structure shown in fig. 13 is electronically scanned for imaging.
Similarly, in order to prevent damage to the first filling layer when the second stacked structure is removed, an etching method different from the plasma dry etching method for etching the second stacked structure is adopted, for example, in the preferred embodiment, the second stacked structure is removed by wet etching. More preferably, the second stacked structure 104 is removed by HF acid etching, and since the first filling layer 103 is formed of a material that is not etched by HF acid, such as polysilicon, the first filling layer 103 is not damaged by etching when the second stacked structure is etched by HF acid, and good morphology can be maintained.
The result of the electronic scanning imaging is shown in fig. 14, and from this fig. 14, the outer diameter d of the first filling layer 103 can be obtained1' and the diameter d of the second opening 108 in the first fill layer 1032'. As described in the above preferred embodiment, in the preferred embodiment, when the first semiconductor structure formed by the first stacked structure and the second semiconductor structure used as the sacrificial insulating layer are etched to form the first trench hole, the second trench hole, and the through hole, the same etching mask, the same etching method, and the same etching parameters are used, so that theoretically, the three are completely identical and completely aligned up and down, but due to environmental or human factors, the alignment of the three is deviated. Based on this, as can be seen from fig. 13, the outer diameter d of the first filling-up layer 1031' can be used to characterize the aperture of the upper openings of the first channel hole 102 and the second channel hole 105, the diameter d of the first opening 10312' can be used to characterize the first trenchThe aperture of the bottom opening of the channel hole 102 and the second channel hole 105. Comparison d in the electronically scanned image shown in FIG. 141' and d2' the difference between the upper and lower pore diameters of the first channel hole and the second channel hole is obtained, whereby the pore diameters of the first channel hole and the second channel hole can be evaluated.
The center O of the channel hole can also be determined in fig. 141' and center O of bottom opening of via 2072', whereby O is obtained1' and O2' distance d between3', the offset distance d of the via hole 207 with respect to the channel hole can be obtained3' which can be used to estimate the offset distance of the upper channel hole relative to the lower channel hole. In addition, O can also be obtained from the scanned image shown in fig. 141' and O2'angle α' with respect to the horizontal direction, whereby the offset direction of the through-hole 207 with respect to the channel hole can be determined. Likewise, since the via 207 and the first and second channel holes are formed by the same mask, the same etching method, and the same etching parameters, the offset distance and offset direction of the via 207 with respect to the channel hole can be used to evaluate the offset distance and offset direction of the second channel hole with respect to the first channel hole.
According to the method, the first through structure and the second through structure are directly detected through scanning imaging, so that the detection is more visual, and the detection result is more accurate. Especially for a stacked structure in which the film layers are opaque, the method can obtain accurate through structure (such as channel holes, gate line gaps, etc.) data.
Example two
The present embodiment provides a 3D memory device manufacturing method, as shown in fig. 15, including the steps of:
step S201: obtaining adjusted etching parameters according to the method for detecting the alignment of the semiconductor structure in the embodiment of the invention;
according to the method of the first embodiment, for example, information of the aperture of the first channel hole and the aperture of the second channel hole, and information of the offset distance and the offset direction of the second channel hole with respect to the first channel hole are obtained, and then parameters of the etching machine to be adjusted, such as related parameters of etching time, flow rate of etching gas, flow velocity, etching temperature, and the like, are obtained according to the information, so that adjusted etching parameters capable of compensating for the offset and the like of the second channel hole with respect to the first channel hole are obtained.
Step S202: providing a substrate for manufacturing the 3D memory device, and forming a lower stack structure on the substrate;
referring to fig. 16, a substrate 200 for fabricating the 3D memory device is provided, and the substrate 200 may be, for example, silicon, a single crystal silicon-on-insulator, or other suitable substrate.
A lower stack structure 201 is formed on the substrate 200, the lower stack structure 201 includes an insulating layer 2011 and a sacrificial layer 2012 alternately formed above the substrate 200, the insulating layer 2011 may be silicon oxide, and the sacrificial layer 2012 may be silicon nitride, i.e., the lower stack structure 201 forms an ONO stack structure in which silicon oxide and silicon nitride are alternately arranged, and the lower stack structure 201 may include 64 layers, 128 layers, or even more. After the lower stack structure 201 is formed, it is etched, and before the etching, the following step S209 is first performed.
Step S203: etching the lower stack structure to form a lower channel hole;
referring to fig. 16, after the lower stack structure 201 is formed, the first semiconductor structure is etched in the method for detecting alignment of semiconductor structures according to the first embodiment of the present invention, and the etching parameters are not changed when the first through structure is formed, and the lower stack structure is etched until a portion of the substrate 200 is formed, so as to form the lower channel hole 2031.
Step S204: and forming an upper stack structure above the lower stack structure, etching the upper stack structure based on the adjusted etching parameters to form an upper channel hole corresponding to the lower channel hole, and forming a channel hole which is communicated with the upper stack structure and the lower stack structure by the upper channel hole and the lower channel hole.
After the lower channel hole 2031 is formed, a filling layer may also be formed in the lower channel hole 2031 to support the stack structure and prevent contamination of the lower channel hole 2031 when the upper stack structure is formed. An upper stack structure 202 is then formed over the lower stack structure, the upper stack structure 202 also including an insulating layer 2021 and a sacrificial layer 2022 alternately formed over the lower stack structure 201, similarly, the insulating layer 2021 may be silicon oxide, the sacrificial layer 2022 may be silicon nitride, an ONO stack structure in which silicon oxide and silicon nitride are alternately arranged is formed, and the upper stack structure 202 also may include 64 layers, 128 layers, or even more.
Then, the upper stack structure 202 is etched by using the same mask and the same etching method as those used for forming the lower channel hole, based on the adjusted etching parameters, until the upper stack structure 202 is penetrated, so as to form an upper channel hole 2032. The filling material filled in the lower trench hole 2031 is removed, and the upper trench hole 2032 and the lower trench hole 2031 are opened, thereby forming a trench hole 203 penetrating the upper stack structure 202 and the lower stack structure 201 as shown in fig. 16.
In a preferred embodiment of the present embodiment, after the channel hole 203 is formed, a step of forming a channel structure in the channel hole is further included.
As shown in fig. 17, first, selective epitaxial growth is performed at the bottom of the channel hole 203, i.e., at the opening of the lower channel hole 2031 formed on the substrate 200, to form an epitaxial structure, and then a blocking layer 2051, a charge trapping layer 2052, and a tunneling layer 2053 are sequentially formed in the channel hole from the sidewall toward the center. The material of the barrier layer may be a high K dielectric. The high-K dielectric material has a thinner Equivalent Oxide Thickness (EOT) which effectively reduces gate leakage while maintaining transistor performance. The high-K dielectric may be, for example, alumina, zirconia, or the like. The barrier layer may be a single layer of dielectric oxide or a bilayer model, such as high K oxide and silicon oxide. The charge trapping layer 2052 may be a floating gate structure, including, for example, a polysilicon material. The tunneling layer 2053 is an insulating layer, which may be, for example, a nitride insulating layer. The blocking layer, the charge trapping layer and the tunneling layer constitute a memory layer.
In forming the memory layer, the barrier layer, the charge trapping layer and the tunneling layer are also deposited simultaneously at the bottom of the channel hole, and in order to form a channel layer in communication with the epitaxial layer, the barrier layer, the charge trapping layer and the tunneling layer 1103 at the bottom of the channel hole are first etched to expose the epitaxial structure, and then, as shown in fig. 17, a channel layer 2054, which may be single crystal silicon, polycrystalline silicon, SiGe, SiC, SiGe, etc., is deposited in the vertical channel hole. The blocking layer 2051, the charge trapping layer 2052, the tunneling layer 2053, and the channel layer 2054 form a complete channel structure 205. As is well known, the central region of the channel hole may also be filled with an isolation dielectric layer or an air gap may be left as described in fig. 17, which will not be described in detail herein.
As is well known, the present embodiment may further include the step of forming a gate structure and a common source contact in the upper stack structure and the lower stack structure.
For example, the upper stack structure and the lower stack structure are first etched to form a gate line gap (not shown), and then, as shown in fig. 18, the sacrificial layers 1022 and 2022 of the upper stack structure and the lower stack structure are etched to form the gate trench 204. In a preferred embodiment, the sacrificial layer is removed by acid etching, for example, through the resulting grid line gaps. Then, as shown in fig. 19, a metal layer 206 is filled in the gate trench 204 to form a metal gate, for example, the metal layer 206 may be tungsten or the like.
A dielectric isolation layer (not shown) is formed on the side wall of the gate line gap to isolate the metal gate, and then a conductive material, such as polysilicon, is filled in the gate line trench to form a common source contact.
When the 3D memory is formed in this embodiment, the test wafer is used to adjust or compensate the etching parameters, and then the stack forming the 3D memory is etched to ensure that the upper channel hole and the lower channel hole have the same aperture, no offset up and down, or very small offset, so that the formed channel structure has good electrical performance, thereby improving the yield of subsequent devices.
As described above, the overlay alignment detection method and the 3D memory device manufacturing method provided by the present invention have the following advantages:
the method for detecting the alignment of the semiconductor structure overlay comprises the steps of forming a first through structure in a first semiconductor structure on a substrate, forming a first filling layer in the first through structure, forming a second semiconductor structure above the first semiconductor structure, forming a second through structure in the second semiconductor structure, forming a first opening on the top of the first filling layer by the second through structure, removing the second semiconductor structure, scanning and imaging the top of the structure which exposes the first filling layer and the first opening after the second semiconductor structure is removed, and directly measuring information such as the line width of the first filling layer and the first opening, the offset distance and the offset angle of the centers of the first filling layer and the first opening in the scanned image, thereby obtaining the offset information of the first through structure and the second through structure. The through structure may be a channel hole, a through hole, a gate line slit, or the like. According to the method, the first through structure and the second through structure are directly detected through imaging, so that the detection is more visual, and the detection result is more accurate. Especially for a stacked structure in which the film layers are opaque, the method can obtain accurate through structure (such as channel holes, gate line gaps, etc.) data. The line width and the offset information can be used as a reference of a subsequent etching process to adjust or compensate parameters of the subsequent etching process.
The offset information of the through structure is obtained by the semiconductor overlay alignment detection method, and the offset information can be used for reference data of the next through structure etching process to adjust or compensate etching parameters, so that the etched through structures, such as the aperture of a channel hole is consistent, the vertical size of a grid line gap is consistent, offset cannot occur, and the like, thereby improving the quality of the channel hole and the grid line gap and improving the yield of subsequent devices.
The method for detecting the alignment of the semiconductor overlay is suitable for detecting holes or grooves with high aspect ratios such as grid line gaps, contact holes and the like in the stacked structure, and is particularly suitable for the stacked structure comprising the opaque film layer. The method has the advantages of easy operation, wide application range, accurate detection result and the like.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (11)
1. A method for detecting alignment of semiconductor structure overlay is characterized by comprising the following steps:
providing a substrate, and forming a first semiconductor structure on the substrate;
etching the first semiconductor structure to form a first through structure;
filling a first filling layer in the first through structure;
forming a second semiconductor structure over the first semiconductor structure and the first fill layer;
etching the second semiconductor structure to form a second through structure above the first through structure, wherein the second through structure forms a first opening at the top of the first filling layer;
removing the second semiconductor structure to expose the first filling layer;
scanning and imaging the top of the structure with the second semiconductor structure removed, and respectively determining the center of the first filling layer as a first center and the center of the first opening as a second center; measuring the distance between a first center and the second center to obtain the offset distance and/or the offset angle of the first through structure and the second through structure;
and adjusting etching parameters according to the offset distance and/or the offset angle.
2. The method for detecting the overlay alignment of a semiconductor structure according to claim 1, wherein the structure after the second semiconductor structure is removed is imaged to obtain offset information of the first through structure and the second through structure, further comprising the steps of:
measuring the cross-sectional dimension of the first filling layer to obtain the cross-sectional dimension of the first through structure;
measuring a cross-sectional dimension of the first opening of the first filling layer to obtain a cross-sectional dimension of the second through structure.
3. The method of claim 1, wherein the first and second semiconductor structures comprise stacked structures.
4. The method of claim 1, wherein the first semiconductor structure comprises a stacked structure and the second semiconductor structure comprises a sacrificial insulating layer.
5. The method of claim 1, wherein the substrate comprises a test wafer.
6. The method according to claim 1, wherein the first and second through structures are the same structure, and the first and second through structures comprise a channel hole and/or a gate slit.
7. A method of fabricating a 3D memory device, comprising the steps of:
obtaining adjusted etching parameters according to the method for detecting the alignment of the overlay of the semiconductor structure as claimed in any one of claims 1 to 6;
providing a substrate for manufacturing the 3D memory device, and forming a lower stack structure on the substrate;
etching the lower stack structure to form a lower channel hole;
and forming an upper stack structure above the lower stack structure, etching the upper stack structure based on the adjusted etching parameters, and forming an upper channel hole corresponding to the lower channel hole, wherein the upper channel hole and the lower channel hole form a channel hole which is communicated with the upper stack structure and the lower stack structure.
8. The method of manufacturing a 3D memory device according to claim 7, wherein etching the lower stack structure to form the lower channel hole comprises the steps of:
the method for detecting alignment of overlay of semiconductor structure according to any of claims 1 to 6, wherein the first semiconductor structure is etched to form a first through structure with unchanged etching parameters, the lower stack structure is etched while the substrate is partially etched, and a lower channel hole is formed in the substrate and the lower stack structure.
9. The method of manufacturing a 3D memory device according to claim 8, further comprising the steps of:
forming an epitaxial structure at the bottom of the channel hole;
forming a blocking layer, a charge trapping layer and a tunneling layer in sequence from the side wall of the channel hole to the center;
and forming a channel layer in the center of the channel hole, wherein the channel layer is communicated with the epitaxial structure.
10. The method of manufacturing a 3D memory device according to claim 7, further comprising the steps of:
etching the upper stack structure and the lower stack structure to form a grid line gap;
etching and removing the sacrificial layers of the upper stack structure and the lower stack structure to form a gate groove;
and filling a metal layer in the grid groove to form a metal grid.
11. The method of manufacturing a 3D memory device according to claim 10, further comprising the steps of:
forming a dielectric isolation layer on the side wall of the grid line gap;
and filling a conductive material in the gate line gap to form a common source contact.
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| CN112435936B (en) * | 2020-11-23 | 2022-03-15 | 长江存储科技有限责任公司 | Overlay precision detection method and semiconductor structure |
| CN112582422B (en) * | 2020-11-30 | 2022-02-11 | 长江存储科技有限责任公司 | Preparation method of three-dimensional memory and three-dimensional memory |
| CN114420696A (en) * | 2021-02-03 | 2022-04-29 | 长江存储科技有限责任公司 | 3D memory device, measuring method thereof and thin film measuring device |
| CN113571527B (en) * | 2021-07-26 | 2023-07-21 | 长江存储科技有限责任公司 | Channel hole manufacturing method, memory, manufacturing method thereof and memory system |
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