CN113571527B - Channel hole manufacturing method, memory, manufacturing method thereof and memory system - Google Patents
Channel hole manufacturing method, memory, manufacturing method thereof and memory system Download PDFInfo
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- CN113571527B CN113571527B CN202110845874.7A CN202110845874A CN113571527B CN 113571527 B CN113571527 B CN 113571527B CN 202110845874 A CN202110845874 A CN 202110845874A CN 113571527 B CN113571527 B CN 113571527B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention provides a channel hole manufacturing method, a memory, a manufacturing method of the memory and a memory system. The method comprises the steps of forming a filling column in each first channel hole, forming a patterned mask layer on a first stacking structure, etching the first stacking structure by taking the patterned mask layer as a mask, exposing the first end, forming an intermediate insulating layer on the patterned mask layer, forming a first protruding mark at the position of the first end, corresponding to the first end, of the intermediate insulating layer, forming a second protruding mark on the surface of the second stacking structure after forming a second stacking structure, and performing alignment by utilizing the second protruding mark at the position of a preformed second channel through hole, so that deviation of the forming position of the second channel through hole is reduced, alignment precision between the second channel through hole and the first channel through hole is improved, and electrical performance of a device is ensured.
Description
Technical Field
The invention relates to the technical field of memories, in particular to a manufacturing method of a channel hole, a memory, a manufacturing method of the memory and a memory system.
Background
In order to continuously increase the memory density capacity and reduce the critical size of the memory, many memory designs and manufacturers change the traditional 2D integration mode, and the memory density of the NAND flash memory is increased by adopting a three-dimensional stacking technology.
In the current 3D NAND memory, a stacked 3D NAND memory structure is generally implemented by vertically stacking multiple layers of data storage units. In order to obtain the above-described stacked 3D NAND memory structure, it is necessary to form a stacked structure in which a sacrificial layer and an isolation layer are alternately stacked on a silicon substrate, and etch the stacked structure to form a Channel (CH), form a gate spacer (GLS) in the stacked structure after forming a memory structure in the channel, and then remove the sacrificial layer to fill a gate electrode in contact with the memory structure.
Along with the gradual increase of the number of vertical stacking layers, the thickness accuracy and uniformity of the stacking structure are difficult to ensure, and the etching difficulty of a high aspect ratio channel is gradually improved, so that the problems of channel reaming (tilting), skewing (tilting) and the like are easily generated. In order to solve the above-mentioned problems, a double stacking technique (double stacking) is proposed in the prior art, which is divided into a double deposition stacking structure and a trench, and the number of layers of the stacking structure deposited each time is less than that of a single stacking, and the depth of the etched trench is shallower, thereby being beneficial to the improvement of the yield.
In the above dual stacking technology, an alignment process is generally adopted to form a lower trench hole (LCH) and an upper trench hole (UCH) in two stacked structures, so that the two trench holes are communicated to form a deep hole, currently in the process of forming two stacked structures, an alignment groove is required to be formed on the surface of the stacked structure above by the alignment process for aligning the upper trench hole and the lower trench hole formed subsequently, however, the alignment groove is formed after the stacked structure above, the distance between the alignment groove and the lower trench hole is far, and a step of heat treatment is generally required in the deposition process of forming the stacked structure, the heat treatment can lead to bending of a substrate, thereby affecting the alignment precision (OVL) of the alignment process of forming the alignment groove, the alignment error of the alignment groove and the upper trench hole is further affected, and finally affecting the performance of the manufactured memory structure.
Disclosure of Invention
The invention mainly aims to provide a manufacturing method of a channel hole, a memory, a manufacturing method of the memory and a memory system, so as to solve the problem that the performance of a device is affected due to large alignment error of a lower channel hole and an upper channel hole in the prior art.
In order to achieve the above object, according to one aspect of the present invention, there is provided a method for manufacturing a channel hole, comprising the steps of: providing a substrate with a first stacked structure on the surface, wherein a plurality of first channel holes penetrating to the substrate are formed in the first stacked structure, and filling columns are formed in the first channel holes and have first ends far away from the substrate; forming a patterned mask layer on the first stacked structure, and etching the first stacked structure by taking the patterned mask layer as a mask so as to expose the first end part; forming an intermediate insulating layer on the patterned mask layer, wherein the first end part is positioned in the intermediate insulating layer, and a first convex mark is formed at a position of the intermediate insulating layer corresponding to the first end part; forming a second stacked structure on the intermediate insulating layer, the second stacked structure being formed with a second bump mark at a position corresponding to the first bump mark; and forming a second channel through hole sequentially penetrating through the second stacking structure and the intermediate insulating layer to the filling column by an overlay process based on the second raised mark, and removing the filling column to enable the second channel through hole to be communicated with the first channel through hole.
Further, the material of the packed column is carbon or carbide.
Further, the etching selectivity ratio of the patterned mask layer to the first stacked structure is greater than 1.
Further, the first stack structure includes a first sacrificial layer and a first isolation layer alternately stacked; the second stack structure includes second sacrificial layers and second isolation layers alternately stacked.
Further, the patterned mask layer is a polysilicon layer, the first sacrificial layer is a silicon nitride layer, the first isolation layer is a silicon oxide layer, and in the step of etching the first stacked structure with the patterned mask layer as a mask, etching is stopped on the silicon oxide layer so as to expose the first end portion.
Further, the step of forming a patterned mask layer on the first stacked structure includes: sequentially covering a mask material layer and a photoresist layer on the first stacked structure; patterning the photoresist layer; and etching the mask material layer by taking the patterned photoresist layer as a mask to obtain the patterned mask layer.
Further, the step of forming the second trench via includes: covering a hard mask on the surface of the second stacking structure, and forming a third raised mark at the position of the hard mask corresponding to the second raised mark; and forming an opening at the position of the third raised mark by adopting a photoetching process, and etching the second stacking structure through the opening to form a second channel through hole, wherein the opening corresponds to the first channel through hole one by one.
According to another aspect of the present invention, there is provided a method for manufacturing a memory, including the steps of: forming a stacked structure on the substrate by adopting the manufacturing method, wherein the stacked structure is provided with a channel hole penetrating to the substrate and comprises sacrificial layers and isolation layers which are alternately stacked along a direction away from the substrate; forming a memory structure in the channel hole; forming a gate spacer penetrating to the substrate in the stacked structure, the gate spacer being located between adjacent channel holes; and removing the sacrificial layer and forming a gate layer at a position corresponding to the sacrificial layer.
Further, the step of forming the memory structure includes: a stacked charge blocking layer, an electron trapping layer, a tunneling layer, and a channel layer are sequentially formed on sidewalls of the channel hole.
According to another aspect of the present invention, there is also provided a memory including a substrate having a dual gate stack structure including a first gate stack structure, an intermediate insulating layer, and a second gate stack structure sequentially stacked in a direction away from the substrate, the first gate stack structure having a first channel hole therethrough to the substrate, the intermediate insulating layer and the second gate stack structure having a second channel via in communication with the first channel hole, the memory structure being located in the first and second channel vias in communication, the intermediate insulating layer having a first raised mark on a side thereof away from the substrate, the second gate stack structure having a second raised mark corresponding to the first raised mark on a side surface thereof away from the substrate, the second channel via sequentially penetrating the second raised mark and the first raised mark.
According to another aspect of the present invention, there is also provided a memory system comprising a controller and the memory described above, the controller being coupled to the memory and controlling the memory to store data.
After forming the first channel holes in the first stacked structure, forming filling columns in the first channel holes, wherein each filling column is provided with a first end part far away from a substrate, forming a patterned mask layer on the first stacked structure, etching the first stacked structure by taking the patterned mask layer as a mask so as to expose the first end part, forming an intermediate insulating layer on the patterned mask layer, wherein the first end part is positioned in the intermediate insulating layer, and a first bulge mark is formed at the position of the intermediate insulating layer corresponding to the first end part, so that after forming a second stacked structure, a second bulge mark is correspondingly formed on the surface of the second stacked structure.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention. In the drawings:
FIG. 1 shows a schematic flow chart generated by a method for fabricating a channel hole according to an embodiment of the present application;
fig. 2 to 9 respectively show schematic structural views during the fabrication of a channel hole according to an embodiment of the present application;
FIG. 10 shows a flow diagram generated by a method of fabricating a memory according to an embodiment of the present application;
fig. 11 shows a schematic diagram of a connection relationship of a storage system provided in an embodiment of the present application.
Wherein the above figures include the following reference numerals:
100. a first stacked structure; 101. a substrate; 102. a packed column; 103. patterning the mask layer; 104. an intermediate insulating layer; 105. a first raised mark; 106. a second stacked structure; 107. a second raised mark; 108. a second trench via; 200. a first sacrificial layer; 201. a first isolation layer; 202. a mask material layer; 203. a photoresist layer; 1000. a three-dimensional memory; 2000. a controller; 3000. a host; 20000. a storage system.
Detailed Description
It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other. The invention will be described in detail below with reference to the drawings in connection with embodiments.
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As described in the background art, in the prior art, the alignment error between the lower channel hole and the upper channel hole is large, which affects the performance of the device, and in order to solve the above problem, the present application provides a method for manufacturing the channel hole, a memory and a manufacturing method thereof.
According to an exemplary embodiment of the present application, there is provided a method for manufacturing a channel hole, as shown in fig. 1, including the steps of:
step S101, as shown in fig. 2, providing a substrate 101 having a first stack structure 100 on a surface thereof, wherein a plurality of first channel holes penetrating the substrate are formed in the first stack structure 100, and a filling column 102 is formed in each of the first channel holes, the filling column 102 having a first end portion distant from the substrate;
step S102, as shown in fig. 3, of forming a patterned mask layer 103 on the first stacked structure 100, and etching the first stacked structure 100 with the patterned mask layer 103 as a mask, as shown in fig. 4 to 6, so as to expose the first end portion;
step S103, forming an intermediate insulating layer 104 on the patterned mask layer 103 to obtain a structure as shown in fig. 7, wherein the first end portion is located in the intermediate insulating layer 104, and a first bump mark 105 is formed on the intermediate insulating layer 104 at a position corresponding to the first end portion;
step S104, forming a second stacking structure 106 on the intermediate insulating layer to obtain a structure as shown in FIG. 8, wherein a second bump mark 107 is formed on the second stacking structure 106 at a position corresponding to the first bump mark 105;
in step S105, a second trench through hole 108 is formed sequentially penetrating the second stacked structure 106 and the intermediate insulating layer 104 to the filling column 102 by an alignment process based on the second bump mark 107, and the filling column 102 is removed so that the second trench through hole 108 communicates with the first trench through hole, thereby obtaining the structure shown in fig. 9.
In the method for manufacturing the trench holes, after the first trench holes in the first stacked structure are formed, the filling columns are formed in the first trench holes, the filling columns are provided with the first end parts far away from the substrate, then the patterned mask layer is formed on the first stacked structure, the patterned mask layer is used as a mask to etch the first stacked structure so as to expose the first end parts, the middle insulating layer is formed on the patterned mask layer, the first end parts are positioned in the middle insulating layer, the first protruding marks are formed at the positions of the middle insulating layer corresponding to the first end parts, and therefore after the second stacked structure is formed, the second protruding marks are correspondingly formed on the surface of the second stacked structure.
The substrate of the application can be selected according to the actual requirement of a device, and can comprise a silicon substrate, a germanium substrate, a silicon germanium substrate, an SOI substrate or a GOI substrate and the like.
According to a specific embodiment of the present application, the material of the packed column is carbon or carbide. Compared with the prior art that polysilicon (Poly) is used as the material of the filling column, the method of the application ensures that the manufacturing process of the channel hole is simpler and simultaneously ensures that the cost for manufacturing the channel hole is lower by using carbon or carbide as the material of the filling column.
In addition, in the prior art, under the condition that the Poly column is replaced by the carbon column, the carbon column is etched together while the first stacking structure is etched, so that the problem that the first end part of the carbon column cannot be exposed is solved, and subsequent alignment of upper and lower channel holes cannot be performed.
In order to further ensure that the patterned mask layer 103 can be removed more easily later, according to another specific embodiment of the present application, an etching selectivity ratio of the patterned mask layer 103 to the first stacked structure 100 is greater than 1.
In a practical application process, as shown in fig. 2, the first stacked structure 100 includes a first sacrificial layer 200 and a first isolation layer 201 that are alternately stacked; the second stack structure includes second sacrificial layers and second spacer layers (not shown) alternately stacked.
The first sacrificial layer 200, the first isolation layer 201, the second sacrificial layer, the second isolation layer, and the patterned mask layer 103 may be made of a material conventional in the art. In still another specific embodiment of the present application, the patterned mask layer is a polysilicon layer, the first sacrificial layer is a silicon nitride layer, the first isolation layer is a silicon oxide layer, the second sacrificial layer is a silicon nitride layer, and the second isolation layer is a silicon oxide layer.
In the case where the patterned mask layer 103 is a polysilicon layer and the first isolation layer 201 is a silicon oxide layer, in the step of etching the first stacked structure 100 using the patterned mask layer 103 as a mask, the etching can be stopped at the silicon oxide layer due to the high etching selectivity between the polysilicon and the silicon oxide layer, so that the first end portion is exposed.
In the above-mentioned embodiments, the specific method for forming the first stacked structure and the second stacked structure may be any feasible method in the prior art, and those skilled in the art may select a suitable method to form these structures according to the actual situation. For example, the forming process of the first stacking structure includes: and alternately depositing a first sacrificial layer and a first isolation layer on the substrate to form a first preparation stacking structure, and then etching the first preparation stacking structure to remove part of the first preparation stacking structure to form the first channel hole.
These structural layers described above may be formed by one or more of Molecular Beam Epitaxy (MBE), metal Organic Chemical Vapor Deposition (MOCVD), metal Organic Vapor Phase Epitaxy (MOVPE), hydride Vapor Phase Epitaxy (HVPE), and/or other well-known crystal growth processes.
The method for forming the patterned mask layer of the present application may be any available method in the prior art, and a person skilled in the art may determine a suitable method according to the actual situation to form the patterned mask layer of the present application. In order to simply and quickly form the patterned mask layer, in another specific embodiment of the present application, the step of forming the patterned mask layer on the first stacked structure includes: as shown in fig. 3, a mask material layer 202 and a photoresist layer 203 are sequentially covered on the first stacked structure 100; patterning the photoresist layer 203; the patterned photoresist layer 203 is used as a mask to etch the mask material layer 202, thereby obtaining the patterned mask layer 103. The process of patterning the photoresist layer 203 may be a photolithography process.
In still another embodiment of the present application, sequentially covering the mask material layers on the first stacked structure includes: setting a hard mask layer on the first stacking structure; and arranging an anti-reflection layer on the exposed surface of the hard mask layer, wherein the hard mask layer and the anti-reflection layer form the mask material layer.
Of course, the above-mentioned mask material layer of the present application is not limited to the above-mentioned forming method, but may be formed by other forming methods, and a person skilled in the art may select appropriate materials and processes according to practical situations to form the above-mentioned mask material layer of the present application.
In order to form the more stable mask material layer and ensure better lithography and etching effects, in a specific embodiment of the present application, the material of the hard mask layer includes Kodiak, and the anti-reflection layer includes SiON.
There are many methods for forming the photoresist layer of the present application, and those skilled in the art can select a suitable method to form the photoresist layer of the present application according to practical situations.
According to another embodiment of the present application, the step of forming the second trench through hole 108 includes: covering a hard mask on the surface of the second stacking structure, wherein a third protruding mark is formed at a position corresponding to the second protruding mark on the hard mask; and forming an opening at the position of the third bump mark by adopting a photoetching process, and etching the second stacked structure through the opening to form the second channel through holes 108, wherein the opening corresponds to the first channel holes one by one.
According to another exemplary embodiment of the present application, there is also provided a method for manufacturing a memory, as shown in fig. 10, including the steps of:
step S201, forming a stacked structure on a substrate by any one of the manufacturing methods, wherein the stacked structure is provided with a channel hole penetrating through the substrate, and comprises sacrificial layers and isolation layers which are alternately stacked along a direction away from the substrate;
step S202, forming a storage structure in the channel hole;
step S203, forming a grid isolation groove penetrating through the substrate in the stacking structure, wherein the grid isolation groove is positioned between adjacent channel holes;
step S204, removing the sacrificial layer and forming a gate layer at a position corresponding to the sacrificial layer.
In the method for manufacturing the memory, first, a channel hole is formed in a stacked structure on a substrate by using any one of the above manufacturing methods, the channel hole penetrates through the substrate, and the stacked structure includes a sacrificial layer and an isolation layer alternately stacked in a direction away from the substrate; then, forming a storage structure in the channel hole; forming a gate spacer penetrating through the substrate between adjacent channel holes in the stacked structure; finally, the sacrificial layer is replaced by a gate layer. According to the method, after the first channel holes in the first stacked structure are formed, the filling columns are formed in the first channel holes, the filling columns are provided with the first end parts far away from the substrate, then the patterned mask layer is formed on the first stacked structure, the patterned mask layer is used as a mask to etch the first stacked structure, so that the first end parts are exposed, the patterned mask layer is provided with the middle insulating layer, the first end parts are positioned in the middle insulating layer, the first protruding marks are formed at the positions of the middle insulating layer corresponding to the first end parts, and therefore after the second stacked structure is formed, the second protruding marks are formed on the surfaces of the second stacked structure, and due to the fact that the second protruding marks correspond to the positions of the preformed second channel through holes, alignment is carried out by utilizing the second protruding marks, the alignment accuracy between the second channel through holes and the first channel holes is guaranteed to be higher, and therefore the performance of the obtained memory is guaranteed to be better.
In a specific embodiment, the step of forming the storage structure includes: and sequentially forming a stacked charge blocking layer, an electron capturing layer, a tunneling layer and a channel layer on the side wall of the channel hole, namely forming a silicon-oxide-silicon nitride-oxide SONO stack structure.
In other embodiments, the gate layer and the first isolation layer that are alternately stacked may be directly deposited to form the stacked structure, and the stacked structure may be etched to form the channel hole without performing a gate layer replacement process.
According to still another exemplary embodiment of the present application, there is also provided a memory including a substrate having a double gate stack structure including a first gate stack structure having a first channel hole penetrating through the substrate, an intermediate insulating layer having a second channel through hole communicating with the first channel hole, and a second gate stack structure having a second channel through hole communicating with the first channel hole, and a memory structure located in the first channel hole and the second channel through hole, the intermediate insulating layer having a first bump mark on a side thereof remote from the substrate, and the second gate stack structure having a second bump mark corresponding to the first bump mark on a side thereof remote from the substrate, the second channel through hole penetrating through the second bump mark and the first bump mark in sequence.
The memory includes a substrate having a dual gate stack structure including a first gate stack structure, an intermediate insulating layer, and a second gate stack structure stacked in this order, the first gate stack structure having a first channel hole penetrating through the substrate, the intermediate insulating layer and the second gate stack structure having a second channel via communicating with the first channel hole, and the memory structure being located in the communicating first channel hole and second channel via, wherein a side of the intermediate insulating layer away from the substrate has a first bump mark, a side surface of the second gate stack structure away from the substrate has a second bump mark corresponding to the first bump mark, and the second channel via sequentially penetrates through the second bump mark and the first bump mark. In the memory, the second channel through hole is obtained by performing alignment by utilizing the first protruding mark and the second protruding mark, so that the deviation of the formation position of the second channel through hole is ensured to be smaller, the alignment precision between the second channel through hole and the first channel through hole is further ensured to be higher, and the electrical property of the memory is ensured to be better.
According to another aspect of the present invention, there is also provided a storage system 20000, and fig. 11 is an internal block diagram of the storage system 20000 according to an embodiment of the present invention. As shown in fig. 11, the storage system 20000 may comprise a three-dimensional memory 1000 and a controller 2000.
The three-dimensional memory 1000 may be the same as the memory described in any of the above embodiments, and will not be described in detail herein.
The controller 2000 may control the three-dimensional memory 1000 through the channel CH, and the three-dimensional memory 1000 may perform operations based on the control of the controller 2000 in response to a request from the host 3000. The three-dimensional memory 1000 may receive a command CMD and an address ADDR from the controller 2000 through a channel CH and access an area selected from the memory cell array in response to the address. In other words, the three-dimensional memory 1000 may perform an internal operation corresponding to a command on an area selected by an address.
In some embodiments, the above-described storage system may be implemented as a multimedia card such as universal flash memory storage (UFS) devices, solid State Drives (SSDs), MMC, eMMC, RS-MMC and micro MMC forms, secure digital cards in SD, mini SD and micro SD forms, personal Computer Memory Card International Association (PCMCIA) card type storage devices, peripheral Component Interconnect (PCI) type storage devices, PCI-express (PCI-E) type storage devices, compact Flash (CF) cards, smart media cards or memory sticks, and the like.
From the above description, it can be seen that the above embodiments of the present invention achieve the following technical effects: .
1) In the manufacturing method of the channel hole, after the first channel holes in the first stacked structure are formed, the filling columns are formed in the first channel holes, the filling columns are provided with the first end parts far away from the substrate, then the patterned mask layer is formed on the first stacked structure, the patterned mask layer is used as a mask to etch the first stacked structure, so that the first end parts are exposed, the patterned mask layer is provided with the middle insulating layer, the first end parts are positioned in the middle insulating layer, the positions of the middle insulating layer corresponding to the first end parts are provided with the first protruding marks, and therefore after the second stacked structure is formed, the second protruding marks are correspondingly formed on the surfaces of the second stacked structure.
2) In the method for manufacturing a memory described above, first, a channel hole is formed in a stacked structure on a substrate by using any one of the above-described manufacturing methods, the channel hole penetrates through the substrate, and the stacked structure includes a sacrificial layer and an isolation layer alternately stacked in a direction away from the substrate; then, forming a storage structure in the channel hole; forming a gate spacer penetrating through the substrate between adjacent channel holes in the stacked structure; finally, the sacrificial layer is replaced by a gate layer. According to the method, after the first channel holes in the first stacked structure are formed, the filling columns are formed in the first channel holes, the filling columns are provided with the first end parts far away from the substrate, then the patterned mask layer is formed on the first stacked structure, the patterned mask layer is used as a mask to etch the first stacked structure, so that the first end parts are exposed, the patterned mask layer is provided with the middle insulating layer, the first end parts are positioned in the middle insulating layer, the first protruding marks are formed at the positions of the middle insulating layer corresponding to the first end parts, and therefore after the second stacked structure is formed, the second protruding marks are formed on the surfaces of the second stacked structure, and due to the fact that the second protruding marks correspond to the positions of the preformed second channel through holes, alignment is carried out by utilizing the second protruding marks, the alignment accuracy between the second channel through holes and the first channel holes is guaranteed to be higher, and therefore the performance of the obtained memory is guaranteed to be better.
3) The memory comprises a substrate and a memory structure, wherein the substrate comprises a double-gate stacking structure, the double-gate stacking structure comprises a first gate stacking structure, an intermediate insulating layer and a second gate stacking structure which are sequentially stacked, a first channel hole penetrating through the substrate is formed in the first gate stacking structure, a second channel through hole communicated with the first channel hole is formed in the intermediate insulating layer and the second gate stacking structure, the memory structure is located in the communicated first channel hole and second channel through hole, a first protruding mark is formed on one side, far away from the substrate, of the intermediate insulating layer, a second protruding mark corresponding to the first protruding mark is formed on one side, far away from the substrate, of the second gate stacking structure, and the second channel through hole sequentially penetrates through the second protruding mark and the first protruding mark. In the memory, the second channel through hole is obtained by performing alignment by utilizing the first protruding mark and the second protruding mark, so that the deviation of the formation position of the second channel through hole is ensured to be smaller, the alignment precision between the second channel through hole and the first channel through hole is further ensured to be higher, and the electrical property of the memory is ensured to be better.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (11)
1. The manufacturing method of the channel hole is characterized by comprising the following steps of:
providing a substrate with a first stacked structure on the surface, wherein a plurality of first channel holes penetrating to the substrate are formed in the first stacked structure, and filling columns are formed in the first channel holes, and the filling columns are provided with first end parts far away from the substrate;
forming a patterned mask layer on the first stacked structure, and etching the first stacked structure by taking the patterned mask layer as a mask so as to expose the first end part;
forming an intermediate insulating layer on the patterned mask layer, wherein the first end part is positioned in the intermediate insulating layer, and a first protruding mark is formed at a position of the intermediate insulating layer corresponding to the first end part;
forming a second stacked structure on the intermediate insulating layer, wherein a second protruding mark is formed at a position of the second stacked structure corresponding to the first protruding mark;
and forming a second channel through hole sequentially penetrating through the second stacking structure and the intermediate insulating layer to the filling column by an overlay process based on the second raised mark, and removing the filling column to enable the second channel through hole to be communicated with the first channel through hole.
2. The method of claim 1, wherein the material of the packed column is carbon or carbide.
3. The method of claim 2, wherein an etch selectivity of the patterned mask layer to the first stack structure is greater than 1.
4. The method of claim 3, wherein,
the first stack structure includes a first sacrificial layer and a first isolation layer alternately stacked;
the second stack structure includes second sacrificial layers and second isolation layers alternately stacked.
5. The method of claim 4, wherein the patterned mask layer is a polysilicon layer, the first sacrificial layer is a silicon nitride layer, the first isolation layer is a silicon oxide layer, and etching is stopped in the silicon oxide layer to expose the first end portion during the step of etching the first stacked structure with the patterned mask layer as a mask.
6. The method of any one of claims 1 to 5, wherein forming the patterned mask layer on the first stacked structure comprises:
sequentially covering a mask material layer and a photoresist layer on the first stacked structure;
patterning the photoresist layer;
and etching the mask material layer by taking the patterned photoresist layer as a mask to obtain the patterned mask layer.
7. The method of any one of claims 1 to 5, wherein the step of forming the second trench via includes:
covering a hard mask on the surface of the second stacking structure, wherein a third protruding mark is formed at the position of the hard mask corresponding to the second protruding mark;
and forming an opening at the position of the third protruding mark by adopting a photoetching process, and etching the second stacking structure through the opening to form the second channel through holes, wherein the openings are in one-to-one correspondence with the first channel holes.
8. A method of fabricating a memory, comprising the steps of:
forming a stacked structure on a substrate with a channel hole penetrating to the substrate using the manufacturing method of any one of claims 1 to 7, the stacked structure including sacrificial layers and isolation layers alternately stacked in a direction away from the substrate;
forming a storage structure in the channel hole;
forming a gate spacer penetrating to the substrate in the stacked structure, wherein the gate spacer is positioned between adjacent channel holes;
and removing the sacrificial layer and forming a gate layer at a position corresponding to the sacrificial layer.
9. The method of manufacturing of claim 8, wherein the step of forming the memory structure comprises:
and sequentially forming a stacked charge blocking layer, an electron capturing layer, a tunneling layer and a channel layer on the side wall of the channel hole.
10. A memory comprising a substrate having a double gate stack structure and a memory structure, wherein the double gate stack structure comprises a first gate stack structure, an intermediate insulating layer and a second gate stack structure which are sequentially stacked in a direction away from the substrate, the first gate stack structure has a first channel hole penetrating through to the substrate, the intermediate insulating layer and the second gate stack structure have a second channel through hole communicated with the first channel hole, the memory structure is positioned in the communicated first channel hole and second channel through hole, a side of the intermediate insulating layer away from the substrate has a first raised mark, a side surface of the second gate stack structure away from the substrate has a second raised mark corresponding to the first raised mark, and the second channel through hole sequentially penetrates through the second raised mark and the first raised mark.
11. A memory system comprising a controller and the memory of claim 10, the controller coupled to the memory and controlling the memory to store data.
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