CN113571527A - Manufacturing method of channel hole, memory, manufacturing method of memory and memory system - Google Patents
Manufacturing method of channel hole, memory, manufacturing method of memory and memory system Download PDFInfo
- Publication number
- CN113571527A CN113571527A CN202110845874.7A CN202110845874A CN113571527A CN 113571527 A CN113571527 A CN 113571527A CN 202110845874 A CN202110845874 A CN 202110845874A CN 113571527 A CN113571527 A CN 113571527A
- Authority
- CN
- China
- Prior art keywords
- layer
- channel
- stacked structure
- forming
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention provides a manufacturing method of a channel hole, a memory, a manufacturing method of the memory and a memory system. The method forms a filled pillar in each first channel hole, the filled pillar having a first end portion away from the substrate, then forming a patterned mask layer on the first stacked structure, etching the first stacked structure with the patterned mask layer as a mask, so as to expose the first end part, and form an intermediate insulating layer on the patterned mask layer, the first end part is positioned in the intermediate insulating layer, a first convex mark is formed on the intermediate insulating layer corresponding to the first end part, so that after the second stacking structure is formed, the surface of the second stacking structure is correspondingly provided with a second convex mark, because the second raised mark corresponds to the position of the preformed second channel through hole, the deviation of the forming position of the second channel through hole is reduced by utilizing the second raised mark to carry out alignment, and further, the alignment precision between the second channel through hole and the first channel hole is improved, and the electrical performance of the device is ensured.
Description
Technical Field
The invention relates to the technical field of memories, in particular to a manufacturing method of a channel hole, a memory, a manufacturing method of the memory and a memory system.
Background
In order to continuously increase the memory density capacity and reduce the critical dimension of the memory with certain physical limitations, many memory designs and manufacturers change the conventional 2D integration mode, and adopt the three-dimensional stacking technology to increase the storage density of the NAND flash memory.
In the current 3D NAND memory, a stacked 3D NAND memory structure is generally implemented by vertically stacking multiple layers of data storage units. In order to obtain the stacked 3D NAND memory structure, it is necessary to form a stacked structure in which sacrificial layers and isolation layers are alternately stacked on a silicon substrate, etch the stacked structure to form a Channel (CH), form a memory structure in the channel, form a gate spacer (GLS) in the stacked structure, and then remove the sacrificial layer to fill a gate in contact with the memory structure.
Along with the gradual increase of the number of layers of vertical stacking, the thickness accuracy and uniformity of the stacking structure are difficult to ensure, and the etching difficulty of the channel with the high depth-to-width ratio is gradually improved, so that the problems of channel reaming (bending), skewing (twisting) and the like are easy to generate. In order to solve the above problems, a double stacking technique (double stacking) is proposed in the prior art, that is, a stacking structure and a channel are deposited twice, and the number of layers of the stacking structure deposited each time is less than that of a single stacking, and the depth of an etched channel is shallow, thereby facilitating the improvement of yield.
In the above-mentioned double-stacking technique, an alignment process is usually adopted to form a Lower Channel Hole (LCH) and an Upper Channel Hole (UCH) in two stacked structures, respectively, so as to connect the two channel holes to form a deep hole, and in the process of forming two stacked structures, an alignment groove is formed on the surface of the upper stacked structure by the alignment process, and is used for aligning the subsequently formed upper channel hole with the lower channel hole, however, the alignment groove is formed after the upper stacked structure, and has a longer distance from the lower channel hole, and a step of heat treatment is usually required in the deposition process of forming the stacked structure, the heat treatment can cause the substrate to bend, thereby affecting the alignment precision (OVL) of the alignment process of forming the alignment groove, the alignment deviation can further affect the alignment precision of the subsequently formed upper channel hole, and further increase the alignment error of the lower channel hole and the upper channel hole, ultimately affecting the performance of the resulting memory structure.
Disclosure of Invention
The invention mainly aims to provide a method for manufacturing a channel hole, a memory, a method for manufacturing the same and a memory system, so as to solve the problem that the alignment error of a lower channel hole and an upper channel hole is large and the performance of a device is influenced in the prior art.
In order to achieve the above object, according to an aspect of the present invention, there is provided a method of fabricating a channel hole, including the steps of: providing a substrate with a first stacked structure on the surface, wherein a plurality of first channel holes penetrating through the substrate are formed in the first stacked structure, and a filling column is formed in each first channel hole and is provided with a first end part far away from the substrate; forming a graphical mask layer on the first stacked structure, and etching the first stacked structure by taking the graphical mask layer as a mask so as to expose the first end part; forming an intermediate insulating layer on the patterned mask layer, wherein the first end part is positioned in the intermediate insulating layer, and a first protruding mark is formed on the intermediate insulating layer at a position corresponding to the first end part; forming a second stacking structure on the intermediate insulating layer, wherein a second bump mark is formed on the second stacking structure at a position corresponding to the first bump mark; and forming a second channel through hole which sequentially penetrates through the second stacking structure and the middle insulating layer to the filling column by adopting an alignment process based on the second protruding mark, and removing the filling column to enable the second channel through hole to be communicated with the first channel hole.
Further, the material of the packed column is carbon or carbide.
Further, the etching selection ratio of the patterned mask layer to the first stacked structure is greater than 1.
Further, the first stacked structure includes first sacrificial layers and first isolation layers that are alternately stacked; the second stack structure includes second sacrificial layers and second isolation layers alternately stacked.
Furthermore, the patterned mask layer is a polysilicon layer, the first sacrificial layer is a silicon nitride layer, the first isolation layer is a silicon oxide layer, and in the step of etching the first stacked structure by using the patterned mask layer as a mask, etching is stopped at the silicon oxide layer so as to expose the first end portion.
Further, the step of forming a patterned mask layer on the first stacked structure includes: sequentially covering a mask material layer and a photoresist layer on the first stacked structure; patterning the photoresist layer; and etching the mask material layer by taking the patterned photoresist layer as a mask to obtain a patterned mask layer.
Further, the step of forming a second trench via includes: covering a hard mask on the surface of the second stacking structure, wherein a third bump mark is formed at the position of the hard mask corresponding to the second bump mark; and forming an opening at the position of the third raised mark by adopting a photoetching process, and etching the second stacked structure through the opening to form a second channel through hole, wherein the opening corresponds to the first channel through hole one to one.
According to another aspect of the present invention, there is provided a method for manufacturing a memory, including the steps of: forming a stacked structure on the substrate by adopting the manufacturing method, wherein the stacked structure is provided with a channel hole penetrating through the substrate and comprises sacrificial layers and isolating layers which are alternately stacked along the direction far away from the substrate; forming a storage structure in the channel hole; forming gate isolation grooves penetrating through the substrate in the stacked structure, wherein the gate isolation grooves are positioned between adjacent channel holes; and removing the sacrificial layer and forming a gate layer at the position corresponding to the sacrificial layer.
Further, the step of forming the memory structure includes: a charge blocking layer, an electron trapping layer, a tunneling layer, and a channel layer are sequentially formed on sidewalls of the channel hole in a stacked manner.
According to another aspect of the present invention, there is also provided a memory including a substrate having a dual gate stack structure and a memory structure, the dual gate stack structure including a first gate stack structure, an intermediate insulating layer and a second gate stack structure sequentially stacked in a direction away from the substrate, the first gate stack structure having a first channel hole penetrating through to the substrate, the intermediate insulating layer and the second gate stack structure having a second channel via communicating with the first channel hole, the memory structure being located in the first channel hole and the second channel via communicating with each other, a side of the intermediate insulating layer away from the substrate having a first protrusion mark, a side surface of the second gate stack structure away from the substrate having a second protrusion mark corresponding to the first protrusion mark, and the second channel via sequentially penetrating through the second protrusion mark and the first protrusion mark.
According to another aspect of the present invention, there is also provided a memory system including a controller and the above memory, the controller being coupled to the memory and controlling the memory to store data.
Applying the technical scheme of the invention, a method for manufacturing channel holes is provided, the method for manufacturing the channel holes comprises the steps of forming a filling column in each first channel hole after forming the first channel hole in a first stacked structure, forming a graphical mask layer on the first stacked structure, etching the first stacked structure by taking the graphical mask layer as a mask to expose the first end, forming an intermediate insulating layer on the graphical mask layer, wherein the first end is positioned in the intermediate insulating layer, a first bulge mark is formed on the intermediate insulating layer at a position corresponding to the first end, so that a second bulge mark is correspondingly formed on the surface of the second stacked structure after forming the second stacked structure, and alignment is carried out by utilizing the second bulge mark due to the fact that the second bulge mark corresponds to the position of a pre-formed second channel through hole, the deviation of the forming position of the second channel through hole is reduced, the alignment precision between the second channel through hole and the first channel hole is improved, and the electrical performance of the device is guaranteed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 shows a schematic flow diagram generated by a method of fabricating a channel hole according to an embodiment of the present application;
fig. 2 to 9 respectively show a schematic structural diagram in a process of manufacturing a channel hole according to an embodiment of the present application;
FIG. 10 shows a flow diagram generated by a method of fabricating a memory according to an embodiment of the present application;
fig. 11 is a schematic diagram illustrating a connection relationship of a storage system provided in an embodiment of the present application.
Wherein the figures include the following reference numerals:
100. a first stacked structure; 101. a substrate; 102. filling a column; 103. patterning the mask layer; 104. an intermediate insulating layer; 105. a first raised indicia; 106. a second stacked structure; 107. a second raised indicia; 108. a second trench via; 200. a first sacrificial layer; 201. a first isolation layer; 202. a layer of masking material; 203. a photoresist layer; 1000. a three-dimensional memory; 2000. a controller; 3000. a host; 20000. a storage system.
Detailed Description
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged under appropriate circumstances in order to facilitate the description of the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As described in the background art, in the prior art, the alignment error between the lower channel hole and the upper channel hole is large and affects the device performance, and in order to solve the above problems, the present application provides a method for fabricating a channel hole, a memory and a method for fabricating the same.
According to an exemplary embodiment of the present application, there is provided a method for forming a channel hole, as shown in fig. 1, including the steps of:
step S101, as shown in fig. 2, providing a substrate 101 having a first stacked structure 100 on a surface thereof, wherein a plurality of first channel holes penetrating through the substrate are formed in the first stacked structure 100, and a filling pillar 102 is formed in each of the first channel holes, wherein the filling pillar 102 has a first end portion away from the substrate;
step S102, as shown in fig. 3, forming a patterned mask layer 103 on the first stacked structure 100, and etching the first stacked structure 100 by using the patterned mask layer 103 as a mask, as shown in fig. 4 to 6, so as to expose the first end portion;
step S103, forming an intermediate insulating layer 104 on the patterned mask layer 103 to obtain the structure shown in fig. 7, wherein the first end portion is located in the intermediate insulating layer 104, and a first protrusion mark 105 is formed on the intermediate insulating layer 104 at a position corresponding to the first end portion;
step S104, forming a second stacked structure 106 on the intermediate insulating layer to obtain the structure shown in fig. 8, wherein a second bump mark 107 is formed on the second stacked structure 106 at a position corresponding to the first bump mark 105;
step S105, forming a second trench via 108 penetrating the second stacked structure 106 and the inter-layer insulation layer 104 to the pillar 102 in sequence based on the second bump mark 107 by using an overlay process, and removing the pillar 102 to connect the second trench via 108 with the first trench via, thereby obtaining the structure shown in fig. 9.
In the method for manufacturing the channel holes, after the first channel holes in the first stacked structure are formed, filling columns are formed in the first channel holes, the filling columns are provided with first end parts far away from the substrate, then a graphical mask layer is formed on the first stacked structure, the first stacked structure is etched by taking the graphical mask layer as a mask, so that the first end parts are exposed, an intermediate insulating layer is formed on the graphical mask layer, the first end parts are positioned in the intermediate insulating layer, first protruding marks are formed on the intermediate insulating layer at positions corresponding to the first end parts, therefore, after the second stacked structure is formed, second protruding marks are correspondingly formed on the surface of the second stacked structure, and due to the fact that the second protruding marks correspond to the positions of pre-formed second channel through holes, alignment is conducted by utilizing the second protruding marks, and deviation of the forming positions of the second channel through holes is reduced, and further, the alignment precision between the second channel through hole and the first channel hole is improved, and the electrical performance of the device is better.
The substrate of the present application may be selected according to the actual requirements of the device, and may include a silicon substrate, a germanium substrate, a silicon germanium substrate, an SOI substrate, a GOI substrate, or the like.
According to a specific embodiment of the present application, the material of the packed column is carbon or carbide. Compared with the prior art in which polycrystalline silicon (Poly) is used as the material of the filling column, the method of the application ensures that the manufacturing process of the channel hole is simpler and the cost for manufacturing the channel hole is lower by using carbon or carbide as the material of the filling column.
In addition, in the prior art, when the Poly column is replaced with the carbon column, the carbon column is etched while the first stacked structure is etched, so that the problem that the first end of the carbon column cannot be exposed is solved, and subsequent alignment of the upper channel hole and the lower channel hole cannot be performed.
In order to further ensure that the patterned mask layer 103 can be removed more easily subsequently, according to another embodiment of the present application, an etching selection ratio between the patterned mask layer 103 and the first stacked structure 100 is greater than 1.
In practical applications, as shown in fig. 2, the first stacked structure 100 includes first sacrificial layers 200 and first isolation layers 201 that are alternately stacked; the second stack structure includes second sacrificial layers and second isolation layers (not shown) alternately stacked.
The first sacrificial layer 200, the first isolation layer 201, the second sacrificial layer, the second isolation layer, and the patterned mask layer 103 may be made of materials that are conventional in the art. In yet another embodiment of the present application, the patterned mask layer is a polysilicon layer, the first sacrificial layer is a silicon nitride layer, the first isolation layer is a silicon oxide layer, the second sacrificial layer is a silicon nitride layer, and the second isolation layer is a silicon oxide layer.
In the case where the patterned mask layer 103 is a polysilicon layer and the first isolation layer 201 is a silicon oxide layer, in the step of etching the first stacked structure 100 using the patterned mask layer 103 as a mask, due to the high etching selectivity between the polysilicon and the silicon oxide, the etching can be stopped at the silicon oxide layer, so that the first end portion is exposed.
In the above solution, the specific method for forming the first stacked structure and the second stacked structure may be any feasible method in the prior art, and those skilled in the art may select an appropriate method to form these structures according to actual situations. For example, the forming process of the first stacked structure includes: and alternately depositing a first sacrificial layer and a first isolation layer on the substrate to form a first preliminary stacking structure, etching the first preliminary stacking structure, removing part of the first preliminary stacking structure, and forming the first channel hole.
These structural layers described above may be formed via one or more of Molecular Beam Epitaxy (MBE), Metal Organic Chemical Vapor Deposition (MOCVD), Metal Organic Vapor Phase Epitaxy (MOVPE), Hydride Vapor Phase Epitaxy (HVPE), and/or other well-known crystal growth processes.
The method for forming the patterned mask layer of the present application may be any feasible method in the prior art, and those skilled in the art can determine an appropriate method for forming the patterned mask layer of the present application according to practical situations. In order to form the patterned mask layer more easily and quickly, in another embodiment of the present invention, the step of forming the patterned mask layer on the first stacked structure includes: as shown in fig. 3, a mask material layer 202 and a photoresist layer 203 are sequentially covered on the first stacked structure 100; patterning the photoresist layer 203; the mask material layer 202 is etched using the patterned photoresist layer 203 as a mask, thereby obtaining the patterned mask layer 103. The process of patterning the photoresist layer 203 may be a photolithography process.
In another embodiment of the present application, sequentially covering a mask material layer on the first stacked structure includes: setting a hard mask layer on the first stacking structure; and arranging an anti-reflection layer on the exposed surface of the hard mask layer, wherein the hard mask layer and the anti-reflection layer form the mask material layer.
Of course, the mask material layer of the present application is not limited to the above-mentioned forming method, and other forming methods can be adopted, and those skilled in the art can select appropriate materials and processes according to actual situations to form the mask material layer of the present application.
In order to form the mask material layer with stability and ensure better photoetching and etching effects, in a specific embodiment of the present application, the material of the hard mask layer comprises Kodiak, and the anti-reflection layer comprises SiON.
There are many methods for forming the photoresist layer described above, and those skilled in the art can select an appropriate method for forming the photoresist layer described above according to actual circumstances.
According to another specific embodiment of the present application, the step of forming the second trench via 108 includes: covering a hard mask on the surface of the second stacking structure, wherein a third bump mark is formed on the hard mask at a position corresponding to the second bump mark; and forming an opening at the position of the third bump mark by using a photolithography process, and etching the second stacked structure through the opening to form the second trench through hole 108, wherein the openings correspond to the first trench through holes one to one.
According to another exemplary embodiment of the present application, there is also provided a method for manufacturing a memory, as shown in fig. 10, the method including the steps of:
step S201, forming a stacked structure on a substrate by adopting any one of the above manufacturing methods, wherein the stacked structure is provided with a channel hole penetrating through the substrate and comprises sacrificial layers and isolating layers which are alternately stacked along a direction far away from the substrate;
step S202, forming a storage structure in the channel hole;
step S203, forming gate isolation grooves penetrating to the substrate in the stacked structure, wherein the gate isolation grooves are located between adjacent channel holes;
step S204 is to remove the sacrificial layer and form a gate layer at a position corresponding to the sacrificial layer.
In the method of manufacturing the memory, first, a channel hole is formed in a stacked structure on a substrate by any one of the above-described manufacturing methods, the channel hole penetrating the substrate, the stacked structure including a sacrificial layer and an isolation layer alternately stacked in a direction away from the substrate; then, forming a storage structure in the channel hole; forming grid isolation grooves penetrating through the substrate between the adjacent channel holes in the stacked structure; finally, the sacrificial layer is replaced by a gate layer. The method of the present application forms a filling pillar in each first channel hole after forming the first channel hole in the first stacked structure, the filling pillar having a first end portion away from the substrate, then forms a patterned mask layer on the first stacked structure, etches the first stacked structure with the patterned mask layer as a mask to expose the first end portion, and forms an intermediate insulating layer on the patterned mask layer, the first end portion being located in the intermediate insulating layer, the intermediate insulating layer having a first protrusion mark formed at a position corresponding to the first end portion, so that a second protrusion mark is formed on a surface of the second stacked structure after forming the second stacked structure, and the alignment accuracy between the second channel hole and the first channel hole is ensured to be high by performing alignment using the second protrusion mark due to the position of the second protrusion mark corresponding to the pre-formed second channel hole, thereby ensuring better performance of the obtained memory.
In a specific embodiment, the step of forming the memory structure includes: and sequentially forming a charge blocking layer, an electron capturing layer, a tunneling layer and a channel layer which are stacked on the side wall of the channel hole, namely forming a SONO (silicon-oxide-silicon nitride-oxide) stacked structure.
In other embodiments, the gate layer and the first isolation layer, which are alternately stacked, may be directly deposited to form the stacked structure, and the stacked structure may be etched to form the channel hole without a gate layer replacement process.
According to still another exemplary embodiment of the present application, there is also provided a memory device, including a substrate having a dual gate stack structure and a memory structure, the dual gate stack structure including a first gate stack structure, an intermediate insulating layer, and a second gate stack structure sequentially stacked in a direction away from the substrate, the first gate stack structure having a first channel hole penetrating through the substrate, the intermediate insulating layer and the second gate stack structure having a second channel via communicating with the first channel hole, the memory structure being located in the first channel hole and the second channel via communicating with each other, a side of the intermediate insulating layer away from the substrate having a first protrusion mark, a side surface of the second gate stack structure away from the substrate having a second protrusion mark corresponding to the first protrusion mark, the second channel through hole sequentially penetrates the second protrusion mark and the first protrusion mark.
The memory comprises a substrate with a double-gate stack structure and a memory structure, wherein the double-gate stack structure comprises a first gate stack structure, an intermediate insulating layer and a second gate stack structure which are sequentially stacked, the first gate stack structure having a first channel hole penetrating through the substrate, the interlayer insulating layer and the second gate stack structure having a second channel via communicating with the first channel hole, the memory structure being located in the communicating first channel hole and second channel via, wherein, one side of the middle insulating layer far away from the substrate is provided with a first convex mark, one side surface of the second grid stacking structure far away from the substrate is provided with a second convex mark corresponding to the first convex mark, the second channel through hole sequentially penetrates the second protrusion mark and the first protrusion mark. In the memory, the second trench through hole is obtained by utilizing the first protruding mark and the second protruding mark to perform alignment, so that the deviation of the forming position of the second trench through hole is small, the alignment precision between the second trench through hole and the first trench through hole is high, and the electrical performance of the memory is good.
According to another aspect of the present invention, there is also provided a storage system 20000, and fig. 11 is an internal block diagram of the storage system 20000 according to an embodiment of the present invention. As shown in fig. 11, the storage system 20000 may include a three-dimensional memory 1000 and a controller 2000.
The three-dimensional memory 1000 may be the same as the memory described in any of the above embodiments, and is not described in detail in this application.
The controller 2000 may control the three-dimensional memory 1000 through the channel CH, and the three-dimensional memory 1000 may perform an operation based on the control of the controller 2000 in response to a request from the host 3000. The three-dimensional memory 1000 may receive a command CMD and an address ADDR from the controller 2000 through a channel CH and access a region selected from the memory cell array in response to the address. In other words, the three-dimensional memory 1000 may perform an internal operation corresponding to a command on a region selected by an address.
In some embodiments, the above-described storage system may be implemented as a device such as a universal flash memory storage (UFS) device, a Solid State Disk (SSD), a multimedia card in the form of an MMC, eMMC, RS-MMC, and micro-MMC, a secure digital card in the form of an SD, mini-SD, and micro-SD, a Personal Computer Memory Card International Association (PCMCIA) card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a PCI express (PCI-E) type storage device, a Compact Flash (CF) card, a smart media card, or a memory stick, and the like.
From the above description, it can be seen that the above-described embodiments of the present invention achieve the following technical effects: .
1) In the method for manufacturing the channel hole, after forming the first channel hole in the first stacked structure, a filling column is formed in each first channel hole, the filling column is provided with a first end part far away from the substrate, then a graphical mask layer is formed on the first stacked structure, the first stacked structure is etched by taking the graphical mask layer as a mask, so that the first end part is exposed, an intermediate insulating layer is formed on the graphical mask layer, the first end part is positioned in the intermediate insulating layer, a first bulge mark is formed on the intermediate insulating layer at a position corresponding to the first end part, so that after the second stacked structure is formed, a second bulge mark is correspondingly formed on the surface of the second stacked structure, and due to the fact that the second bulge mark corresponds to the position of the pre-formed second channel through hole, alignment is carried out by utilizing the second bulge mark, and the deviation of the forming position of the second channel through hole is reduced, and further, the alignment precision between the second channel through hole and the first channel hole is improved, and the electrical performance of the device is better.
2) In the method of manufacturing a memory of the present application, first, a channel hole is formed in a stacked structure on a substrate by any of the above-described manufacturing methods, the channel hole penetrating the substrate, the stacked structure including a sacrificial layer and an isolation layer alternately stacked in a direction away from the substrate; then, forming a storage structure in the channel hole; forming grid isolation grooves penetrating through the substrate between the adjacent channel holes in the stacked structure; finally, the sacrificial layer is replaced by a gate layer. The method of the present application forms a filling pillar in each first channel hole after forming the first channel hole in the first stacked structure, the filling pillar having a first end portion away from the substrate, then forms a patterned mask layer on the first stacked structure, etches the first stacked structure with the patterned mask layer as a mask to expose the first end portion, and forms an intermediate insulating layer on the patterned mask layer, the first end portion being located in the intermediate insulating layer, the intermediate insulating layer having a first protrusion mark formed at a position corresponding to the first end portion, so that a second protrusion mark is formed on a surface of the second stacked structure after forming the second stacked structure, and the alignment accuracy between the second channel hole and the first channel hole is ensured to be high by performing alignment using the second protrusion mark due to the position of the second protrusion mark corresponding to the pre-formed second channel hole, thereby ensuring better performance of the obtained memory.
3) The memory comprises a substrate with a double-gate stack structure and a memory structure, the double-gate stack structure comprises a first gate stack structure, an intermediate insulating layer and a second gate stack structure which are sequentially stacked, the first gate stack structure having a first channel hole penetrating through the substrate, the interlayer insulating layer and the second gate stack structure having a second channel via communicating with the first channel hole, the memory structure being located in the communicating first channel hole and second channel via, wherein, one side of the middle insulating layer far away from the substrate is provided with a first convex mark, one side surface of the second grid stacking structure far away from the substrate is provided with a second convex mark corresponding to the first convex mark, the second channel through hole sequentially penetrates the second protrusion mark and the first protrusion mark. In the memory, the second trench through hole is obtained by utilizing the first protruding mark and the second protruding mark to perform alignment, so that the deviation of the forming position of the second trench through hole is small, the alignment precision between the second trench through hole and the first trench through hole is high, and the electrical performance of the memory is good.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (11)
1. A method for manufacturing a channel hole is characterized by comprising the following steps:
providing a substrate with a first stacked structure on the surface, wherein a plurality of first channel holes penetrating through the substrate are formed in the first stacked structure, and a filling column is formed in each first channel hole and is provided with a first end part far away from the substrate;
forming a patterned mask layer on the first stacked structure, and etching the first stacked structure by taking the patterned mask layer as a mask so as to expose the first end part;
forming an intermediate insulating layer on the patterned mask layer, wherein the first end part is positioned in the intermediate insulating layer, and a first protruding mark is formed on the intermediate insulating layer at a position corresponding to the first end part;
forming a second stacked structure on the intermediate insulating layer, wherein a second raised mark is formed on the second stacked structure at a position corresponding to the first raised mark;
and forming a second channel through hole which sequentially penetrates through the second stacking structure and the intermediate insulating layer to the filling column by adopting an alignment process based on the second protruding mark, and removing the filling column to communicate the second channel through hole with the first channel hole.
2. The method of claim 1, wherein the material of the packed column is carbon or carbide.
3. The method of claim 2, wherein an etch selectivity ratio of the patterned mask layer to the first stacked structure is greater than 1.
4. The method of manufacturing according to claim 3,
the first stacked structure includes first sacrificial layers and first isolation layers that are alternately stacked;
the second stack structure includes second sacrificial layers and second isolation layers alternately stacked.
5. The method according to claim 4, wherein the patterned mask layer is a polysilicon layer, the first sacrificial layer is a silicon nitride layer, the first isolation layer is a silicon oxide layer, and in the step of etching the first stacked structure with the patterned mask layer as a mask, the etching is stopped at the silicon oxide layer to expose the first end portion.
6. The method of any of claims 1-5, wherein the step of forming the patterned mask layer on the first stacked structure comprises:
sequentially covering a mask material layer and a photoresist layer on the first stacked structure;
patterning the photoresist layer;
and etching the mask material layer by taking the patterned photoresist layer as a mask to obtain the patterned mask layer.
7. The method of fabricating according to any one of claims 1 to 5, wherein the step of forming the second trench via includes:
covering a hard mask on the surface of the second stacked structure, wherein the hard mask forms a third raised mark at a position corresponding to the second raised mark;
and forming an opening at the position of the third protruding mark by adopting a photoetching process, and etching the second stacked structure through the opening to form the second channel through hole, wherein the opening corresponds to the first channel hole one by one.
8. A method for manufacturing a memory is characterized by comprising the following steps:
forming a stacked structure on a substrate by using the manufacturing method of any one of claims 1 to 7, the stacked structure having a channel hole penetrating through the substrate, the stacked structure including sacrificial layers and isolation layers alternately stacked in a direction away from the substrate;
forming a storage structure in the channel hole;
forming gate spacers penetrating through the substrate in the stacked structure, the gate spacers being located between adjacent ones of the channel holes;
and removing the sacrificial layer, and forming a gate layer at a position corresponding to the sacrificial layer.
9. The method of claim 8, wherein the step of forming the memory structure comprises:
and sequentially forming a charge blocking layer, an electron capturing layer, a tunneling layer and a channel layer which are stacked on the side wall of the channel hole.
10. A memory comprises a substrate with a double-gate stack structure and a memory structure, the double gate stack structure comprises a first gate stack structure, an intermediate insulating layer and a second gate stack structure sequentially stacked in a direction away from the substrate, the first gate stack structure having a first channel hole therethrough to the substrate, the intermediate insulating layer and the second gate stack structure having a second channel via therein communicating with the first channel hole, the storage structure is positioned in the first channel hole and the second channel through hole which are communicated, one side of the intermediate insulating layer, which is far away from the substrate, is provided with a first raised mark, a side surface of the second gate stack structure away from the substrate is provided with a second protruding mark corresponding to the first protruding mark, the second channel through hole sequentially penetrates through the second protruding mark and the first protruding mark.
11. A memory system comprising a controller and the memory of claim 10, the controller coupled to the memory and controlling the memory to store data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110845874.7A CN113571527B (en) | 2021-07-26 | 2021-07-26 | Channel hole manufacturing method, memory, manufacturing method thereof and memory system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110845874.7A CN113571527B (en) | 2021-07-26 | 2021-07-26 | Channel hole manufacturing method, memory, manufacturing method thereof and memory system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113571527A true CN113571527A (en) | 2021-10-29 |
| CN113571527B CN113571527B (en) | 2023-07-21 |
Family
ID=78167657
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110845874.7A Active CN113571527B (en) | 2021-07-26 | 2021-07-26 | Channel hole manufacturing method, memory, manufacturing method thereof and memory system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113571527B (en) |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0892433A1 (en) * | 1997-07-15 | 1999-01-20 | International Business Machines Corporation | Method of forming an alignment mark in a semiconductor structure |
| US20020028528A1 (en) * | 2000-09-01 | 2002-03-07 | Shiro Ohtaka | Alignment marks and method of forming the same |
| US20110062510A1 (en) * | 2009-09-14 | 2011-03-17 | Han-Soo Joo | 3d non-volatile memory device and method for fabricating the same |
| US20110121366A1 (en) * | 2009-04-14 | 2011-05-26 | NuPGA Corporation | System comprising a semiconductor device and structure |
| US20110294278A1 (en) * | 2010-05-28 | 2011-12-01 | Renesas Electronics Corporation | Method for manufacturing semiconductor device |
| US20200035699A1 (en) * | 2018-07-27 | 2020-01-30 | Yangtze Memory Technologies Co., Ltd. | Multiple-stack three-dimensional memory device and fabrication method thereof |
| CN111276416A (en) * | 2020-02-20 | 2020-06-12 | 长江存储科技有限责任公司 | Method for detecting alignment of semiconductor structure alignment and method for manufacturing 3D memory device |
| CN111312691A (en) * | 2020-03-02 | 2020-06-19 | 长江存储科技有限责任公司 | Overlay alignment mark structure, overlay alignment measurement method and semiconductor device |
| US20200350258A1 (en) * | 2019-05-02 | 2020-11-05 | SK Hynix Inc. | Manufacturing method of a semiconductor memory device |
| US20210066342A1 (en) * | 2019-09-02 | 2021-03-04 | Kioxia Corporation | Semiconductor memory device and method for manufacturing semiconductor memory device |
| CN112563286A (en) * | 2020-12-09 | 2021-03-26 | 长江存储科技有限责任公司 | Method for manufacturing semiconductor device |
| CN112614846A (en) * | 2020-12-15 | 2021-04-06 | 长江存储科技有限责任公司 | Manufacturing method of channel hole, memory and manufacturing method of memory |
-
2021
- 2021-07-26 CN CN202110845874.7A patent/CN113571527B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0892433A1 (en) * | 1997-07-15 | 1999-01-20 | International Business Machines Corporation | Method of forming an alignment mark in a semiconductor structure |
| US20020028528A1 (en) * | 2000-09-01 | 2002-03-07 | Shiro Ohtaka | Alignment marks and method of forming the same |
| US20110121366A1 (en) * | 2009-04-14 | 2011-05-26 | NuPGA Corporation | System comprising a semiconductor device and structure |
| US20110062510A1 (en) * | 2009-09-14 | 2011-03-17 | Han-Soo Joo | 3d non-volatile memory device and method for fabricating the same |
| US20110294278A1 (en) * | 2010-05-28 | 2011-12-01 | Renesas Electronics Corporation | Method for manufacturing semiconductor device |
| US20200035699A1 (en) * | 2018-07-27 | 2020-01-30 | Yangtze Memory Technologies Co., Ltd. | Multiple-stack three-dimensional memory device and fabrication method thereof |
| US20200350258A1 (en) * | 2019-05-02 | 2020-11-05 | SK Hynix Inc. | Manufacturing method of a semiconductor memory device |
| US20210066342A1 (en) * | 2019-09-02 | 2021-03-04 | Kioxia Corporation | Semiconductor memory device and method for manufacturing semiconductor memory device |
| CN111276416A (en) * | 2020-02-20 | 2020-06-12 | 长江存储科技有限责任公司 | Method for detecting alignment of semiconductor structure alignment and method for manufacturing 3D memory device |
| CN111312691A (en) * | 2020-03-02 | 2020-06-19 | 长江存储科技有限责任公司 | Overlay alignment mark structure, overlay alignment measurement method and semiconductor device |
| CN112563286A (en) * | 2020-12-09 | 2021-03-26 | 长江存储科技有限责任公司 | Method for manufacturing semiconductor device |
| CN112614846A (en) * | 2020-12-15 | 2021-04-06 | 长江存储科技有限责任公司 | Manufacturing method of channel hole, memory and manufacturing method of memory |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113571527B (en) | 2023-07-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10957648B2 (en) | Three-dimensional memory device containing contact via structure extending through source contact layer and dielectric spacer assembly | |
| US10903237B1 (en) | Three-dimensional memory device including stepped connection plates and methods of forming the same | |
| US10516025B1 (en) | Three-dimensional NAND memory containing dual protrusion charge trapping regions and methods of manufacturing the same | |
| EP3613079B1 (en) | Three-dimensional memory device having contact via structures in overlapped terrace region and method of making thereof | |
| US11355515B2 (en) | Three-dimensional memory device including locally thickened electrically conductive layers and methods of manufacturing the same | |
| EP3420591B1 (en) | Through-memory-level via structures between staircase regions in a three-dimensional memory device and method of making thereof | |
| US10879264B1 (en) | Three-dimensional memory device containing through-array contact via structures between dielectric barrier walls and methods of making the same | |
| KR101857681B1 (en) | 3-dimensional semiconductor memory devices and methods for fabricating the same | |
| US10872857B1 (en) | Three-dimensional memory device containing through-array contact via structures between dielectric barrier walls and methods of making the same | |
| US11189637B2 (en) | Three-dimensional memory array including self-aligned dielectric pillar structures and methods of making the same | |
| US11121153B1 (en) | Three-dimensional memory devices containing structures for controlling gate-induced drain leakage current and method of making the same | |
| US11282783B2 (en) | Three-dimensional memory device with via structures surrounded by perforated dielectric moat structure and methods of making the same | |
| US11404427B2 (en) | Three-dimensional memory device including multi-tier moat isolation structures and methods of making the same | |
| US10797070B2 (en) | Three-dimensional memory device containing a replacement buried source line and methods of making the same | |
| US11127759B2 (en) | Three-dimensional memory devices containing structures for controlling gate-induced drain leakage current and method of making the same | |
| US11756877B2 (en) | Three-dimensional memory device with via structures surrounded by perforated dielectric moat structure and methods of making the same | |
| US20200219895A1 (en) | Three-dimensional memory device containing a replacement buried source line and methods of making the same | |
| CN112614846B (en) | Manufacturing method of channel hole, memory and manufacturing method of memory | |
| US20200357815A1 (en) | A three-dimensional memory device having a backside contact via structure with a laterally bulging portion at a level of source contact layer | |
| US11637118B2 (en) | Three-dimensional memory device containing auxiliary support pillar structures and method of making the same | |
| US12009306B2 (en) | Three-dimensional memory device containing a capped isolation trench fill structure and methods of making the same | |
| CN113571527B (en) | Channel hole manufacturing method, memory, manufacturing method thereof and memory system | |
| CN115036290A (en) | Semiconductor device, method of manufacturing the same, and three-dimensional memory system | |
| KR20130092341A (en) | Semiconductor device and method of manufacturing the same | |
| CN113517298B (en) | Three-dimensional memory, manufacturing method thereof and storage system with three-dimensional memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |