TW201320212A - Testkey structure and method for measuring step height by such testkey structure - Google Patents

Testkey structure and method for measuring step height by such testkey structure Download PDF

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TW201320212A
TW201320212A TW100139808A TW100139808A TW201320212A TW 201320212 A TW201320212 A TW 201320212A TW 100139808 A TW100139808 A TW 100139808A TW 100139808 A TW100139808 A TW 100139808A TW 201320212 A TW201320212 A TW 201320212A
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test
contact
height
test contact
stage
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TW100139808A
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TWI562258B (en
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Chih-Kai Kang
Shu-Hsuan Chih
Sheng-Yuan Hsueh
Chia-Chen Sun
Po-Kuang Hsieh
Chi-Horn Pai
Shih-Chieh Hsu
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United Microelectronics Corp
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Abstract

A testkey structure for use in measuring step height includes a substrate, and a pair of test contacts. The substrate includes an isolation region and a diffusion region. The test contact pair includes a first test contact and a second test contact for measuring electrical resistances. The first test contact is disposed on the diffusion region and the second test contact is disposed on the isolation region.

Description

測試鍵結構與使用此測試鍵結構以量測階段高度的方法Test key structure and method of using this test key structure to measure stage height

本發明大致上關於一種測試鍵結構,與使用此測試鍵結構以量測階段高度(step-height)的方法。特別是,本發明關於一種用來測量電阻之測試鍵結構,與使用此測試鍵結構以量測階段高度的方法。The present invention generally relates to a test key structure and a method of using the test key structure to measure a step-height. In particular, the present invention relates to a test key structure for measuring electrical resistance and a method of using the test key structure to measure the height of a stage.

光滑平坦的矽晶圓是用來製作積體電路的基礎。矽晶圓中各元件所形成階層(levels)的差異,例如金屬氧化半導電晶體(MOSFET)的淺溝渠隔離層(shallow trench isolation,STI)與鄰近電晶體主動區域(active region)的高度差,會造成基材表面凹凸不平的起伏,稱之為階段高度。此等階段高度對於半導體製程的良窳,起著關鍵性的影響。Smooth and flat silicon wafers are the basis for making integrated circuits. The difference in the level of formation of each component in the wafer, such as the height difference between the shallow trench isolation (STI) of the metal oxide semiconductive crystal (MOSFET) and the active region of the adjacent transistor. It will cause unevenness on the surface of the substrate, which is called the stage height. These stages are highly critical to the success of semiconductor processes.

此等關鍵性的影響可以涵蓋多個方面。例如,在製程上,基材表面凹凸的程度對於微影曝光的精確度造成重大的影響,例如造成對焦不良(defocus)或是失真等問題。而在元件特性上,會影響元件的可靠度。例如,基材表面的凹凸程度與元件隔離特性的接面漏電流(junction leakage)及元件之其他特性,包含短通道效應(short channel effect,SCE)、窄通道效應(narrow width effect,NWE)都具有高度的相關性。因此,如果想要有穩定的製程控制,例如化學機械研磨或是黃光製程,就需要一種能得知基材的階段高度,既快速又不破壞基材的方法。These key impacts can cover multiple aspects. For example, in the process, the degree of unevenness of the surface of the substrate has a major influence on the accuracy of the lithographic exposure, such as problems such as defocus or distortion. In terms of component characteristics, it will affect the reliability of the component. For example, the junction surface of the substrate and the junction leakage characteristics of the device isolation characteristics and other characteristics of the device include a short channel effect (SCE) and a narrow width effect (NWE). Has a high degree of correlation. Therefore, if there is a need for stable process control, such as chemical mechanical polishing or a yellow light process, a method is needed to know the stage height of the substrate, both quickly and without destroying the substrate.

目前已知有一些方法,可以得知基材的階段高度。例如,使用原子力顯微鏡技術(atomic force microscope,AFM)雖然可以窺知基材表面的狀況,但是卻不能夠在有限的時間內觀察到足夠範圍的表面。There are currently known methods for knowing the stage height of the substrate. For example, an atomic force microscope (AFM) can be used to see the surface condition of a substrate, but it is not possible to observe a sufficient range of surfaces in a limited time.

另一種已知方法,也可以得知基材的階段高度,稱為穿透式電子顯微鏡(Transmission Electron Microscopy,TEM)。雖然使用穿透式電子顯微鏡比起原子力顯微鏡技術較為省時,卻需要以破壞性的方式取得基材樣品。有鑑於現行技術並沒有一種得知基材階段高度兩全其美的方法,所以目前想要得知基材階段高度的方法仍有改善的空間。Another known method can also be used to know the stage height of the substrate, which is called Transmission Electron Microscopy (TEM). Although the use of a penetrating electron microscope is less time-consuming than atomic force microscopy, it is necessary to obtain a substrate sample in a destructive manner. In view of the current technology, there is no way to know that the height of the substrate stage is the best of both worlds, so there is still room for improvement in the current method of knowing the height of the substrate stage.

本發明於是提出一種測試鍵結構,與使用此測試鍵結構以量測階段高度的方法。本發明至少具有快速、準確又非破壞性取得階段高度之特徵。The present invention thus proposes a test key structure and a method of using the test key structure to measure the stage height. The invention is characterized by at least a fast, accurate and non-destructive acquisition stage height.

本發明首先提出一種測試鍵結構。本發明之測試鍵結構,包含基材與一組測試接觸(test contact)。基材具有絕緣區與擴散區,而一組測試接觸則包含用來測量電阻之第一測試接觸與第二測試接觸。第一測試接觸位於擴散區,而第二測試接觸則位於絕緣區。經由此測試鍵結構,即可間接地得知基材表面的階段高度。The present invention first proposes a test key structure. The test key structure of the present invention comprises a substrate and a set of test contacts. The substrate has an insulating region and a diffusion region, and a set of test contacts includes a first test contact for measuring resistance and a second test contact. The first test contact is in the diffusion region and the second test contact is in the insulating region. By thus testing the bond structure, the stage height of the substrate surface can be indirectly known.

本發明於是又提出一種使用此測試鍵結構以量測基材表面階段高度的方法。首先,提供一測試鍵結構。此測試鍵結構包含第一測試接觸與第二測試接觸,且第一測試接觸與第二測試接觸具有一階段高度。其次,經由第一測試接觸與第二測試接觸分別量得第一測試電阻值與第二測試電阻值。然後,參考一資料庫,而分別獨立地得到對應第一測試電阻值之第一測試高度與對應第二測試電阻值之第二測試高度。接著,計算第一測試高度與第二測試高度,即可以非破壞性地方式得到階段高度。The present invention then proposes a method of using this test key structure to measure the height of the surface phase of the substrate. First, a test key structure is provided. The test key structure includes a first test contact and a second test contact, and the first test contact and the second test contact have a one-stage height. Secondly, the first test resistance value and the second test resistance value are respectively measured through the first test contact and the second test contact. Then, referring to a database, the first test height corresponding to the first test resistance value and the second test height corresponding to the second test resistance value are independently obtained. Next, the first test height and the second test height are calculated, ie the stage height can be obtained in a non-destructive manner.

在本發明一實施例中,量測階段高度的方法,還可以包含以下之步驟。首先,提供多組高度不同之測試接觸。其次,經由多組測試接觸分別量得多組之測試電阻值。然後,測量多組測試接觸之多組高度。再來,彚整(integrate)對應多組高度之多組測試電阻值,即可以建立資料庫。In an embodiment of the invention, the method for measuring the height of the stage may further comprise the following steps. First, multiple sets of test contacts of different heights are provided. Secondly, a larger number of test resistance values were respectively contacted via multiple sets of tests. Then, measure the heights of multiple sets of test contacts. Then, a plurality of sets of test resistance values corresponding to a plurality of sets of heights are integrated, and a database can be established.

由於本發明可以經由測試鍵結構中之第一測試接觸與第二測試接觸,分別獨立地得到對應之第一測試高度與對應之第二測試高度。另外,利用計算第一測試高度與第二測試高度,即可以非破壞性的方式得到一階段高度,因此,本發明能夠以既快速又不破壞基材的方法得知基材的階段高度。本發明測量基材階段高度的方法具有兩全其美的優點,使得製程的穩定控制可以在既快速又不破壞基材的方法下順利進行。Since the present invention can independently contact the second test contact via the first test contact in the test key structure, the corresponding first test height and the corresponding second test height are independently obtained. In addition, by calculating the first test height and the second test height, a one-stage height can be obtained in a non-destructive manner. Therefore, the present invention can know the stage height of the substrate in a fast and non-destructive manner. The method of the present invention for measuring the height of the substrate stage has the best of both worlds, so that the stable control of the process can be carried out smoothly without breaking the substrate.

本發明係提供一種測試鍵結構,用以非破壞性量測一基材表面凹凸起伏的階段高度,例如淺溝渠隔離凸出基材表面所造成的階段高度。The present invention provides a test key structure for non-destructive measurement of the stage height of a surface of a substrate, such as a shallow trench separating the surface height caused by the surface of the substrate.

請參考第1圖至第3圖,第1圖至第3圖繪示形成本發明測試鍵結構之方法。首先,如第1圖所示,使用硬遮罩102在基材101中蝕刻出複數個用來形成淺溝渠隔離的溝渠103。其中,基材101可以包含有晶片區104與測試鍵區105,且晶片區104與測試鍵區105又可分別包含絕緣區106與擴散區107。此外,硬遮罩102可為單一薄膜層或堆疊薄膜層,包含有氮矽化合物或矽氧化合物等材料。Please refer to FIGS. 1 to 3, and FIGS. 1 to 3 illustrate a method of forming the test key structure of the present invention. First, as shown in FIG. 1, a plurality of trenches 103 for forming shallow trench isolation are etched into the substrate 101 using the hard mask 102. The substrate 101 may include a wafer region 104 and a test keypad 105, and the wafer region 104 and the test keypad 105 may respectively include an insulating region 106 and a diffusion region 107. In addition, the hard mask 102 may be a single film layer or a stacked film layer containing a material such as a nitrogen cerium compound or a cerium oxide compound.

隨後,如第2圖所示,將絕緣材料填入溝渠103,並於平坦化形成淺溝渠隔離110之後,移除硬遮罩102。由於硬遮罩102厚度的緣故,所以絕緣區106中的淺溝渠隔離110會分別相對凸出於晶片區104與測試鍵區105的基材101表面,而具有一階段高度。此外,在其他實施例中,絕緣區106中的淺溝渠隔離110亦可替換成其他絕緣物件,例如直接在基材101表面使用氧化法來局部形成場氧化層(圖未示)。Subsequently, as shown in FIG. 2, the insulating material is filled into the trench 103, and after the planarization forms the shallow trench isolation 110, the hard mask 102 is removed. Due to the thickness of the hard mask 102, the shallow trench isolations 110 in the insulating regions 106 will protrude from the surface of the substrate 101 of the wafer region 104 and the test keypad 105, respectively, with a one-stage height. In addition, in other embodiments, the shallow trench isolation 110 in the insulating region 106 can also be replaced with other insulating materials, such as directly forming an oxide layer on the surface of the substrate 101 by oxidation to form a field oxide layer (not shown).

接著如第3圖所示,進行所需之半導體製程,例如在基材101上形成離子井(圖未示)、矽閘極結構、源極摻雜區(圖未示)與汲極摻雜區(圖未示)等,並使用絕緣材料覆蓋矽閘極結構形成層間絕緣層108,隨後再使用化學機械研磨等平坦化製程來移除多餘的絕緣材料,直到矽閘極結構暴露出來為止。此時,位於晶片區104中的矽閘極結構115即為金氧半導體(MOS)元件的閘極,而位於淺溝渠隔離110上之矽閘極結構117則可以是過路閘極(passing gate)、電阻或電熔絲(eFuse)等元件。Next, as shown in FIG. 3, a desired semiconductor process is performed, for example, an ion well (not shown), a gate structure, a source doping region (not shown), and a gate doping are formed on the substrate 101. A region (not shown) or the like is used to cover the gate structure with an insulating material to form an interlayer insulating layer 108, and then a planarization process such as chemical mechanical polishing is used to remove excess insulating material until the gate structure is exposed. At this time, the gate structure 115 in the wafer region 104 is the gate of the metal oxide semiconductor (MOS) device, and the gate structure 117 on the shallow trench isolation 110 may be the passing gate. Components such as resistors or electrical fuses (eFuse).

值得注意的是,伴隨該等半導體製程而同時形成於測試鍵區105中的矽閘極結構則成為本發明一組測試接觸120。此組測試接觸120包含第一測試接觸121與第二測試接觸125。第一測試接觸121與第二測試接觸125在測試鍵區105中的位置並不相同,例如,分別位於擴散區107與絕緣區106上。由於淺溝渠隔離110的表面凸出於基材101的表面,而具有一階段高度,且經過化學機械研磨,本發明之第一測試接觸121的頂面與第二測試接觸125的頂面共享平面,所以在本實施例中,第一測試接觸121與第二測試接觸125的厚度不同,如第3圖所示,位於基材101表面之第一測試接觸121的厚度大於位於淺溝渠隔離110的表面之第二測試接觸125的厚度,而且兩者的厚度差即為此階段高度。It is noted that the germanium gate structure simultaneously formed in the test keypad 105 along with the semiconductor processes becomes a set of test contacts 120 of the present invention. This set of test contacts 120 includes a first test contact 121 and a second test contact 125. The locations of the first test contact 121 and the second test contact 125 in the test keypad 105 are not the same, for example, on the diffusion region 107 and the insulating region 106, respectively. Since the surface of the shallow trench isolation 110 protrudes from the surface of the substrate 101 to have a stage height and is subjected to chemical mechanical polishing, the top surface of the first test contact 121 of the present invention shares a plane with the top surface of the second test contact 125. Therefore, in the embodiment, the thickness of the first test contact 121 and the second test contact 125 are different. As shown in FIG. 3, the thickness of the first test contact 121 on the surface of the substrate 101 is greater than that of the shallow trench isolation 110. The thickness of the second test contact 125 of the surface, and the difference in thickness between the two is the height of this stage.

視情況需要,還可以將晶片區104或是測試鍵區105中的至少一矽閘極結構以後置閘極(Gate-last)等製程,選擇性轉換為金屬閘極結構,並在矽閘極結構的周圍形成必要之源極接觸插塞(圖未示)或是汲極接觸插塞(圖未示)以及形成分別與第一測試接觸121與第二測試接觸125電連接之接觸插塞(圖未示)。例如,可以將第一測試接觸121與第二測試接觸125其中一者或是全部都轉換為金屬閘極結構。而轉換為金屬閘極結構的方法可以是,先在矽閘極結構中經由蝕刻步驟形成所需的閘極溝渠,隨後將適當的金屬,例如功函數金屬層、阻障層、鋁、銅等金屬,填入閘極溝渠中同時一併覆蓋層間絕緣層108,再使用化學機械研磨移除多餘的金屬,直到層間絕緣層108暴露出來為止,即可以形成金屬閘極結構。經過上述步驟,第一測試接觸121與/或第二測試接觸125可獨立為金屬閘極結構或是矽閘極結構。Optionally, the wafer region 104 or at least one gate structure of the test keypad 105 may be selectively converted into a metal gate structure by a gate-last process such as a gate-gate and a gate gate. A necessary source contact plug (not shown) or a drain contact plug (not shown) and a contact plug electrically connected to the first test contact 121 and the second test contact 125, respectively, are formed around the structure ( The figure is not shown). For example, one or both of the first test contact 121 and the second test contact 125 can be converted to a metal gate structure. The method of converting to a metal gate structure may be to first form a desired gate trench through an etching step in the gate structure, and then to apply a suitable metal such as a work function metal layer, a barrier layer, aluminum, copper, etc. The metal is filled in the gate trench while covering the interlayer insulating layer 108, and the excess metal is removed by chemical mechanical polishing until the interlayer insulating layer 108 is exposed, thereby forming a metal gate structure. Through the above steps, the first test contact 121 and/or the second test contact 125 can be independently a metal gate structure or a germanium gate structure.

經過前述之步驟,即可得到位於晶片區104中的矽閘極結構與/或金屬閘極結構,還有位於測試鍵區105中,對應於晶片區104中矽閘極結構與金屬閘極結構的本發明之測試鍵結構120。因為測試鍵區105中與晶片區104中的各閘極結構與各測試接觸的厚度差,都是淺溝渠隔離110凸出的階段高度,所以本發明之測試鍵結構100可以對應地模擬並測量位於晶片區104中的階段高度。本發明之測試鍵結構100包含基材101與一組測試接觸(test contact)120。基材101具有晶片區104與鄰近晶片區104之測試鍵區105。晶片區104與測試鍵區105均分別包含絕緣區106與擴散區107。絕緣區106可以是嵌入基材101中之淺溝渠隔離110或是場氧化層(Fox)等。Through the foregoing steps, the germanium gate structure and/or the metal gate structure in the wafer region 104 can be obtained, and also located in the test keypad 105 corresponding to the gate gate structure and the metal gate structure in the wafer region 104. The test key structure 120 of the present invention. Because the thickness difference between each gate structure in the test keypad 105 and the wafer region 104 and each test contact is the stage height of the shallow trench isolation 110, the test key structure 100 of the present invention can be correspondingly simulated and measured. The stage height in the wafer area 104. The test key structure 100 of the present invention comprises a substrate 101 and a set of test contacts 120. Substrate 101 has a wafer area 104 and a test keypad 105 adjacent wafer area 104. Both the wafer region 104 and the test keypad 105 include an insulating region 106 and a diffusion region 107, respectively. The insulating region 106 may be a shallow trench isolation 110 or a field oxide layer (Fox) embedded in the substrate 101.

仍如第3圖所示,本較佳實施例之該組測試接觸120包含兩個用來測量電阻之第一測試接觸121與第二測試接觸125。例如,第一測試接觸121位於離子井、源極摻雜區與汲極摻雜區等之擴散區107上方但不接觸絕緣區106。也就是說,第一測試接觸121會被擴散區域(diffusion region)所包圍,而第二測試接觸125則位於絕緣區106上方但不接觸擴散區107,而且第一測試接觸121與第二測試接觸125其中之一者會被另一者圍繞,而在第一測試接觸121與第二測試接觸125之間則有層間絕緣層108。本發明測試鍵結構100可以用來進行晶圓測試(wafer acceptance test,WAT),且經由此測試鍵結構100,即可間接地得知基材表面的階段高度。As still shown in FIG. 3, the set of test contacts 120 of the preferred embodiment includes two first test contacts 121 and second test contacts 125 for measuring resistance. For example, the first test contact 121 is located above the diffusion region 107 of the ion well, the source doped region and the drain doped region, but does not contact the insulating region 106. That is, the first test contact 121 is surrounded by a diffusion region, and the second test contact 125 is located above the insulating region 106 but does not contact the diffusion region 107, and the first test contact 121 is in contact with the second test. One of the 125 is surrounded by the other, and between the first test contact 121 and the second test contact 125 there is an interlayer insulating layer 108. The test bond structure 100 of the present invention can be used to perform a wafer acceptance test (WAT), and via the test bond structure 100, the stage height of the substrate surface can be indirectly known.

如果第一測試接觸121具有高度H1而第二測試接觸125具有高度H2,則第一測試接觸121與第二測試接觸125間的落差ΔH即為階段高度(ΔH=H1-H2)。If the first test contact 121 has a height H 1 and the second test contact 125 has a height H 2 , the drop ΔH between the first test contact 121 and the second test contact 125 is the stage height (ΔH=H 1 -H 2 ) .

此外,本發明之測試鍵結構100中之第一測試接觸121與第二測試接觸125可以有多種不同之佈局(layout)方式。請參閱第4圖,第4圖繪示本發明測試鍵結構一種實施例之上視圖。本發明之測試鍵結構100,包含一組測試接觸120。此組測試接觸120則包含用來測量電阻之第一測試接觸121與第二測試接觸125。第一測試接觸121成直條狀(strip),且第一測試接觸121被擴散區107所包圍。再者,第二測試接觸125係位於第一測試接觸121周圍,並同時包圍呈直條狀之第一測試接觸121與擴散區域107。第一測試接觸121與第二測試接觸125分別具有向外電連接用之導電插塞131/135。In addition, the first test contact 121 and the second test contact 125 in the test key structure 100 of the present invention can have a variety of different layout modes. Please refer to FIG. 4, which shows a top view of an embodiment of the test key structure of the present invention. The test key structure 100 of the present invention includes a set of test contacts 120. The set of test contacts 120 includes a first test contact 121 and a second test contact 125 for measuring resistance. The first test contact 121 is in a strip and the first test contact 121 is surrounded by the diffusion region 107. Furthermore, the second test contact 125 is located around the first test contact 121 and simultaneously encloses the first test contact 121 and the diffusion region 107 in a straight strip shape. The first test contact 121 and the second test contact 125 respectively have conductive plugs 131/135 for electrical connection.

需要注意的是,第4圖僅為例示,導電插塞131/135的位置並不限於第一測試接觸121與第二測試接觸125的末端。第一測試接觸121與第二測試接觸125的相對長度也並無限制。It should be noted that FIG. 4 is merely an illustration, and the positions of the conductive plugs 131/135 are not limited to the ends of the first test contact 121 and the second test contact 125. There is also no limitation on the relative length of the first test contact 121 and the second test contact 125.

由於閘極中之閘極導體會具有一種電阻性質,例如片電阻(sheet resistance),而且片電阻與導體材料的厚度,也就是閘極導體的高度,彼此間高度相關。因此,理論上,在相同的通道長度下,閘極導體的高度越高,其截面積便越大,而所具有的片電阻值就會越小,所以本發明即係藉由測量測試鍵結構的片電阻,而可以非破壞性的方式來得知閘極導體的高度與基材表面的階段高度。例如,經由導電插塞131量得第一測試接觸121之片電阻為ρ1,所以可以推算出其高度H1。類似地,經由導電插塞135則量得第二測試接觸125之片電阻為ρ2,所以可以推算出其高度H2。在本實施例中,高度H1大於高度H2,因此高度H1與高度H2之間的差值即為階段高度ΔH。Since the gate conductor in the gate will have a resistive property, such as sheet resistance, and the sheet resistance and the thickness of the conductor material, that is, the height of the gate conductor, are highly correlated with each other. Therefore, in theory, under the same channel length, the higher the height of the gate conductor, the larger the cross-sectional area, and the smaller the sheet resistance value, so the present invention measures the test key structure. The sheet resistance can be used in a non-destructive manner to know the height of the gate conductor and the stage height of the substrate surface. For example, the sheet resistance of the first test contact 121 is measured by the conductive plug 131 to be ρ 1 , so that the height H 1 can be derived. Similarly, the sheet resistance of the second test contact 125 is measured by the conductive plug 135 to be ρ 2 , so that the height H 2 can be derived. In the present embodiment, the height H 1 is greater than the height H 2 , so the difference between the height H 1 and the height H 2 is the stage height ΔH.

本發明於是又提供一種使用測試鍵結構以量測基材表面階段高度的方法。第5圖至第6圖繪示本發明使用測試鍵結構以量測基材表面階段高度方法的一實施方式。首先,請參考第3圖,提供一測試鍵結構100。本發明之測試鍵結構100之說明可以參考前述。其次,請參考第5圖,經由第一測試接觸121與第二測試接觸125分別量得第一測試電阻值ρ1與第二測試電阻值ρ2。此二測試電阻值ρ1與ρ2可以2點探針量測,但不僅限此量測方法,例如4點探針量測亦可。然後,請參考第6圖,參考一資料庫,其提供測試電阻值ρ與測試高度H間之關連性,而得到對應第一測試電阻值ρ1之第一測試高度H1,與對應第二測試電阻值ρ2之第二測試高度H2。接著,獨立計算第一測試高度H1與第二測試高度H2,即可以非破壞性的方式得到此階段高度ΔH。The present invention then provides a method of using a test key structure to measure the height of a surface stage of a substrate. Figures 5 through 6 illustrate an embodiment of the method of the present invention for measuring the surface height of a substrate using a test key structure. First, please refer to FIG. 3 to provide a test key structure 100. The description of the test key structure 100 of the present invention can be referred to the foregoing. Next, referring to FIG. 5, the first test resistance value ρ 1 and the second test resistance value ρ2 are respectively measured through the first test contact 121 and the second test contact 125. The two test resistance values ρ1 and ρ2 can be measured by a 2-point probe, but it is not limited to this measurement method, for example, 4-point probe measurement is also possible. Then, referring to FIG. 6, refer to a database, which provides a test with a test resistance value ρ off between the height H of the connected, test and obtain a first resistance value corresponding to the first test ρ height H 1 of 1, corresponding to the second The second test height H 2 of the resistance value ρ 2 is tested. Next, the first test height H 1 and the second test height H 2 are independently calculated, ie the stage height ΔH can be obtained in a non-destructive manner.

用來參考得到測試高度的資料庫,舉例而言,可以經由以下之方式得到。例如,可以先提供多組已知具有不同高度的閘極結構等之導體。而實際閘極結構的高度亦可以使用多種習知的方法來測量,例如原子力顯微鏡技術或是穿透式電子顯微鏡技術等破壞性的方式。同時,又經由測試接觸分別量得個別閘極結構的測試電阻值。當提供足夠的多組樣本之後,即可以彙整得到如第5圖所示,電阻值對應閘極結構高度的資料庫。或是,可以進一步整理資料庫,得到電阻值ρ對應閘極結構高度的公式H。例如:The database used to refer to the test height can be obtained, for example, by the following method. For example, a plurality of sets of conductors of gate structures and the like having different heights may be provided first. The height of the actual gate structure can also be measured using a variety of conventional methods, such as atomic force microscopy or transmissive electron microscopy. At the same time, the test resistance values of the individual gate structures are separately measured through the test contacts. After providing a sufficient number of sets of samples, a database of resistance values corresponding to the height of the gate structure as shown in Fig. 5 can be obtained. Alternatively, the database may be further organized to obtain a formula H of the resistance value ρ corresponding to the height of the gate structure. E.g:

H=aρ+kH=aρ+k

其中,a係數,k為校正常數。此外,測試接觸中之導體亦可以包含不同之導電材料。例如鋁或是矽等。如果測試接觸的材料不同時,可以參考先前所例示之方式,提供材料不同與高度不同之多組樣本,一樣可以彙整得到如第5圖所示,電阻值對應不同高度的資料庫。Where a coefficient, k is a correction constant. In addition, the conductors in the test contact may also contain different conductive materials. For example, aluminum or enamel. If the materials touched by the test are different, you can refer to the previously exemplified method to provide multiple sets of samples with different materials and heights, and you can collect the data with different resistance levels as shown in Figure 5.

另外,也可以分別測量由不同導電材料所形成之測試鍵結構。例如,由矽所形成之測試鍵結構,與由鋁所形成之測試鍵結構。理論上,雖然階段高度ΔH與測試鍵結構的材料無關,但是實際測量的結果卻有可能不同。但是如此一來,分別由不同導電材料所得到之階段高度ΔH可以用來估計階段高度ΔH的誤差範圍。In addition, the test bond structure formed by different conductive materials can also be measured separately. For example, the test bond structure formed by bismuth, and the test bond structure formed of aluminum. In theory, although the stage height ΔH is independent of the material of the test key structure, the actual measurement results may be different. However, the phase height ΔH obtained from different conductive materials, respectively, can be used to estimate the error range of the phase height ΔH.

經由上述的方法所得到的階段高度,例如50奈米(nm)-60 nm,可以用來檢驗半導體結構的可靠度與品質。如果所得到的階段高度不符合預期值,例如超過預期值或是小於預期值時,便可以啟動一後續的元件修正步驟,或是回饋並加以調整前階段的各半導體製程,以確保半導體結構的可靠度與品質。The stage height obtained by the above method, for example, 50 nanometers (nm) to 60 nm, can be used to verify the reliability and quality of the semiconductor structure. If the resulting phase height does not meet the expected value, such as exceeding the expected value or less than the expected value, a subsequent component modification step can be initiated, or the semiconductor process of the previous stage can be fed back and adjusted to ensure the semiconductor structure. Reliability and quality.

綜上所述,本發明即提供一種使用測試鍵結構以量測基材表面階段高度的方法暨其測試鍵結構,特徵之一在於包含兩個以上,形成一組之測試接觸,可以設計放在產品元件旁邊,間接、即時且能非破壞性的確認產品元件之階段高度是否符合預期。In summary, the present invention provides a method for measuring the height of a surface stage of a substrate using a test key structure and a test key structure thereof. One of the features is that two or more test contacts are formed, which can be designed and placed. Next to the product components, indirectly, instantaneously and non-destructively confirm whether the stage height of the product components is as expected.

以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100...測試鍵結構100. . . Test key structure

101...基材101. . . Substrate

102...硬遮罩102. . . Hard mask

103...溝渠103. . . ditch

104...晶片區104. . . Wafer area

105...測試鍵區105. . . Test keypad

106...絕緣區106. . . Insulating area

107...擴散區107. . . Diffusion zone

108...層間絕緣層108. . . Interlayer insulation

110...淺溝渠隔離110. . . Shallow trench isolation

115...矽閘極結構115. . .矽 gate structure

117...矽閘極結構117. . .矽 gate structure

120...一組測試接觸120. . . a set of test contacts

121...第一測試接觸121. . . First test contact

125...第二測試接觸125. . . Second test contact

131/135...導電插塞131/135. . . Conductive plug

第1圖至第3圖繪示形成本發明測試鍵結構之方法。Figures 1 through 3 illustrate a method of forming the test bond structure of the present invention.

第4圖繪示本發明測試鍵結構一種實施例之上視圖。Figure 4 is a top plan view of an embodiment of the test key structure of the present invention.

第5圖至第6圖繪示本發明使用測試鍵結構以量測基材表面階段高度方法的一實施方式。Figures 5 through 6 illustrate an embodiment of the method of the present invention for measuring the surface height of a substrate using a test key structure.

100...測試鍵結構100. . . Test key structure

101...基材101. . . Substrate

104...晶片區104. . . Wafer area

105...測試鍵區105. . . Test keypad

106...絕緣區106. . . Insulating area

107...擴散區107. . . Diffusion zone

108...層間絕緣層108. . . Interlayer insulation

110...淺溝渠隔離110. . . Shallow trench isolation

115...矽閘極結構115. . .矽 gate structure

117...矽閘極結構117. . .矽 gate structure

120...一組測試接觸120. . . a set of test contacts

121...第一測試接觸121. . . First test contact

125...第二測試接觸125. . . Second test contact

Claims (20)

一種測試鍵(testkey)結構,包含:一基材,具有一絕緣區與一擴散區;以及一組測試接觸(test contact),包含一第一測試接觸與一第二測試接觸,而用來測量電阻,其中該第一測試接觸位於該擴散區,而該第二測試接觸則位於該絕緣區。A test key structure includes: a substrate having an insulating region and a diffusion region; and a set of test contacts including a first test contact and a second test contact for measuring A resistor, wherein the first test contact is located in the diffusion region and the second test contact is located in the insulation region. 如請求項1之測試鍵結構,其中該第一測試接觸包含不接觸該絕緣區且為一金屬閘極與一矽閘極其中一者之一第一閘極結構,該第二測試接觸包含不接觸該擴散區且為一金屬閘極與一矽閘極其中一者之一第二閘極結構。The test key structure of claim 1, wherein the first test contact comprises a first gate structure that does not contact the insulating region and is one of a metal gate and a gate, the second test contact includes Contacting the diffusion region is a second gate structure of one of a metal gate and a gate. 如請求項1之測試鍵結構,其中該絕緣區與該擴散區具有一階段高度(step height)。The test key structure of claim 1, wherein the insulating region and the diffusion region have a step height. 如請求項1之測試鍵結構,其中該第一測試接觸的一頂面與該第二測試接觸的一頂面共享一平面。The test key structure of claim 1, wherein a top surface of the first test contact shares a plane with a top surface of the second test contact. 如請求項1之測試鍵結構,其中該第一測試接觸的厚度大於該第二測試接觸的厚度。The test key structure of claim 1, wherein the thickness of the first test contact is greater than the thickness of the second test contact. 如請求項1之測試鍵結構,其中該第一測試接觸被該擴散區所包圍。The test key structure of claim 1, wherein the first test contact is surrounded by the diffusion region. 如請求項1之測試鍵結構,其中該第一測試接觸與該第二測試接觸其中之一者圍繞另一者。The test key structure of claim 1, wherein the first test contact and the second test contact one of the other. 如請求項1之測試鍵結構,其中該第一測試接觸與該第二測試接觸之兩端分別與一接觸插塞電連接。The test key structure of claim 1, wherein both ends of the first test contact and the second test contact are electrically connected to a contact plug. 一種量測階段高度(step height)的方法,包含:提供一測試鍵結構,其包含一第一測試接觸與一第二測試接觸,且該第一測試接觸與該第二測試接觸具有一階段高度;經由該第一測試接觸與該第二測試接觸分別量得一第一測試電阻值與一第二測試電阻值;參考一資料庫,而得到對應該第一測試電阻值之一第一測試高度與對應該第二測試電阻值之一第二測試高度;以及計算該第一測試高度與該第二測試高度之一差值,以非破壞性的方式得到該階段高度。A method for measuring a step height, comprising: providing a test key structure including a first test contact and a second test contact, and the first test contact and the second test contact have a stage height Receiving a first test resistance value and a second test resistance value respectively through the first test contact and the second test contact; and referring to a database, obtaining a first test height corresponding to one of the first test resistance values And a second test height corresponding to one of the second test resistance values; and calculating a difference between the first test height and the second test height to obtain the stage height in a non-destructive manner. 如請求項9量測階段高度的方法,其中該測試鍵(testkey)結構,更包含:一基材,其包含一絕緣區與一擴散區,其中該第一測試接觸位於該擴散區上方但不接觸該絕緣區,而該第二測試接觸則位於該絕緣區上方但不接觸該擴散區。The method of claim 9, wherein the test key structure further comprises: a substrate comprising an insulating region and a diffusion region, wherein the first test contact is located above the diffusion region but not The insulating region is contacted while the second test contact is above the insulating region but does not contact the diffusion region. 如請求項9量測階段高度的方法,其中該絕緣區凸出該基材表面,而與該擴散區形成該階段高度。A method of measuring the height of a stage as claimed in claim 9, wherein the insulating region protrudes from the surface of the substrate and forms a height with the diffusion region. 如請求項9量測階段高度的方法,其中該第一測試接觸的一頂面與該第二測試接觸的一頂面共享一平面。A method of measuring a stage height according to claim 9, wherein a top surface of the first test contact shares a plane with a top surface of the second test contact. 如請求項9量測階段高度的方法,其中該第一測試接觸的厚度大於該第二測試接觸的厚度。A method of measuring a stage height as claimed in claim 9, wherein the thickness of the first test contact is greater than the thickness of the second test contact. 如請求項9量測階段高度的方法,其中該第一測試接觸與該第二測試接觸之至少一者為一金屬閘極。The method of claim 9, wherein the at least one of the first test contact and the second test contact is a metal gate. 如請求項9量測階段高度的方法,其中該第一閘極結構與該第二閘極結構之至少一者為一矽閘極。The method of claim 9, wherein the first gate structure and the second gate structure are at least one gate. 如請求項9量測階段高度的方法,其中該第一測試接觸被該擴散區所包圍。A method of measuring a stage height as in claim 9, wherein the first test contact is surrounded by the diffusion zone. 如請求項9量測階段高度的方法,其中該第一測試接觸與該第二測試接觸其中之一者圍繞另一者。A method of measuring a stage height as claimed in claim 9, wherein the first test contact is in contact with the second test to surround the other. 如請求項9量測階段高度的方法,更包含提供多組高度不同之測試接觸;經由該多組測試接觸分別量得多組測試電阻值;測量該多組測試接觸之多組高度;彚整(integrate)對應該多組高度之多組測試電阻值,以建立該資料庫。The method of measuring the height of the stage of claim 9, further comprising providing a plurality of sets of test contacts having different heights; respectively, measuring a plurality of sets of test resistance values by the plurality of sets of test contacts; measuring the plurality of sets of test contact heights; (integrate) A set of test resistance values corresponding to multiple sets of heights to establish the database. 如請求項18量測階段高度的方法,其中使用破壞性的方式以測量該多組測試接觸之該多組高度。A method of measuring the height of a stage, as in claim 18, wherein a destructive manner is used to measure the plurality of sets of heights of the plurality of sets of test contacts. 如請求項9量測階段高度的方法,其中當得到之該階段高度不符合預期時,進行一元件修正步驟。A method of measuring the height of a stage, as in claim 9, wherein a component correction step is performed when the height of the stage is not as expected.
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CN110767572A (en) * 2018-07-27 2020-02-07 无锡华润上华科技有限公司 Method for monitoring step height of junction region of active region and isolation structure
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CN110767572A (en) * 2018-07-27 2020-02-07 无锡华润上华科技有限公司 Method for monitoring step height of junction region of active region and isolation structure
CN110767572B (en) * 2018-07-27 2021-11-05 无锡华润上华科技有限公司 Method for monitoring step height of junction region of active region and isolation structure
TWI722509B (en) * 2018-11-20 2021-03-21 南亞科技股份有限公司 Test structure, semiconductor device and method for obtaining fabricating information in semiconductor device
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CN109659296A (en) * 2018-12-18 2019-04-19 武汉华星光电半导体显示技术有限公司 The big plate of feeler switch and OLED for monitoring oled panel etch depth

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