CN110164818A - Form the method and three-dimensional storage of three-dimensional storage - Google Patents
Form the method and three-dimensional storage of three-dimensional storage Download PDFInfo
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- CN110164818A CN110164818A CN201910445232.0A CN201910445232A CN110164818A CN 110164818 A CN110164818 A CN 110164818A CN 201910445232 A CN201910445232 A CN 201910445232A CN 110164818 A CN110164818 A CN 110164818A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
Abstract
The present invention relates to a kind of methods and three-dimensional storage for forming three-dimensional storage.Method includes the following steps: semiconductor structure is provided, the first storehouse of stacking of the semiconductor structure with substrate, on the substrate and multiple first channels hole across first storehouse；The second storehouse is formed on first storehouse；It is formed across multiple second channels hole of second storehouse, the bottom in every one second channel hole is connected to the top in a first channel hole；And etching the multiple second channel hole bottom sidewall and at least partly first channel hole top sidewall, to expand the multiple second channel hole in the aperture and at least partly aperture of first channel hole at the top of the bottom.
Description
Technical field
The invention mainly relates to semiconductor making methods, are particularly to the formation of the method and three-dimensional storage of three-dimensional storage
Device.
Background technique
Semiconductor integrated circuit experienced since birth from small-scale, middle scale to extensive and ultra-large integrated
Developing stage, and have become one of technical field the most active in modern science and technology.
In field of semiconductor memory, in order to overcome conventional two-dimensional memory in terms of limitation, often
Higher performance and integrated level are realized by the way of stacking storage chip.Three-dimensional (3D) Stack Technology can be by different function
Chip or structure, by stacking or the micromachining technologies such as hole interconnection, make its is formed in vertical direction it is three-dimensional integrated, believe
Number connection 3D solid storing chip.Three-dimensional (3D) memory is exactly to be three-dimensionally disposed in memory cell using this technology
Substrate and then the storage density for improving memory.
In the three-dimensional storage part of such as 3D nand flash memory, storage array may include the core with channel structure
(core) area.Channel structure is formed in the channel hole for the stack layer (stack) for extending vertically through three-dimensional storage part.Usually pass through
Single etch forms the channel hole of stack layer.But in order to improve storage density and capacity, the number of plies of three-dimensional storage
(tier) continue to increase, such as rise to 96 layers, 128 layers or more from 64 layers.Under this trend, the method for single etch
It is higher and higher in processing cost, it is more and more inefficent in processing capacity.
Therefore, in the manufacturing process of three-dimensional storage, stack layer (stack) is usually divided into multiple heaps being stacked with
Stack (deck).For example, lower channel hole is first etched after forming push-down stack in dual stack technique (Dual Deck Process), then
The stacked on storehouse of heap and the upper channel hole of etching, then form the channel structure for filling upper and lower channel hole.What is be stacked is upper and lower
Two layer stacks need to be directed at (Overlay), so that the center line alignment in upper and lower channel hole.Alignment.
Existing alignment is utilized through photoetching (Photolithography) technology use in upper and lower channel hole
What the offset of heart line compensated.For example, spy is respectively formed on upper and lower two layer stack respectively using photomask (mask)
Fixed alignment mark (Overlay mark, OVL mark), to realize the alignment in upper and lower channel hole.Common alignment mark can
With the one or more groups of linear labels for being.
However, this alignment is only limitted to global migration, the case where being not particularly suited for local offset.For example,
The larger offset of upper and lower channel centerline hole caused by pressure (stress) just can not be compensated by photoetching technique.Therefore,
Industry needs between a kind of local channel hole for compensating adjacent storehouse that there are the methods of larger offset.
Summary of the invention
Technical problem to be solved by the invention is to provide it is a kind of formed three-dimensional storage method and three-dimensional storage,
The offset between the local channel hole of storehouse can be compensated.
The present invention is to solve above-mentioned technical problem and the technical solution adopted is that propose a kind of side for forming three-dimensional storage
Method, comprising the following steps: semiconductor structure is provided, stacking of the semiconductor structure with substrate, on the substrate
First storehouse and multiple first channels hole across first storehouse；The second storehouse is formed on first storehouse；Shape
At the multiple second channels hole for passing through second storehouse, the bottom in every one second channel hole and the top in a first channel hole
Connection；And the bottom sidewall in the multiple second channel hole and the top sidewall at least partly first channel hole are etched,
To expand the multiple second channel hole in the aperture of the bottom and at least partly first channel hole at the top
Aperture.
In one embodiment of this invention, at least partly top sidewall in etching at least partly first channel hole, makes
At least partly top sidewall is obtained to project radially outward relative to the bottom sidewall in the first channel hole.
In one embodiment of this invention, at least partly center line in second channel hole is relative to corresponding first channel
There is offset on the extending direction of the substrate in the center line in hole.
In one embodiment of this invention, when the center line of a certain second channel hole bottom is relative to corresponding first channel hole
Center line on the extending direction of the substrate exist offset when, etch the multiple first channel hole atop part side
Wall so that the center line at the top of the first channel of correspondence hole is not overlapped with the center line in the corresponding first channel hole, and compares
Center line of the center line in first channel of correspondence hole closer to a certain second channel hole bottom.
In one embodiment of this invention, in the step of forming the multiple second channel hole, every one second channel hole exists
The aperture of the bottom is less than corresponding first channel hole in the aperture at the top.
In one embodiment of this invention, the semiconductor structure further includes the sacrifice for filling the multiple first channel hole
Layer when being formed across multiple second channel holes of second storehouse, removes the sacrificial layer at the top of the multiple first channel hole.
In one embodiment of this invention, the bottom in the multiple second channel hole is etched using isotropic etching method
The top sidewall of side wall and at least partly first channel hole.
In one embodiment of this invention, the isotropic etching method includes wet etching and gas etching.
The present invention also proposes a kind of three-dimensional storage, comprising: substrate；First storehouse of the stacking on the substrate and
Second storehouse, first storehouse and the second storehouse respectively include the grid layer at interval；It is multiple in first storehouse
First channel hole；Multiple second channels hole in second storehouse, the bottom in every one second channel hole with one first
The top in channel hole is connected to, and wherein at least at least partly top sidewall in part first channel hole is relative to the first channel hole
Bottom sidewall project radially outward.
In one embodiment of this invention, at least partly center line in second channel hole is relative to corresponding first channel
There is offset on the extending direction of the substrate in the center line in hole.
In one embodiment of this invention, when the center line of a certain second channel hole bottom is relative to corresponding first channel hole
Center line on the extending direction of the substrate exist offset when, the atop part side wall in the specific first channel hole is opposite
It is projected radially outward in bottom sidewall, so that the center line at the top of the first channel of correspondence hole and the corresponding first channel hole
Center line be not overlapped, and than the center line in first channel of correspondence hole closer in a certain second channel hole bottom
Heart line.
In one embodiment of this invention, every one second channel hole is less than corresponding first channel hole in the aperture of the bottom
In the aperture at the top.
In one embodiment of this invention, the bottom cross section in the multiple second channel hole is round；And when a certain
The center line in the second channel hole bottom exists on the extending direction of the substrate relative to the center line in corresponding first channel hole
When offset, the top cross-sectional in first channel of correspondence hole is round.
In one embodiment of this invention, the bottom cross section in the multiple second channel hole is round；And when a certain
The center line in the second channel hole bottom exists on the extending direction of the substrate relative to the center line in corresponding first channel hole
When offset, the top cross-sectional in first channel of correspondence hole is non-circular.
In one embodiment of this invention, three-dimensional storage further include: multiple in the multiple first channel hole
First channel layer；And multiple second channel layers in the multiple second channel hole, every one second channel layer are corresponding every
One first channel layer.
The present invention forms the method and three-dimensional storage of three-dimensional storage, by the bottom for etching multiple second channels hole
The top sidewall of side wall and at least partly the first channel hole, to expand multiple second channels hole in the aperture and at least partly of bottom
In the aperture at top, can alleviate between the local channel hole of adjacent storehouse has larger offset in the first channel hole, tool
There is higher storehouse alignment precision.
Detailed description of the invention
For the above objects, features and advantages of the present invention can be clearer and more comprehensible, below in conjunction with attached drawing to tool of the invention
Body embodiment elaborates, in which:
Fig. 1-Fig. 4 is the section signal in the example process of the method for the formation three-dimensional storage of one embodiment of the invention
Figure.
Fig. 5 is the flow chart of the method for the formation three-dimensional storage of one embodiment of the invention.
Fig. 6 A and Fig. 6 B be center line alignment the first channel hole top and the second channel hole bottom before etching and
The schematic diagram projected on substrate after etching.
Fig. 6 C and Fig. 6 D be the first channel hole of disalignment top and the second channel hole bottom before etching and
The schematic diagram projected on substrate after etching.
Fig. 7 and Fig. 8 be respectively the first channel hole of disalignment top and the second channel hole bottom before etching
And the schematic diagram of the projected array after etching on substrate.
Fig. 9 to Figure 11 is each before the channel hole reaming of the method for the formation three-dimensional storage of one embodiment of the invention etches
Angle schematic diagram.
Figure 12 to Figure 14 is the channel hole reaming etching front and back of the method for the formation three-dimensional storage of one embodiment of the invention
Each angle schematic diagram.
Specific embodiment
For the above objects, features and advantages of the present invention can be clearer and more comprehensible, below in conjunction with attached drawing to tool of the invention
Body embodiment elaborates.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, but the present invention can be with
It is different from other way described herein using other and implements, therefore the present invention is by the limit of following public specific embodiment
System.
As shown in the application and claims, unless context clearly prompts exceptional situation, " one ", "one", " one
The words such as kind " and/or "the" not refer in particular to odd number, may also comprise plural number.It is, in general, that term " includes " only prompts to wrap with "comprising"
Include clearly identify the step of and element, and these steps and element do not constitute one it is exclusive enumerate, method or apparatus
The step of may also including other or element.
When describing the embodiments of the present invention, for purposes of illustration only, indicating that the sectional view of device architecture can disobey general proportion work
Partial enlargement, and the schematic diagram is example, should not limit the scope of protection of the invention herein.In addition, in practical system
It should include the three-dimensional space of length, width and depth in work.
For the convenience of description, herein may use such as " under ", " lower section ", " being lower than ", " following ", " top ", "upper"
Etc. spatial relationship word the relationships of an elements or features shown in the drawings and other elements or feature described.It will reason
Solve, these spatial relationship words be intended to encompass in use or device in operation, other than the direction described in attached drawing
Other directions.For example, being described as be in other elements or feature " below " or " under " if overturning the device in attached drawing
Or the direction of the element of " following " will be changed to " top " in the other elements or feature.Thus, illustrative word " under
Side " and " following " can include upper and lower both direction.Device may also have other directions (to be rotated by 90 ° or in its other party
To), therefore spatial relation description word used herein should be interpreted accordingly.In addition, it will also be understood that being referred to as when one layer at two layers
" between " when, it can be only layer between described two layers, or there may also be one or more intervenient layers.
In the context of this application, structure of the described fisrt feature in the "upper" of second feature may include first
Be formed as the embodiment directly contacted with second feature, also may include that other feature is formed between the first and second features
Embodiment, such first and second feature may not be direct contact.
It is referred to as " on the other part " it should be appreciated that working as a component, " being connected to another component ", " is coupled in
When another component " or " contacting another component ", it can directly on another component, be connected or coupled to,
Or another component is contacted, or may exist insertion part.In contrast, when a component is referred to as " directly another
On a component ", " being directly connected in ", " being coupled directly to " or when " directly contact " another component, insertion part is not present.Together
Sample, when first component referred to as " is in electrical contact " or " being electrically coupled to " second component, in the first component and this second
There is the power path for allowing electric current flowing between part.The power path may include capacitor, the inductor of coupling and/or permission electricity
Other components of flowing, or even do not contacted directly between conductive component.
Following embodiment of the invention proposes a kind of method for forming three-dimensional storage, the method for the formation three-dimensional storage
Can solve between the channel hole of the adjacent storehouse of three-dimensional storage has larger offset, helps to improve three-dimensional storage
The alignment precision of middle storehouse.
Fig. 1-Fig. 4 is the section signal in the example process of the method for the formation three-dimensional storage of one embodiment of the invention
Figure.Fig. 5 is the flow chart of the method for the formation three-dimensional storage of one embodiment of the invention.Below with reference to Fig. 1 to Fig. 5 to the present invention
The method of the formation three-dimensional storage of one embodiment is illustrated.
Step 510, semiconductor structure is provided.
This semiconductor structure is at least part that will be used for follow-up process to ultimately form three-dimensional storage part.Scheming
In semiconductor structure 100a exemplified by 1, the first of stacking of the semiconductor structure 100 with substrate 101, on substrate 101
Storehouse 110 and multiple first channels hole 120 across the first storehouse 110.In one example, in the first channel hole 120
Heart line (dotted line A in figure) is perpendicular to the surface of substrate 101, but embodiments herein is not limited thereto.
In one embodiment of this invention, the first storehouse 110 can be by first material layer 111 and second material layer 112
Alternately stacked lamination.Wherein, first material layer 111 can be used as grid layer or dummy gate layer.It can be with shape on first storehouse 110
At storehouse middle layer 113, the first storehouse 110 and storehouse thereon is isolated.The semiconductor structure 100 of example shown in Fig. 1 cuts open
In the figure of face, stair-stepping wordline bonding pad is formd around the first storehouse 110 in semiconductor structure 100.It is to be understood that word
Line bonding pad can be the concordant form of for example each layer, rather than ladder-like.
In one embodiment of this invention, lithographic process can be used to form the first channel hole 120 in the first storehouse 110.
For example, being exposed using photomask (not shown) to the first storehouse 110, cooperate corresponding etching, to form the first channel hole
120。
In one embodiment of this invention, above-mentioned semiconductor structure 100 further includes the sacrificial of filling multiple first channels hole 120
Domestic animal layer (sacrificial layer).As shown in Figure 1, being filled with sacrificial layer 122 in multiple first channels hole 120.
It is appreciated that the material of substrate 101 is, for example, silicon.The material of first material layer 111 and second material layer 112 is for example
It is silicon nitride, silica or combinations thereof.By taking the combination of silicon nitride and silica as an example, can using chemical vapor deposition (CVD),
Atomic layer deposition (ALD) or other suitable deposition methods successively replace deposited silicon nitride and silica, shape on substrate 101
At the first storehouse 110.In addition, the material of storehouse middle layer 113, which can be some and silicon nitride, has high etching selection ratio
Material, such as silica, silicon carbide, silicon oxide carbide and aluminium oxide etc..The material of sacrificial layer 122 can be silica, polysilicon
With photoresist etc..
Although there is described herein the exemplary composition of initial semiconductor structure 100, it is to be understood that, it is one or more special
Sign can be omitted, substituted or be increased to from this semiconductor structure 100 in this semiconductor structure 100.For example, substrate
Various well region (not shown) can be formed in 101 as needed.In addition, the material for each layer illustrated is only exemplary, example
As the material of substrate 101 can also be other siliceous compounds, such as SOI (silicon-on-insulator), SiGe, Si:C etc..
Step 520, the second storehouse is formed on the first storehouse 110.
In this step, the second storehouse is formed on the first storehouse and forms stack layer (stack) with the first storehouse.
Referring to figs. 1 to shown in Fig. 2, the second storehouse 210 is formed on the first storehouse 110 of semiconductor structure 100, obtains half
Conductor structure 200.The structure and material of second storehouse 210 can be similar with the first storehouse 110.For example, the second storehouse 210 includes
The first material layer and second material layer being stacked with.The material of first material layer and second material layer is, for example, silicon nitride, oxygen
SiClx or combinations thereof.Storehouse middle layer can also be formed on second storehouse 210.The material of storehouse middle layer can be some and nitrogen
SiClx has the material, such as silica, silicon carbide, silicon oxide carbide and aluminium oxide etc. of high etching selection ratio.
For example, in the sectional view of the semiconductor structure 100b of example shown in Fig. 2, the first storehouse of semiconductor structure 100b
It is stacked on 110 and forms the second storehouse 210.Second storehouse 210 includes the first material layer 211 and second material layer being stacked with
212.Storehouse middle layer 213 is formed on second storehouse 210.It is similar with the first storehouse 110, it is also formed around the second storehouse 210
Such as stair-stepping wordline bonding pad.It should be appreciated that the second storehouse 210 and the first storehouse 110 can also be in structure, materials etc.
Aspect is different.
Step 530, formed across multiple second channels hole of the second storehouse, the bottom in every one second channel hole with one the
The top in one channel hole is connected to.
Referring to figs. 2 to shown in Fig. 3, in the second storehouse 210 of semiconductor structure 200, is formed and had using techniques such as photoetching
Have across multiple second channels hole 220 of the second storehouse 210, obtains semiconductor structure 300.Semiconductor structure 300 has substrate
101, the first storehouse 110 and the second storehouse 210.First storehouse 110 and the second storehouse 210 stack gradually on substrate 101.The
One storehouse 110 has multiple the first channel holes 120 perpendicular to substrate 101, is filled with sacrificial layer 122 in the first channel hole 120.
It is formed in the second storehouse 210 across multiple second channels hole 220 of the second storehouse 210.Each second channel hole 220 is corresponding
In a first channel hole 120, and the top phase in the corresponding first channel hole 120 in bottom in every one second channel hole 220
Connection.In one example, the central axis in the second channel hole 220 is in the surface of substrate 101, but embodiments herein is simultaneously
It is non-as limit.
Illustratively, lithographic process can be used and form the second channel hole 220 in the second storehouse 210.For example, using light
Mask (not shown) is exposed the second storehouse 210, cooperates corresponding etching, to form the second channel hole 220.Optionally,
Be used to form photomask used in the second channel hole 220 can with light used in the first channel hole 120 is formed in step 510
Mask is identical.
In one embodiment of this invention, when being formed across multiple second channel holes 220 of the second storehouse 210, removal
The sacrificial layer at 120 top of multiple first channels hole.Such as semiconductor structure 300 shown in Fig. 3, the is being formed using photoetching process
During two channel holes 220, the sacrificial layer of the part at 120 top of the first channel hole is removed together.
In some embodiments, the top or bottom cross section in the first channel hole 120 and the second channel hole 220 are in substrate
Projection on 101 can be circle, be also possible to other non-circular equal rules or irregular figure, but embodiments herein is simultaneously
It is non-as limit.
In one embodiment of this invention, at least partly center line in the second channel hole 220 is relative to corresponding first channel
There is offset on the extending direction of substrate 101 in the center line in hole 120.Specifically, three-dimensional storage is in the mistake for forming storehouse
It will receive the influence of various internal or external factors, such as pressure in journey.It may between upper and lower channel hole in adjacent storehouse
There are a degree of offsets.As shown in figure 3, center of the center line B in the second channel hole 220 relative to the first channel hole 120
There is offset in line A, i.e. the center line in the first channel hole 120 and the second channel hole 220 does not weigh on the extending direction of substrate 101
It closes.Accordingly, the central point of projection of the bottom in the top in the first channel hole 120 and the second channel hole 220 on substrate 101
It is not overlapped.
Fig. 6 A be center line alignment the first channel hole top and the second channel hole bottom before etching on substrate
The schematic diagram of projection.Fig. 6 C is that the top in the first channel hole of disalignment and the bottom in the second channel hole are being served as a contrast before etching
The schematic diagram projected on bottom.As shown in Figure 6A, when the center line in the first channel hole 120 and the center line in the second channel hole 220 exist
When on the extending direction of substrate 101 without offset (alignment), the two is in the state of alignment.At this point, the top in the first channel hole 120
The central point of projection 611a of the portion on substrate 101 and the bottom in the second channel hole 220 are in the projection 612a on substrate 101
Heart point is overlapped.As shown in Figure 6 C, when the center line in the first channel hole 120 and the center line in the second channel hole 220 are in substrate 101
When there is offset on extending direction, the two is in non-aligned state.At this point, the top in the first channel hole 120 is on substrate 101
The central point of projection 622a of the central point with the bottom in the second channel hole 220 on substrate 101 of projection 621a be not overlapped.
In one embodiment of this invention, it is formed in the step 530 in multiple second channels hole 220, every one second channel hole
220 are less than corresponding first channel hole 120 in the aperture at top in the aperture of bottom.
In one example, with reference to shown in Fig. 6 A, when the first channel hole 120 and the second channel hole 220 are in alignment,
The aperture of projection 611a of the top in the first channel hole 120 on substrate 101 is greater than the bottom in the second channel hole 220 in substrate
Projection 612a on 101；Similarly, with reference to shown in Fig. 6 C, the first channel hole 120 and the second channel hole 220 are in non-aligned shape
When state, bottom of the aperture that projects 621a of the top in the first channel hole 120 on substrate 101 also greater than the second channel hole 220
Projection 622a on substrate 101.
When the first channel hole 120 and the second 220 misregistration of channel hole, the center line and second in the first channel hole 120
Larger offset will be present in the center line in channel hole 220 on the extending direction of substrate 101, this will lead to subsequent filling channel structure
During part stack layer by plasma damage.Also, it is also easy to lead to channel when filling channel layer and dielectric layer
Blocking, the junction especially between storehouse.Meanwhile it can also introduce air-gap and influence the performance of storage unit.
Step 540, the bottom sidewall in multiple second channels hole 220 and the top at least partly the first channel hole 120 are etched
Side wall.
In this step, the top of the bottom sidewall to multiple second channels hole 220 and at least partly the first channel hole 120
Side wall performs etching, to expand multiple second channels hole 220 in the aperture of bottom and at least partly the first channel hole 120 at top
Aperture.For example, in semiconductor structure 300, etching the bottom side in multiple second channels hole 220 with reference to shown in Fig. 3 to Fig. 4
The top of wall and at least partly the first channel hole 120 obtains semiconductor structure 400 shown in Fig. 4.
In one embodiment of this invention, at least partly top sidewall at least partly the first channel hole 120 is etched, so that
At least partly top sidewall is projected radially outward relative to the bottom sidewall in the first channel hole 120.
In one embodiment of this invention, when the center line of 220 bottom of a certain second channel hole is relative to corresponding first ditch
When there is offset in the center line in road hole 120, the part top in etching multiple first channels hole 120 on the extending direction of substrate 101
Portion's side wall, so that the center line at 120 top of corresponding first channel hole is not overlapped with the center line in corresponding first channel hole 120, and
Than corresponding to the center line in the first channel hole 120 closer to the center line of 220 bottom of a certain second channel hole.
Below with reference to Fig. 6 A, 6B to the etching front and back in the first channel hole 120 and the second channel hole 220 in alignment
State be described.
When the center line in the first channel hole 120 and the center line in the second channel hole 220 do not have on the extending direction of substrate 101
When offsetting the state of alignment (i.e. in), the central point of projection 611a of the top in the first channel hole 120 on substrate 101 with
The central point of projection 612a of the bottom in the second channel hole 220 on substrate 101 is overlapped.
After performing etching to the bottom sidewall in the second channel hole 220, the bottom in the second channel hole 220 is on substrate 101
Projection 612b is not moved and borehole enlargement relative to the projection 612a central point before its etching.The second channel hole after etching
The top in aperture the first channel corresponding still less than its hole 120 of projection 612b of 220 bottom on substrate 101 is in substrate
The aperture of projection 611a on 101.At this point, the etching processing procedure that the bottom sidewall in the second channel hole 220 is carried out without influence on
The top sidewall of the top sidewall in the first channel hole 120, the first channel hole 120 is not etched correspondingly.It etches the after processing procedure
Projection 611b of the top in one channel hole 120 on substrate 101 is being served as a contrast relative to the top in the first channel hole 120 before etching processing procedure
Projection 611a on bottom 101 does not change.
After etching processing procedure, the center line in the center line in the first channel hole 120 and the second channel hole 220 is in substrate 101
Still without offset (state i.e. in alignment), projection of the top in the first channel hole 120 on substrate 101 on extending direction
The central point of 611b is still overlapped with projection 612b of the bottom in the second channel hole 220 on substrate 101.
Illustratively, with reference to shown in Fig. 3 and Fig. 4, positioned at 300 middle position of semiconductor structure the first channel hole 120 with
Corresponding second channel hole 220 is in the state of alignment.Projection 611a of the top in the first channel hole 120 on substrate 101 with
The positional relationship of projection 612a of the bottom in the second channel hole 220 on substrate 101 is as shown in Figure 6A.In etching processing procedure, by
The aperture corresponding still less than its first of projection 612b of the bottom in the second channel hole 220 after etching on substrate 101
The aperture of projection 611a of the top in channel hole 120 on substrate 101, the top in the first centrally located channel hole 120
Side wall is not etched correspondingly, as shown in Figure 4.
It should be noted that in other embodiments of the invention, although the first channel hole 120 and corresponding second channel hole
220 states in alignment, but after being performed etching to the bottom sidewall in the second channel hole 220, the bottom in the second channel hole 220
The aperture of projection 612b on substrate 101 can be greater than projection of the top in its corresponding first channel hole 120 on substrate 101
The aperture of 611a.At this point, the etching processing procedure carried out to the bottom sidewall in the second channel hole 220 can influence the first channel hole simultaneously
The top sidewall of 120 top sidewall, the first channel hole 120 can correspondingly be etched.
With reference to shown in Fig. 6 B, etch the projection 611b of the top on substrate 101 in the first channel hole 120 after processing procedure relative to
Projection 611a central point of the top in the first channel hole 120 on substrate 101 does not move and borehole enlargement before etching processing procedure.The
Projection 612b of the bottom in two channel holes 220 on substrate 101 is being served as a contrast relative to the bottom in the second channel hole 220 before etching processing procedure
Projection 612a central point on bottom 101 does not move and borehole enlargement.And the top in the first channel hole 120 is serving as a contrast after etching processing procedure
Projection 611b on bottom 101 is overlapped (not shown) with projection 612b of the bottom in the second channel hole 220 on substrate 101.
Peak excursion degree when first channel hole 120 is in non-aligned state with corresponding second channel hole 220 with
And etching technics itself determines the etching processing procedure that the bottom sidewall to the second channel hole 220 when being in the state being aligned carries out
Whether the top sidewall in first channel hole 120 is influenced whether.
Below with reference to Fig. 6 C, 6D in non-aligned state the first channel hole 120 and the second channel hole 220 etching before
State afterwards is described.
When the center line in the first channel hole 120 and the center line in the second channel hole 220 are deposited on the extending direction of substrate 101
At offset (being in non-aligned state), the central point of projection 621a of the top in the first channel hole 120 on substrate 101
It is not overlapped with the central point of projection 622a of the bottom in the second channel hole 220 on substrate 101.For example, the second channel in Fig. 6 C
The central point of projection 622a of the bottom in hole 220 on substrate 101 is located at the top in the first channel hole 120 on substrate 101
Project the left side of the central point of 621a.
Comparative diagram 6C and 6D, after being performed etching to the bottom sidewall in the second channel hole 220, the bottom in the second channel hole 220
Projection 622b on substrate 101 is not moved and borehole enlargement relative to the projection 622a central point before its etching.After etching
The boundary of projection 622b of the bottom on substrate 101 in the second channel hole 220 have exceeded its corresponding first channel hole 120
The boundary of projection 621a of the top on substrate 101.At this point, the etching processing procedure carried out to the bottom sidewall in the second channel hole 220
The top sidewall in the first channel hole 120 can be influenced simultaneously, and the top sidewall in the first channel hole 120 can correspondingly be etched.It carves
The boundary of projection 621b of the top in the first channel hole 120 on substrate 101 is relative to the first ditch before etching processing procedure after erosion processing procedure
The boundary of projection 621a of the top in road hole 120 on substrate 101 expands.And etch the top in the first channel hole 120 after processing procedure
The boundary portion of the projection 622b of the boundary of projection 621b on substrate 101 and the bottom in the second channel hole 220 on substrate 101
Divide and is overlapped.
With reference to Fig. 6 D, after etching processing procedure, the center line at 120 top of the first channel hole is moved to the left, with first channel
The center line in hole 120 is no longer overlapped, and closer to the center line of 220 bottom of the second channel hole.The top in the first channel hole 120 exists
Top throwing on substrate 101 of the central point of projection 621b on substrate 101 relative to the first channel hole 120 before etching processing procedure
The central point of shadow 621a is moved to the left, and the center of the projection 622b closer to the bottom in the second channel hole 220 on substrate 101
Point.
Illustratively, the first channel hole with reference to shown in Fig. 3 and Fig. 4, other than 300 middle position of semiconductor structure
120 are in non-aligned state with corresponding second channel hole 220.Projection of the top in the first channel hole 120 on substrate 101
The positional relationship of projection 622a of the bottom in 621a and the second channel hole 220 on substrate 101 is as shown in Figure 6 C.In etching processing procedure
In, due to the boundary of the projection 622b of the bottom on substrate 101 in the second channel hole 220 after etching have exceeded its corresponding the
The top in one channel hole 120 on substrate 101 projection 621a boundary, it is centrally located other than the first channel hole 120
Top sidewall can correspondingly be etched.The top sidewall in the first channel hole 120 after being etched is relative to its bottom sidewall diameter
To outwardly protruding, as shown in Figure 4.
The array with multiple channel holes is considered, in one regional area, as shown in fig. 7, in addition to center
Outside first channel hole and the second channel hole, projection 611 of each first channel hole on substrate 101 and corresponding second channel hole exist
Projection 612 on substrate 101 is all offset, and only degree is different.After the second widened etching in channel hole, as shown in figure 8,
The center line in the second channel hole can be mobile to the center line in the first channel hole, so that the degrees of offset in two channel holes be made to be received
It is narrow.
Fig. 9 to Figure 11 is each before the channel hole reaming of the method for the formation three-dimensional storage of one embodiment of the invention etches
Angle schematic diagram.Fig. 9 to Figure 11 is before the channel hole reaming of the method for the formation three-dimensional storage of one embodiment of the invention etches
Each angle schematic diagram afterwards, wherein Fig. 9 is perspective view, and Figure 10 top view and upper right comer region eliminate the second storehouse to expose
One storehouse, Figure 11 are side sectional views.Structure shown in Fig. 9-11 is the structure after experienced step 530 shown in Fig. 5, with Fig. 3 institute
Show that the core region in structure is corresponding, therefore uses same reference numerals.It is appreciated that in the storehouse of three-dimensional storage
In structure, the second channel hole 220 in the first channel hole 120 and the second storehouse 210 in the first storehouse 110 can rectangular battle array
The formal distribution of column, but embodiments herein is not limited thereto.It is noted that Fig. 9 institute although not shown in Fig. 3
The epitaxial layer 121 shown, but can have this structure.Refering to what is shown in Fig. 10, in a regional area, in addition to the first of center
Outside channel hole and the second channel hole, each first channel hole 120 and corresponding second channel hole 220 are offset, and only degree is not
Together.The side sectional view of Figure 11 shows this offset.Figure 12 to Figure 14 is the formation three-dimensional storage of one embodiment of the invention
Method the reaming of channel hole etching front and back each angle schematic diagram, wherein Figure 12 is perspective view, Figure 13 top view and the upper right corner
Region eliminates the second storehouse to expose the first storehouse, and Figure 14 is side sectional view.Structure shown in Figure 12-14 is to experienced Fig. 5
Structure after shown step 540 is corresponding with the core region in structure shown in Fig. 4, therefore uses same reference numerals.
After the second widened etching in channel hole, as shown in figure 13, the center line in the second channel hole can be to the center in the first channel hole
Line is mobile, to keep the degrees of offset in two channel holes narrowed.Compare the bottom section in the second channel hole 220 of Figure 11
221 with the corresponding position of Figure 12 it is found that the direction (left side in figure) of the side wall in the second channel hole 220 towards offset is mobile, thus
Partial offset offset.
In some embodiments of the invention, above-mentioned etching processing procedure etches multiple second ditches using isotropic etching method
The top sidewall of the bottom sidewall in road hole 220 and the multiple first channel hole 120.
Isotropism refer to the physical property of the physics of object, chemistry etc. not with the characteristic of measurement direction change, i.e.,
Jobbie performance value measured by different directions is identical, also known as homogenieity.Such as all gas, liquid (liquid
Except crystalline substance) and noncrystalline object all show isotropism.Isotropic lithographic method can make each to channel hole side wall
The etching degree (depth) in a direction is identical.For example, in the embodiment shown in Fig. 6 A and 6B, to the bottom in the second channel hole 220
After portion's side wall performs etching, projection 612b of the bottom in the second channel hole 220 on substrate 101 and its projection 612a before etching
It is concentric circles.Similarly, in the embodiment shown in Fig. 6 C and 6D, projection of the bottom in the second channel hole 220 on substrate 101
622b is also concentric circles with its projection 622a before etching.
Optionally, above-mentioned isotropic etching method can be wet etching (WET Etch) and gas etching (dry method quarter
Erosion).Wherein, wet etching mainly occurs to chemically react and perform etching using chemical reagent with the material that is etched；Dry etching master
It to be performed etching using reaction gas with plasma.
By etching processing procedure above, so that the central point of projection 621b of the top in the first channel hole 120 on substrate 101
Closer to the second channel hole 220 bottom on substrate 101 projection 622b central point, reduce the first channel hole 120
The degrees of offset of center line and the center line in the second channel hole 220 on the extending direction of substrate 101, improves the first channel hole
The connection effect of the bottom in 120 top and the second channel hole 220, thus improve the first storehouse 110 and the second storehouse 210 it
Between alignment precision.
So far, the technique of the channel structure of three-dimensional storage is basically completed.After the completion of these techniques, along with routine
The three-dimensional storage of the embodiment of the present invention can be obtained in technique.For example, when three-dimensional storage is charge trapping memory
When, the first storehouse 110 and the second storehouse 210 in semiconductor structure 400 shown in Fig. 4 are dummy grid storehouse, first material layer
111 and 211 be dummy gate layer.It after step 540, further include by the first material layer 111 in the first storehouse and the second storehouse
Grid layer is replaced with 211.For another example, when three-dimensional storage is floating gate type memory, the first storehouse 110 and the 2nd 210 is grid
Pole storehouse, first material layer 111 and 211 are grid layer, are not required to the step of replacing by material after step 540.
Flow chart for example shown in fig. 5 has been used to be used to illustrate performed by method according to an embodiment of the present application herein
Operation.It should be understood that the operation of front not necessarily accurately carries out in sequence.On the contrary, can be according to inverted order or same
When handle various steps.Meanwhile or during other operations are added to these, or from these processes remove a certain step or number step
Operation.
In the context of the present invention, three-dimensional storage part can be 3D flash memory, such as 3D NAND or 3D NOR dodge
It deposits.Other details of three-dimensional storage part, such as wordline bonding pad, periphery interconnection etc., and the emphasis of non-present invention, herein no longer
Expansion description.
Above embodiments of the invention propose a kind of method for forming three-dimensional storage, the side of the formation three-dimensional storage
Method, which can solve between the channel hole of the adjacent storehouse of three-dimensional storage, has larger offset, helps to improve three-dimensional storage
The alignment precision of storehouse in device.
Another aspect of the present invention proposes a kind of three-dimensional storage, which can be to avoid the channel of adjacent storehouse
There are problems that larger offset, storehouse alignment precision with higher between hole.
The three-dimensional storage is described below with reference to Fig. 4.
In one embodiment of this invention, which can be semiconductor structure 400 for example shown in Fig. 4.It should
Three-dimensional storage includes substrate 101, the first storehouse 110 and the second storehouse 210 of the stacking on substrate 101.Positioned at first
Multiple first channels hole 120 in storehouse 110 and multiple second channels hole 220 in the second storehouse 210.
Wherein, the first storehouse 110 and the second storehouse 210 respectively include the grid layer at interval, are marked respectively in 111 and 211
The position of note.The bottom in every one second channel hole 220 is connected to the top in a first channel hole 120, wherein at least part
At least partly top sidewall in one channel hole 120 is projected radially outward relative to bottom sidewall.
In one embodiment of this invention, at least partly center line B in the second channel hole 220 is relative to corresponding first channel
There is offset on the extending direction (horizontal direction in figure) of substrate 101 in the center line A in hole 120.
In one embodiment of this invention, when the center line of 220 bottom of a certain second channel hole is relative to corresponding first ditch
When there is offset in the center line in road hole 120, the atop part in the specific first channel hole 120 on the extending direction of substrate 101
Side wall is projected radially outward relative to bottom sidewall, so that the center line at 120 top of corresponding first channel hole and corresponding first ditch
The center line in road hole 120 is not overlapped, and than the center line in corresponding first channel hole 120 closer to 220 bottom of a certain second channel hole
The center line in portion.
In one embodiment of this invention, every one second channel hole 220 is less than corresponding first channel hole in the aperture of bottom
120 top aperture.
In one embodiment of this invention, the bottom cross section in multiple second channels hole 220 is round, and when a certain the
The center line of two channel holes, 220 bottom is deposited on the extending direction of substrate 101 relative to the center line in corresponding first channel hole 120
In offset, the top cross-sectional in the first channel of correspondence hole 120 is non-circular.
In one embodiment of this invention, above-mentioned three-dimensional storage further includes more in multiple first channels hole 120
A first channel layer (not shown) and multiple second channel layer (not shown) in multiple second channels hole 220, it is each
Second channel layer corresponds to every one first channel layer.
Above embodiments of the invention propose a kind of three-dimensional storage, which can alleviate adjacent storehouse
There are problems that larger offset, storehouse alignment precision with higher between local channel hole.
The application has used particular words to describe embodiments herein.As " one embodiment ", " embodiment ",
And/or " some embodiments " means a certain feature relevant at least one embodiment of the application, structure or feature.Therefore, it answers
Emphasize and it is noted that " embodiment " or " one embodiment " that is referred to twice or repeatedly in this specification in different location or
" alternate embodiment " is not necessarily meant to refer to the same embodiment.In addition, certain in one or more embodiments of the application
Feature, structure or feature can carry out combination appropriate.
Although the present invention is described with reference to current specific embodiment, those of ordinary skill in the art
It should be appreciated that above embodiment is intended merely to illustrate the present invention, can also make in the case where no disengaging spirit of that invention
Various equivalent change or replacement out, therefore, as long as to the variation of above-described embodiment, change in spirit of the invention
Type will all be fallen in the range of following claims.
Claims (15)
1. a kind of method for forming three-dimensional storage, comprising the following steps:
Semiconductor structure is provided, the semiconductor structure have substrate, stacking on the substrate the first storehouse and
Across multiple first channels hole of first storehouse；
The second storehouse is formed on first storehouse；
It is formed across multiple second channels hole of second storehouse, the bottom in every one second channel hole and a first channel hole
Top connection；And
The bottom sidewall in the multiple second channel hole and the top sidewall at least partly first channel hole are etched, to expand
Aperture and at least partly first channel hole aperture at the top of the multiple second channel hole in the bottom.
2. method according to claim 2, which is characterized in that at least partly top in etching at least partly first channel hole
Portion's side wall, so that at least partly top sidewall is projected radially outward relative to the bottom sidewall in the first channel hole.
3. the method as described in claim 1, which is characterized in that at least partly the center line in second channel hole is relative to right
The center line in the first channel hole is answered to there is offset on the extending direction of the substrate.
4. according to the method described in claim 2, it is characterized in that, when the center line of a certain second channel hole bottom is relative to right
Answer the center line in the first channel hole when there is offset on the extending direction of the substrate, etching the multiple first channel hole
Atop part side wall, so that center line at the top of the first channel of correspondence hole and the center line in the corresponding first channel hole are not
It is overlapped, and than the center line in first channel of correspondence hole closer to the center line of a certain second channel hole bottom.
5. the method according to claim 1, wherein formed the multiple second channel hole the step of in, it is each
Second channel hole is less than corresponding first channel hole in the aperture at the top in the aperture of the bottom.
6. the method according to claim 1, wherein the semiconductor structure further includes filling the multiple first
The sacrificial layer in channel hole when being formed across multiple second channel holes of second storehouse, removes the multiple first channel hole
The sacrificial layer at top.
7. the method according to claim 1, wherein using isotropic etching method etching the multiple second
The top sidewall of the bottom sidewall in channel hole and at least partly first channel hole.
8. the method according to the description of claim 7 is characterized in that the isotropic etching method includes that wet etching is gentle
Body etching.
9. a kind of three-dimensional storage, comprising:
Substrate；
Between the first storehouse and the second storehouse of stacking on the substrate, first storehouse and the second storehouse respectively include
Every grid layer；
Multiple first channels hole in first storehouse；
Multiple second channels hole in second storehouse, the bottom in every one second channel hole and first channel hole
Top connection, wherein at least bottom side of at least partly top sidewall in part first channel hole relative to the first channel hole
Wall projects radially outward.
10. three-dimensional storage according to claim 9, which is characterized in that at least partly center in second channel hole
There is offset on the extending direction of the substrate relative to the center line in corresponding first channel hole in line.
11. three-dimensional storage according to claim 9, which is characterized in that when the center line of a certain second channel hole bottom
When there is offset in the center line relative to corresponding first channel hole, specific first channel on the extending direction of the substrate
The atop part side wall in hole is projected radially outward relative to bottom sidewall, so that the center line at the top of the first channel of correspondence hole
Be not overlapped with the center line in the corresponding first channel hole, and than the center line in first channel of correspondence hole closer to it is described certain
The center line in one second channel hole bottom.
12. three-dimensional storage according to claim 9, which is characterized in that hole of every one second channel hole in the bottom
Diameter is less than corresponding first channel hole in the aperture at the top.
13. three-dimensional storage according to claim 9, which is characterized in that
The bottom cross section in the multiple second channel hole is round；
And when the center line of a certain second channel hole bottom relative to corresponding first channel hole center line in the substrate
When there is offset on extending direction, the top cross-sectional in first channel of correspondence hole is round.
14. three-dimensional storage according to claim 9, which is characterized in that
The bottom cross section in the multiple second channel hole is round；
And when the center line of a certain second channel hole bottom relative to corresponding first channel hole center line in the substrate
When there is offset on extending direction, the top cross-sectional in first channel of correspondence hole is non-circular.
15. three-dimensional storage according to claim 9, which is characterized in that further include:
Multiple first channel layers in the multiple first channel hole；And
Multiple second channel layers in the multiple second channel hole, every one second channel layer correspond to every one first channel
Layer.
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| CN111403403A (en) * | 2020-03-31 | 2020-07-10 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
| CN111564448A (en) * | 2020-05-22 | 2020-08-21 | 长江存储科技有限责任公司 | Memory and forming method thereof |
| CN111653496A (en) * | 2020-06-11 | 2020-09-11 | 长江存储科技有限责任公司 | Method for detecting etching defects of channel structure |
| CN111276416B (en) * | 2020-02-20 | 2021-05-07 | 长江存储科技有限责任公司 | Method for detecting alignment of semiconductor structure alignment and method for manufacturing 3D memory device |
| CN113284842A (en) * | 2020-02-19 | 2021-08-20 | 爱思开海力士有限公司 | Semiconductor device and method for manufacturing semiconductor device |
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| CN109755252A (en) * | 2019-01-17 | 2019-05-14 | 长江存储科技有限责任公司 | A kind of memory device and its manufacturing method |
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| CN109712977A (en) * | 2019-01-15 | 2019-05-03 | 长江存储科技有限责任公司 | Three-dimensional storage part and preparation method thereof |
| CN109755252A (en) * | 2019-01-17 | 2019-05-14 | 长江存储科技有限责任公司 | A kind of memory device and its manufacturing method |
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| CN113284842A (en) * | 2020-02-19 | 2021-08-20 | 爱思开海力士有限公司 | Semiconductor device and method for manufacturing semiconductor device |
| CN113284842B (en) * | 2020-02-19 | 2024-03-01 | 爱思开海力士有限公司 | Semiconductor device and method for manufacturing semiconductor device |
| CN111276416B (en) * | 2020-02-20 | 2021-05-07 | 长江存储科技有限责任公司 | Method for detecting alignment of semiconductor structure alignment and method for manufacturing 3D memory device |
| CN111403403A (en) * | 2020-03-31 | 2020-07-10 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
| CN111403403B (en) * | 2020-03-31 | 2023-05-26 | 长江存储科技有限责任公司 | Three-dimensional memory and method for manufacturing the same |
| CN111564448A (en) * | 2020-05-22 | 2020-08-21 | 长江存储科技有限责任公司 | Memory and forming method thereof |
| CN111564448B (en) * | 2020-05-22 | 2021-09-28 | 长江存储科技有限责任公司 | Memory and forming method thereof |
| CN111653496A (en) * | 2020-06-11 | 2020-09-11 | 长江存储科技有限责任公司 | Method for detecting etching defects of channel structure |
| CN111653496B (en) * | 2020-06-11 | 2021-04-27 | 长江存储科技有限责任公司 | Method for detecting etching defects of channel structure |
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