CN109524410B

CN109524410B - Method for forming three-dimensional memory

Info

Publication number: CN109524410B
Application number: CN201811404852.1A
Authority: CN
Inventors: 肖莉红; 胡斌
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2018-11-23
Filing date: 2018-11-23
Publication date: 2020-07-28
Anticipated expiration: 2038-11-23
Also published as: CN109524410A

Abstract

The invention provides a method for forming a three-dimensional memory, which comprises the following steps: providing a semiconductor structure having a first substrate, a stacked first stack on the first substrate, and a plurality of first channel layers through the first stack; forming a conductive pattern layer by patterning a peeling layer, wherein the peeling layer is formed on the surface of a second substrate, the material of the peeling layer is monocrystalline silicon, and the conductive pattern layer comprises a plurality of mutually isolated intermediate conductive parts; bonding the conductive pattern layer with the first stack; forming a second stack overlying the conductive pattern layer; a plurality of second channel layers are formed through the second stack, each second channel layer electrically connected to a corresponding first channel layer through an intermediate conductive portion.

Description

Method for forming three-dimensional memory

Technical Field

The invention relates to the field of semiconductor manufacturing, in particular to a three-dimensional memory.

Background

In order to overcome the limitation of the two-dimensional memory device, a memory device having a three-dimensional (3D) structure, which increases integration density by arranging memory cells three-dimensionally over a substrate, has been developed and mass-produced in the industry.

In a three-dimensional memory device such as a 3D NAND flash memory, a memory array may include a core (core) region having a channel structure. The channel structure is formed in a channel hole that vertically penetrates through stacked layers (stacks) of the three-dimensional memory device. The channel holes of the stacked layers are typically formed by a single etch. However, to increase storage density and capacity, the number of layers (tier) of three-dimensional memories continues to increase, for example from 64 layers to 96, 128 or more layers. Under this trend, the single etching method is increasingly more expensive in processing cost and less efficient in processing capacity.

Some improved approaches attempt to divide the stack into multiple stacks (decks) stacked on top of each other. After forming a stack, the channel hole is etched and a channel structure is formed, and then the stack is continuously stacked. The stacks are connected by a common conductive portion therebetween. The material of the conductive portion is typically polysilicon. When the position or the shape of the conductive portion is not good, polysilicon inversion (inversion) failure is easily caused, and thus the resistance of the polysilicon is too high and the electron mobility is too low. This results in a decrease in channel current, which seriously affects the performance of programming/writing/erasing of the three-dimensional memory. To solve this problem, some further improved methods etch the lower channel hole after forming the lower stack, then stack the upper stack and etch the upper channel hole, and then form the channel structure filling the upper and lower channel holes. However, this approach can easily damage the stacked layers in the wet etching step. And when the upper and lower channel holes are misaligned, the stacked layers of the stack may be damaged by the plasma during the process of filling the channel structure. In addition, when the channel layer and the dielectric layer are filled, the holes are easily blocked, and an air gap is introduced to influence the performance of the memory cell.

Disclosure of Invention

The invention provides a three-dimensional memory to reduce resistance, improve electron mobility and improve electrical performance of the three-dimensional memory.

To solve the above technical problem, the present invention provides a three-dimensional memory, including: a semiconductor structure having a first substrate, a stacked first stack on the first substrate, and a plurality of first channel layers through the first stack; a conductive pattern layer bonded to the first stack, the conductive pattern layer including a plurality of intermediate conductive portions isolated from each other; a second stack overlying the conductive pattern layer; a plurality of second channel layers through the second stack, each second channel layer electrically connected to a corresponding first channel layer through an intermediate conductive portion; the conductive pattern layer is formed by patterning a stripping layer, the stripping layer is formed on the surface of the second substrate, and the material of the stripping layer is monocrystalline silicon.

In one embodiment of the invention, a lift-off layer is formed on a surface of a second substrate using a plasma implantation process.

In an embodiment of the invention, the plasma is a hydrogen plasma.

In an embodiment of the present invention, bottom portions of the plurality of second channel layers include a silicon epitaxial layer, at least a portion of the silicon epitaxial layer being embedded in the intermediate conductive portion.

In an embodiment of the present invention, the bottom of the first channel layer includes a silicon epitaxial layer, and the material of the silicon epitaxial layer at the bottom of the first channel layer and the second channel layer is silicon.

In an embodiment of the present invention, a center line of the second channel layer is aligned with a center line of the first channel layer.

In an embodiment of the present invention, a center line of the second channel layer is aligned with a center line of the first channel layer using an optical alignment method.

In an embodiment of the present invention, an interlayer insulating layer for isolating the plurality of intermediate conductive portions is formed between the plurality of intermediate conductive portions, and a material of the interlayer insulating layer is an insulating material.

In an embodiment of the present invention, the conductive pattern layer and the interlayer insulating layer are flat.

In an embodiment of the invention, the insulating material is silicon oxide.

Compared with the prior art, the invention has the following advantages: the invention provides a three-dimensional memory, wherein a stripping layer bonded with a first stack is covered on the surface of the first stack, and the stripping layer is made of monocrystalline silicon and has lower capture density and resistance, so that the electron mobility between the stacks can be improved, and the electrical performance of the memory is improved; in addition, the conductive pattern layer is formed by patterning the stripping layer, the material of which is also monocrystalline silicon, and a second silicon epitaxial layer can be directly formed on the conductive pattern layer, so that the memory cell has a more convergent threshold voltage (V)_t) Distributing; the stripping layer is formed by stripping the second substrate, and the second substrate can be reused, so that the process cost of the silicon wafer is reduced.

Drawings

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:

fig. 1 is a schematic diagram of a structure of a channel formed in a three-dimensional memory in a divided manner.

Fig. 2 is a schematic diagram of a single-formed channel structure in a three-dimensional memory.

Fig. 3 is a flow chart of a method of forming a three-dimensional memory according to an embodiment of the invention.

Fig. 4A-4E are cross-sectional schematic views of an exemplary process of a method of forming a three-dimensional memory according to an embodiment of the invention.

Fig. 5 is a flowchart of a method of covering a surface of a first stack with a release layer bonded to the first stack according to an embodiment of the present invention.

Fig. 6A-6E are schematic cross-sectional views of an exemplary process of a method of covering a surface of a first stack with a release layer bonded to the first stack according to an embodiment of the present invention.

FIG. 7 is a cross-sectional view of a three-dimensional memory according to an embodiment of the invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.

As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.

In describing the embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary words "below" and "beneath" can encompass both an orientation of up and down. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein should be interpreted accordingly. Further, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.

It will be understood that when an element is referred to as being "on," "connected to," "coupled to" or "contacting" another element, it can be directly on, connected or coupled to, or contacting the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to" or "directly contacting" another element, there are no intervening elements present. Similarly, when a first component is said to be "in electrical contact with" or "electrically coupled to" a second component, there is an electrical path between the first component and the second component that allows current to flow. The electrical path may include capacitors, coupled inductors, and/or other components that allow current to flow even without direct contact between the conductive components.

The stacked layers (stack) of the three-dimensional memory are formed by stacking a plurality of stacks (deck), and the channel layers between adjacent stacks are electrically connected. The channel layer manufactured by the conventional method has poor shape at the position between stacks, and the conductive capability between the channel layers is easily reduced.

Fig. 1 is a schematic diagram of a structure of a trench formed in a three-dimensional memory in a plurality of times (a plurality of times of etching and filling): DCF (Dual Cell formation), namely, for the channel holes of the multilayer stack, after the etching and filling of the first channel hole are finished, forming a conductive pattern between stacks, then etching and filling of the second channel hole are carried out, and the like, and stacking are carried out layer by layer. As shown in fig. 1, three-dimensional memory 100 may include a substrate 11, a lower layer stack 12, and an upper layer stack 13 in a core region. The lower layer stack 12 and the upper layer stack 13 are stacked on the substrate 11 in this order. The lower layer stack 12 has a plurality of first channel holes 12a perpendicular to the substrate, in which a first memory layer 12b and a first channel layer 12c are located. The upper layer stack 13 has a plurality of second channel holes 13a aligned with the first channel holes 12a, and a second memory layer 13b and a second channel layer 13c therein. Here, the

memory layer

12b or 13b may include a blocking layer, a charge trapping layer, and a tunneling layer. A conductive portion 14a is provided in the stack intermediate layer 14 between the lower layer stack 12 and the upper layer stack 13, and connects the first channel layer 12b and the second channel layer 13 b. The lower stack 12 and the upper stack 13 of the three-dimensional memory 100 may be sequentially fabricated, so that the first and

second channel holes

12a and 13a and the channel structure thereof may be formed in two times. Thus, the difficulty of the channel process is reduced. However, in the process of forming the upper layer stack 13, a part of the second memory layer 13b may also be formed on the conductive portion 14a, resulting in the second memory layer 13b having a non-conductive projection 13d on the conductive portion 14 a. When a voltage is applied to the gate electrode, the convex portion causes the portion of the intermediate conductive portion serving as a conductive channel to fail to invert, thereby failing to electrically conduct the upper and lower first channel holes 12a and the second channel hole 13 a. However, removing the protruding portion 13d risks damaging the topography of the conductive portion 14a, and after additional complicated process steps, the topography of the bottom of the second channel hole is difficult to control, which affects Cell memory performance.

Fig. 2 is a schematic diagram of a structure of a once-formed (once-filled by multiple etching) trench in a three-dimensional memory: scf (single Cell formation), i.e. for the channel holes of the multi-layer stack, the first channel hole is etched separately and filled with a temporary sacrificial layer, then the inter-stack conductive pattern is formed, the second channel hole is etched, and after the sacrificial layer is removed, the first and second channel holes are filled simultaneously. Referring to fig. 2, a three-dimensional memory 200 may include a substrate 21, a lower layer stack 22, and an upper layer stack 23 in a core region. The lower layer stack 22 and the upper layer stack 23 are sequentially stacked on the substrate 21. The lower layer stack 22 has a plurality of first channel holes 22a perpendicular to the substrate, and the upper layer stack 23 has a plurality of second channel holes 23a substantially aligned with the first channel holes 22 a. The memory 200 also has a memory layer 24a and a channel layer 24b penetrating from the first channel hole 22a to the second channel hole 23 a. Here, the memory layer 24a may include a blocking layer, a charge trapping layer, and a tunneling layer. This three-dimensional memory 100 may form a channel structure at a time when the first channel hole 22a and the second channel hole 23a are formed. In this way, the problem of conductive inversion failure as in fig. 1 can be avoided. The stacked layers at stack location A, B are easily damaged during the formation of the channel structure. And when the upper and

lower channel holes

22a, 23a are misaligned as shown in fig. 2, the plasma during the process of filling the channel structure may also damage the stack layers at stack location C, D. In addition, filling the channel layer 24b and the dielectric layer 24c may also easily result in blocking of the channel hole, especially at the stack junction, thereby resulting in inefficient filling of the underlying first channel hole, including, for example, the barrier layer, the charge trapping layer, the tunneling layer, and the dielectric layer.

Embodiments of the present invention describe a method of forming a three-dimensional memory that may overcome the above-described problems in the conventional multi-formation or one-formation multi-layer stacked three-dimensional memory. Fig. 3 is a flow chart of a method of forming a three-dimensional memory according to an embodiment of the invention. Fig. 4A-4E are cross-sectional schematic views of an exemplary process of a method of forming a three-dimensional memory according to an embodiment of the invention. The method of forming the three-dimensional memory of the present embodiment is described below with reference to fig. 3 to 4E.

In step 302, a semiconductor structure is provided.

The semiconductor structure is to be used in a subsequent process to ultimately form at least a portion of a three-dimensional memory device. The semiconductor structure may include an array region, which may include a core region and a word line connection region. The core region may have a substrate, a first stack of stacks located on the substrate, and a first vertical structure passing through the first stack, as viewed in a vertical direction. The first vertical structure includes a first channel layer that may be electrically interconnected with other conductive portions. In the semiconductor structure illustrated in fig. 4A, the semiconductor structure 400a may include a substrate 401, a first stack 410 on the substrate 401. The first stack 410 may be a stack in which first material layers 411 and second material layers 412 are alternately stacked. The first material layer 411 may be a gate layer or a dummy gate layer. The first stack 410 has a first vertical structure disposed therein perpendicular to the surface of the substrate 401, including a first channel layer 413. It is noted that the first vertical structure may also be a dummy channel structure, and the internal structure thereof may be the same as or different from the channel structure for the core region.

The first vertical structure may further include a blocking layer, a charge trapping layer, and a tunneling layer disposed from the outside to the inside between the first channel layer 413 and the first channel hole in which the first vertical structure is located. These layers constitute a first memory layer 414. The memory layer 414 may not be a dielectric layer disposed in the first channel hole, but a floating gate structure disposed in a lateral trench of the first material layer 411 adjacent to the first channel hole. Some example details of the first memory layer 414 will be described later.

In an embodiment of the present invention, the substrate 401 is made of silicon, for example, the first material layer 411 and the second material layer 412 are made of a combination of silicon nitride and silicon oxide, for example, the first stack 410 may be formed by alternately depositing silicon nitride and silicon oxide on the substrate 401 by Chemical Vapor Deposition (CVD), atomic layer deposition (a L D), or other suitable deposition methods.

The bottom of the first vertical structure may have a silicon epitaxial layer 413 a. The material of the silicon epitaxial layer 413a is, for example, silicon.

Although exemplary configurations of the initial semiconductor structure are described herein, it will be appreciated that one or more features may be omitted, substituted, or added to the semiconductor structure. For example, various well regions may be formed in the substrate as desired; a filler layer 415 may also be disposed within the first channel layer 413. The fill layer 415 may act as a support. The material of the fill layer 415 may be silicon oxide. The filling layer 415 may be solid or hollow. In addition, the materials of the various layers illustrated are merely exemplary, and for example, substrate 401 may also be other silicon-containing substrates, such as SOI (silicon on insulator), SiGe, Si: C, and the like.

In step 304, a surface of the first stack is covered with a release layer bonded to the first stack.

In this step, a peeling layer covering the first stack is formed on a surface of the first stack, the peeling layer being bonded to the first stack. Here, the material of the peeling layer is single crystal silicon. Compared with polysilicon, single crystal silicon has lower capture density and resistance, and can improve electron mobility between stacks, thereby improving read-write performance of the memory. The release layer may be formed by peeling from another material layer, and is therefore referred to as a release layer. The method of forming the peeling layer covering and bonding to the first stack may be a Smart-cut method (detailed process of which will be described later).

In the cross-sectional view of the semiconductor structure illustrated in fig. 4B, the surface of the first stack 410 of the semiconductor structure 400B is formed with a peeling layer 420 covering the first stack 410. The release layer 420 is bonded to the first stack 410. The material of the peeling layer 420 is single crystal silicon, which has lower trapping density and resistance, and can improve the electron mobility between stacks, thereby improving the electrical performance of the memory.

In step 306, the patterned lift-off layer forms a conductive pattern layer.

The step of patterning the lift-off layer to form the conductive pattern layer may further include filling an insulating material between the plurality of intermediate conductive portions to form an interlayer insulating layer (Inter-L a layer Dielectric, I L D) that separates the plurality of intermediate conductive portions.

In the cross-sectional view of the semiconductor structure illustrated in fig. 4C, a conductive pattern layer 421 is formed on the surface of the first stack 410 of the semiconductor structure 400C. The conductive pattern layer 421 includes a plurality of intermediate conductive portions 421a isolated from each other. The step of patterning the peeling layer 420 to form the conductive pattern layer 421 may include: the surface of the peeling layer 420 is covered with an etching stopper layer, and a pattern on the etching stopper layer can be transferred onto the peeling layer 420 by exposure, photolithography, and etching processes, thereby forming the conductive pattern layer 421. Wherein the lift-off layer 420 not covered by the etch stop layer is etched such that the top of the first stack 410 is exposed, and the lift-off layer 420 covered by the etch stop layer is not etched, forming a plurality of intermediate conductive portions 421 a. The step of patterning the peeling layer to form the conductive pattern layer 421 may further include: an insulating material is filled between the plurality of intermediate conductive portions 421a to form an interlayer insulating layer 422 that isolates the plurality of intermediate conductive portions. The method of filling the insulating material may be to deposit the insulating material and then perform chemical mechanical planarization. The insulating material may be, for example, silicon oxide.

In step 308, a second stack is formed overlying the conductive pattern layer.

In this step, a second stack is formed so as to constitute a stacked layer (stack) with the first stack. It is noted that the second stack is not limited to one layer stack, but may be other number of stacks larger than one layer, such as two, three or more layers.

The structure of the second stack may be similar to the structure of the first stack. For example, the second stack comprises a first material layer and a second material layer stacked on top of each other. It will be appreciated that the second stack may also differ from the first stack in structure, material, etc.

In the cross-sectional view of the semiconductor structure illustrated in fig. 4D, a second stack 430 is formed over the first stack 410 of the semiconductor structure 500D. The second stack 430 is a stack of first material layers 431 and second material layers 432 alternately stacked.

At step 310, a plurality of second channel layers are formed through the second stack. Here, each second channel layer is connected to the corresponding first channel layer through one of the intermediate conductive portions. The step of forming a plurality of second channel layers through the second stack may further include forming a silicon epitaxial layer at a bottom of the second channel layers, at least a portion of the silicon epitaxial layer being embedded in the intermediate conductive portion. In a preferred embodiment of the present invention, when a plurality of second channel layers passing through the second stack are formed, the center lines of the second channel layers and the center line of the first channel layer are aligned. For example, an optical alignment method may be employed to align a center line of the second channel layer with a center line of the first channel layer.

Here, a plurality of second channel holes perpendicular to the surface of the substrate may be formed in the second stack, the second channel holes corresponding to the first channel holes. The second channel hole is used to accommodate a storage element to be subsequently formed.

A photolithography process may be used to form a second channel hole in the second stack of the core region. For example, the core region may be exposed using a photomask and the second trench hole may be formed by a corresponding etch. The photomask used herein may be the same photomask used to form the first channel hole.

In the cross-sectional view of the semiconductor structure illustrated in fig. 4E, a blocking layer, a charge trapping layer, and a tunneling layer are formed along the sidewalls thereof from the outside to the inside within the second channel hole 433 of the semiconductor structure 400E. These layers constitute a second memory layer 434. In addition, a vertical second channel layer 435 is formed in the second memory layer 434. The second channel layer 435 extends to the bottom of the second channel hole 433. The bottom of the second channel hole 433 is formed with a silicon epitaxial layer 436, and at least a portion of the silicon epitaxial layer 436 is embedded in the intermediate conductive portion 421a so as to be connected to the intermediate conductive portion 421 a.

Alternatively, when a plurality of second channel layers 433 passing through the second stack 430 are formed, the center line of the second channel layers 433 is aligned with the center line of the first channel layer 413. For example, the center line of the second channel layer 433 and the center line of the first channel layer 413 may be aligned using an optical alignment method.

Optionally, a filler layer 437 may be formed within the second channel layer 435. The filler layer 437 can function as a support. The filler layer 437 may be solid or hollow.

Here, other details of the second memory layer 434, the second channel layer 435, and the filler layer 437 may refer to the first memory layer 414, the first channel layer 415, and the filler layer 416 described in step 402, and are not expanded herein.

So far, the process of the channel structure of the three-dimensional memory is basically finished. After the processes are completed, a conventional process is added to obtain the three-dimensional memory. For example, when the three-dimensional memory is a charge trapping memory, the first stack 410 and the second stack 430 in the semiconductor structure 400E shown in fig. 4E are dummy gate stacks, and the first material layers 411 and 431 are dummy gate layers, then after step 408, replacing the first material layers 411 and 431 in the first stack and the second stack with gate layers is further included. For another example, when the three-dimensional memory is a floating gate memory, the first stack 410 and the second stack 430 are gate stacks, and the first material layers 411 and 431 in the first stack and the second stack are gate layers, there is no need to perform a material replacement step after step 408.

Flow charts are used herein to illustrate operations performed by methods according to embodiments of the present application. It should be understood that the preceding operations are not necessarily performed in the exact order in which they are performed. Rather, various steps may be processed in reverse order or simultaneously. Meanwhile, other operations are added to or removed from these processes.

The invention provides a method for forming a three-dimensional memory, which comprises covering a peeling layer bonded with a first stack on the surface of the first stack, wherein the material of the peeling layer is monocrystalline silicon,the memory has lower electron capture defect state density and resistance, and can improve the electron mobility between stacks, thereby improving the electrical property of the memory; in addition, the conductive pattern layer is formed by patterning the stripping layer, the material of which is also monocrystalline silicon, and a second silicon epitaxial layer can be directly formed on the conductive pattern layer, so that the memory cell has a more convergent threshold voltage (V)_t) Distributing; the stripping layer is formed by stripping the second substrate, and the second substrate can be reused, so that the process cost of the silicon wafer is reduced.

Fig. 5 is a flowchart of a method of covering a surface of a first stack with a release layer bonded to the first stack according to an embodiment of the present invention. Fig. 6A-6E are schematic cross-sectional views of an exemplary process of a method of covering a surface of a first stack with a release layer bonded to the first stack according to an embodiment of the present invention. A method of this embodiment of covering the surface of the first stack with the peeling layer bonded to the first stack is described below with reference to fig. 5 to 6E.

In step 502, a release layer is formed on a surface of a second substrate.

In this step, a peeling layer is formed on the surface of the second substrate. A peeling layer may be formed on a surface of the second substrate by a plasma implantation process. The plasma in the plasma implantation process may be a hydrogen plasma, or an isotope of hydrogen, such as a deuterium plasma, a tritium plasma, or other plasma or other activated particle (radial) state that does not damage the crystalline structure of the silicon atoms nor affect the electrical properties of the memory. Taking hydrogen plasma as an example, hydrogen plasma includes hydrogen atoms, hydrogen molecules, hydrogen ions, charged hydrogen particles, clusters, and the like, and the whole is in a plasma state. The thickness of the release layer formed during plasma implantation can be controlled by adjusting the implantation energy.

In the cross-sectional view of the semiconductor structure illustrated in fig. 6A, plasma is implanted at the surface of the second substrate 601. The plasma may be a hydrogen plasma or an isotope of hydrogen, such as a deuterium plasma, a tritium plasma, or other plasma or other activated particle (radial) state that does not damage the crystalline structure of the silicon atoms nor affect the electrical properties of the memory. Taking hydrogen plasma as an example, hydrogen plasma includes hydrogen atoms, hydrogen molecules, hydrogen ions, charged hydrogen particles, clusters, and the like, and the whole is in a plasma state. In the cross-sectional view of the semiconductor structure illustrated in fig. 6B, after the plasma implantation process, a peeling layer 602 is formed on the surface of the second substrate 601. The thickness of the peeling layer 602 formed during plasma implantation can be controlled by adjusting the implantation energy.

In step 504, the second substrate is bonded to the first stack.

In this step, a second substrate is bonded to the first stack, the side of the second substrate having the peeling layer contacting the first stack. The method of bonding the second substrate and the first stack may be to turn the second substrate over, bond the turned second substrate and the first stack with the first stack being located below the second substrate, or to turn the first stack over, bond the turned first stack and the second substrate with the first stack being located above the second substrate.

In the cross-sectional view of the semiconductor structure illustrated in fig. 6C, the side of the second substrate 601 having the peeling layer 602 contacts the first stack 610. The second substrate 602 is flipped over and the flipped second substrate 602 is bonded to the first stack 610, the first stack 610 being located below the second substrate 601. In the cross-sectional view of the semiconductor structure illustrated in fig. 6C-1, the side of the second substrate 601 having the peeling layer 602 contacts the first stack 610. The first stack 610 is flipped over, the flipped first stack 610 is bonded to the second substrate 602, and the first stack 610 is located above the second substrate 601.

In step 506, the lift-off layer is separated from the second substrate.

In this step, the peeling layer implanted with plasma has a different property from the other portion of the second substrate, and the peeling layer can be separated from the second substrate by the difference in property, thereby forming a peeling layer bonded to the first stack. In subsequent processes, some high temperature processes volatilize plasma in the lift-off layer, which is a single crystal silicon material that does not contain plasma components.

In the cross-sectional views of the semiconductor structures illustrated in fig. 6D and 6E, the peeling layer 602 implanted with plasma has different properties from other portions of the second substrate 601, and the peeling layer 602 can be separated from the second substrate 601 by the difference in properties, thereby forming the peeling layer 602 bonded to the first stack 610. In subsequent processes, some high temperature processes volatilize plasma in the exfoliation layer 602, and the material of the exfoliation layer 602 is single crystal silicon and does not include the plasma components implanted during the formation of the exfoliation layer, thereby not affecting device performance.

FIG. 7 is a cross-sectional view of a three-dimensional memory according to an embodiment of the invention. The three-dimensional memory may be formed by the method described above. The three-dimensional memory includes a semiconductor structure 700. Referring to fig. 7, a semiconductor structure 700 has a first substrate 701, a stacked first stack 710 on the first substrate, and a plurality of first channel layers 711 passing through the first stack 710. A conductive pattern layer 720 bonded to the first stack 710, the conductive pattern layer 720 including a plurality of intermediate conductive portions 721 isolated from each other. A second stack 730 overlying the conductive pattern layer 720. Each of the second channel layers 731 is electrically connected to the corresponding first channel layer 711 through the intermediate conductive portion 721, passing through the plurality of second channel layers 731 of the second stack 730. The conductive pattern layer 720 is formed by patterning a peeling layer, the peeling layer is formed on the surface of the second substrate, and the material of the peeling layer is monocrystalline silicon.

In one embodiment of the invention, a lift-off layer is formed on a surface of a second substrate using a plasma implantation process. In one embodiment of the present invention, the plasma is a hydrogen plasma. In an embodiment of the present invention, the bottom portions of the plurality of second channel layers 731 include a silicon epitaxial layer 732, and at least a portion of the silicon epitaxial layer 732 is embedded in the intermediate conductive portion 721. In an embodiment of the present invention, a center line of the second channel layer 731 is aligned with a center line of the first channel layer 711.

The invention provides a three-dimensional memory, wherein a conductive pattern layer bonded with a first stack is covered on the surface of the first stack, the material of the conductive pattern layer is monocrystalline silicon, the conductive pattern layer has lower trapping density and resistance, the electron mobility between the stacks can be improved, and a memory cell has more convergent threshold voltage (V)_t) Distributing; in addition, the conductive pattern layer may be formedThe silicon epitaxial layer of the second stack is directly formed, so that the conductivity is further improved.

This application uses specific words to describe embodiments of the application. Reference throughout this specification to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic described in connection with at least one embodiment of the present application is included in at least one embodiment of the present application. Therefore, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, some features, structures, or characteristics of one or more embodiments of the present application may be combined as appropriate.

Although the present invention has been described with reference to the present specific embodiments, it will be appreciated by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes and substitutions may be made without departing from the spirit of the invention, and therefore, it is intended that all changes and modifications to the above embodiments within the spirit and scope of the present invention be covered by the appended claims.

Claims

1. A method of forming a three-dimensional memory, comprising:

providing a semiconductor structure having a first substrate, a stacked first stack on the first substrate, and a plurality of first channel layers through the first stack;

forming a conductive pattern layer by patterning a peeling layer, wherein the peeling layer is formed on the surface of a second substrate, the material of the peeling layer is monocrystalline silicon, and the conductive pattern layer comprises a plurality of mutually isolated intermediate conductive parts;

bonding the conductive pattern layer with the first stack;

forming a second stack overlying the conductive pattern layer;

a plurality of second channel layers are formed through the second stack, each second channel layer electrically connected to a corresponding first channel layer through an intermediate conductive portion.

2. The method of claim 1, wherein a release layer is formed on the surface of the second substrate using a plasma implantation process.

3. The method of claim 2, wherein the plasma is a hydrogen plasma.

4. The method of claim 1, wherein a bottom portion of the plurality of second channel layers comprises a silicon epitaxial layer, at least a portion of the silicon epitaxial layer being embedded in the intermediate conductive portion.

5. The method of claim 4, wherein the bottom of the first channel layer comprises a silicon epitaxial layer, and the material of the silicon epitaxial layer at the bottom of the first channel layer and the second channel layer is silicon.

6. The method of claim 1, wherein a centerline of the second channel layer is aligned with a centerline of the first channel layer.

7. The method of claim 6, wherein a center line of the second channel layer is aligned with a center line of the first channel layer using an optical alignment method.

8. The method according to claim 1, wherein an interlayer insulating layer that isolates the plurality of intermediate conductive portions is formed between the plurality of intermediate conductive portions, and a material of the interlayer insulating layer is an insulating material.

9. The method according to claim 8, wherein the conductive pattern layer and the interlayer insulating layer are flat.

10. The method of claim 8, wherein the insulating material is silicon oxide.