CN107731849A - The preparation method and 3D nand flash memories in 3D nand flash memory raceway grooves hole - Google Patents
The preparation method and 3D nand flash memories in 3D nand flash memory raceway grooves hole Download PDFInfo
- Publication number
- CN107731849A CN107731849A CN201710740880.XA CN201710740880A CN107731849A CN 107731849 A CN107731849 A CN 107731849A CN 201710740880 A CN201710740880 A CN 201710740880A CN 107731849 A CN107731849 A CN 107731849A
- Authority
- CN
- China
- Prior art keywords
- layer
- polysilicon
- deposition
- raceway groove
- oxidation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
Abstract
The invention provides the preparation method in 3D nand flash memory raceway grooves hole and 3D nand flash memories, methods described to include：Deposited in the raceway groove hole of substrate stacked structure, form barrier layer, accumulation layer and tunnel layer respectively；Then the deposition of first layer polysilicon layer is carried out；Low temperature free-radical oxidation is carried out to the polysilicon layer of first layer deposition, to form oxidation masking layer；Oxidation masking layer, first layer polysilicon layer, tunnel layer, accumulation layer and barrier layer to raceway groove bottom hole portion perform etching, until spilling silicon epitaxy layer simultaneously over etching silicon epitaxy layer certain depth；Oxidation masking layer is removed, and carries out prerinse before second layer polysilicon deposition；Carry out the deposition of second layer polysilicon layer.Oxidation masking layer is formed as a result of low temperature free-radical oxidation technique and the prerinse before second layer polysilicon deposition is carried out using diluted hydrofluoric acid, save polysilicon and return quarter step, formation uniformity is good, the raceway groove hole polysilicon layer of high quality, and cost is low, reliability is high.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of preparation side of 3D nand flash memories raceway groove hole polysilicon
Method.
Background technology
In order to improve the density of memory device, industry is directed to the memory cell that research and development reduce two-dimensional arrangement extensively
Size method.With the memory cell dimensions continual reductions of two-dimentional (2D) memory device, signal conflict and interference can show
Increase is write, so that being difficult to carry out multi-level-cell (MLC) operation.In order to overcome the limitation of 2D memory devices, there is three-dimensional
The research that memory device this year of (3D) structure comes gradually heats up, by by memory cell be three-dimensionally disposed in substrate come
Improve integration density.
In the making of 3D nand flash memories, it is related to the preparation method of raceway groove hole and each functional layer of side wall, specifically, existing skill
The method that raceway groove hole side wall functional layer is made in art refer to Fig. 1 a-1e：
S1：Such as Fig. 1 a, in raceway groove hole, side wall forms stacked structure, and the stacked structure is ONO structure (oxide skin(coating) 1-1-
Nitride layer 1-2- oxide skin(coating) 1-3)；Prepared by the ONO structure generally use atomic layer deposition method (ALD), then first layer
Polysilicon deposition 1-4；
S2：Such as Fig. 1 b, the wet method of first layer polysilicon, which is returned, carves；Generally use alkalescence standard cleaning (SC1) cuts down first layer
Polysilicon 1-4；
S3：Such as Fig. 1 c, masking barrier oxide (CAP Buffer Oxide) 1-5 depositions, the step generally use atom
Layer sedimentation (ALD)；Purpose is for the polysilicon structure of subsequent etch protective side wall deposition；
S4：Such as Fig. 1 d, the SONO layers etching in raceway groove bottom hole portion is carried out, and carries out wet stripping (wet strip) barrier oxidation
Thing 1-5；And carry out prerinse before second layer polysilicon deposition；
S5：Such as Fig. 1 e, the deposition of second layer polysilicon, first layer is sunk with the polysilicon layer 1-6 for causing the second layer to deposit
Long-pending polysilicon layer 1-4 connects with silicon epitaxy layer.
1) following defect still, in the above-mentioned methods, be present：Polysilicon wet method in S2 steps is returned in carving technology, difficult
To control the uniformity of polysilicon thickness, as shown in Fig. 2 photo, the thickness of raceway groove hole periphery polysilicon is in circumference four direction
Thickness be respectively 6.66 (nm), 6.84 (nm), 7.02 (nm) and 7.2 (nm), differ up to 8% or so, and polysilicon easily by
Damage, so as to which the formation to product impacts.Barrier oxidation prepared by the atomic layer deposition method (ALD) used in S3 steps
Nitride layer is not fine and close enough, produces particle and hole the problem of due to technique itself in sedimentary, and cost is high, and deposition efficiency is low
Under；The bottom disconnection problem of polysilicon is easily formed in subsequent technique is integrated, as best shown in figures 3 a and 3b, it is seen then that the second layer sinks
Long-pending polysilicon layer 1-6 bottoms do not connect, by figure it can also be seen that the polysilicon of second layer deposition is in diverse location thickness
It is inconsistent, it is maximum in the thickness of silicon epitaxy layer deposition, in the thickness minimum (T of ONO structure part depositionSi>Ta-Si>TONO)。
The content of the invention
For drawbacks described above of the prior art, it is an object of the invention to provide a kind of 3D nand flash memories raceway groove hole
Preparation method, this process simplify technological process of the prior art, and it can form that uniformity is good, and the raceway groove hole of high quality is more
The articulamentum of crystal silicon and bottom silicon epitaxy layer.So as to improve the performance of 3D nand flash memories.
To achieve these goals, the technical solution adopted by the present invention is as follows：
A kind of preparation method in 3D nand flash memories raceway groove hole, methods described comprise the following steps：
There is provided one has the substrate stacked structure formed with raceway groove hole；
Deposited in the raceway groove hole, form barrier layer, accumulation layer and tunnel layer respectively；
Carry out the deposition of first layer polysilicon layer；
Low temperature free-radical oxidation (Low temperature radical are carried out to the polysilicon layer of first layer deposition
Oxidation), to form oxidation masking layer；
Oxidation masking layer, first layer polysilicon layer, tunnel layer, accumulation layer and barrier layer to raceway groove bottom hole portion are carved
Erosion, until spilling silicon epitaxy layer (SEG) and the over etching silicon epitaxy layer certain depth；
Oxidation masking layer is removed, and carries out prerinse before second layer polysilicon deposition；
Carry out the deposition of second layer polysilicon layer.
Further, the offer one has the substrate stacked structure formed with raceway groove hole with the following method：
Substrate is provided, interlayer dielectric layer and sacrificial dielectric layer of the substrate surface formed with multi-layer intercrossed stacking form lining
Bottom stacked structure, the sacrificial dielectric layer are formed between adjacent interlayer dielectric layer；The interlayer dielectric layer is silicon oxide layer,
The sacrificial dielectric layer is silicon nitride layer；
The substrate stacked structure is etched, etches the interlayer dielectric layer and sacrificial dielectric layer to form raceway groove hole, it is described
Raceway groove passes to the substrate and forms the silicon groove of certain depth；
Silicon epitaxy layer is formed, silicon is carried out at the silicon groove is epitaxially-formed silicon epitaxy layer.
Further, the barrier layer, accumulation layer and tunnel layer are oxidenitride oxide structure (ONO)；
Further, the oxidenitride oxide structure (ONO) is using atomic layer deposition method (ALD) formation.
Further, the oxidenitride oxide structure (ONO) is the oxide-nitride-oxide knot
Structure (ONO)
Further, the first layer polysilicon layer is using Low Pressure Chemical Vapor Deposition (LPCVD) formation.
Further, the temperature of the low temperature free-radical oxidation is less than 530 DEG C.
Further, the removal oxidation masking layer is carried out using acid standard cleaning (SC2).
Further, prerinse is carried out using diluted hydrofluoric acid (DHF) before the second layer polysilicon deposition.
It is a further object to provide a kind of 3D nand flash memories prepared using the above method.
Compared with prior art, the beneficial effects are mainly as follows：
First, the present invention forms masking oxidation using the low temperature free-radical oxidation technique oxidation polysilicon layer less than 530 DEG C
Layer, uniform in shaping is good, also, low-temperature oxidation can prevent polysilicon crystal, compared to conventional atomic layer cvd silicon oxide more
Densification, without particle and hole.
Secondly, the present invention carries out the prerinse before second layer polysilicon deposition using diluted hydrofluoric acid, can remove polysilicon
The SiO that surface is generated by low temperature free-radical oxidation2Layer, because diluted hydrofluoric acid is to polysilicon and SiO2, can with higher selection ratio
With the SiO that goes out2Without damaging polysilicon, compared to traditional alkaline standard cleaning (SC1), it is easier to stability contorting polysilicon
Uniformity, and prevent the damage of polysilicon；And diluted hydrofluoric acid cleaning can ensure that first layer polysilicon layer and the second layer are more
Interface cleanness between crystal silicon layer, there is no interface SiO2The presence of layer.
Again, the metal of deposition layer surface can be removed using acid standard cleaning, and can be with to the ONO structure of bottom
The processing at interface is carried out, is advantageous to the deposition of second layer polysilicon deposition.
Finally, comprehensive to use above-mentioned technology, the present invention can save polysilicon and return quarter step, and formation uniformity is good, high-quality
The raceway groove hole polysilicon layer of amount, and cost is low, and reliability is high.
Brief description of the drawings
By reading the detailed description of hereafter preferred embodiment, it is various other the advantages of and benefit it is common for this area
Technical staff will be clear understanding.Accompanying drawing is only used for showing the purpose of preferred embodiment, and is not considered as to the present invention
Limitation.And in whole accompanying drawing, identical part is denoted by the same reference numerals.In the accompanying drawings：
Fig. 1 a-1e are the method for making raceway groove hole side wall functional layer in the prior art；
Fig. 2, in the prior art raceway groove hole periphery polysilicon inequality microphoto.
Fig. 3 a-3b, polysilicon bottom, which breaks, in the prior art schemes, and wherein 3a is schematic diagram, and 3b is microphoto.
Fig. 4 a-4f are the process chart of raceway groove hole preparation method in the embodiment of the present invention 1.
Embodiment
The illustrative embodiments of the disclosure are more fully described below with reference to accompanying drawings.Although this public affairs is shown in accompanying drawing
The illustrative embodiments opened, it being understood, however, that may be realized in various forms the disclosure without the reality that should be illustrated here
The mode of applying is limited.Conversely, there is provided these embodiments are to be able to be best understood from the disclosure, and can be by this public affairs
The scope opened completely is communicated to those skilled in the art.
For clarity, whole features of practical embodiments are not described.In the following description, it is not described in detail known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
In hair, it is necessary to a large amount of implementation details are made to realize the specific objective of developer, such as according to relevant system or relevant business
Limitation, another embodiment is changed into by one embodiment.Additionally, it should think that this development is probably complicated and expended
Time, but it is only to those skilled in the art routine work.
More specifically description is of the invention by way of example referring to the drawings in the following passage.Will according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that accompanying drawing is using very simplified form and using non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
Fig. 4 a-4f are refer to, in the present embodiment, it is proposed that a kind of preparation method in 3D nand flash memories raceway groove hole, the party
Method comprises the following steps：
S100：Such as Fig. 4 a, there is provided one has the substrate stacked structure formed with raceway groove hole；
In the embodiment, the offer one has the substrate stacked structure formed with raceway groove hole can be with the following method：
S101：There is provided substrate 100, interlayer dielectric layer 110 of the surface of substrate 100 formed with multi-layer intercrossed stacking and sacrificial
Domestic animal dielectric layer 120 forms substrate stacked structure, and the sacrificial dielectric layer 120 is formed between adjacent interlayer dielectric layer 110；And
And interlayer dielectric layer 110 is silicon oxide layer, the sacrificial dielectric layer 120 is silicon nitride layer；
S102：The substrate stacked structure is etched, etches the interlayer dielectric layer 110 and sacrificial dielectric layer 120 to be formed
Raceway groove hole 130, the raceway groove pass to the substrate 100 and form the silicon groove of certain depth；
S103：Silicon epitaxy layer 140 is formed, silicon is carried out at the silicon groove is epitaxially-formed silicon epitaxy layer 140；
S200：Such as Fig. 4 a, deposited in the raceway groove hole 130, form barrier layer 201, accumulation layer 202 and tunnel layer respectively
203, the barrier layer 201, accumulation layer 202 and tunnel layer 203 are respectively silicon oxide layer, silicon nitride layer and silicon oxide layer.And
The silicon oxide layer and silicon nitride layer are using atomic layer deposition method (ALD) formation；
S300：Such as Fig. 4 b, the deposition of progress first layer polysilicon layer 301；301 layers of the first layer polysilicon uses low pressure
Chemical vapour deposition technique (LPCVD) formation；
S400：Such as Fig. 4 c, low temperature free-radical oxidation (Low is carried out to the polysilicon layer 301 of first layer deposition
Temperature radical oxidation), to form oxidation masking layer 401；The temperature of the low temperature free-radical oxidation is small
In 530 DEG C；
S500：Such as Fig. 4 d, to the oxidation masking layer 401 in raceway groove bottom hole portion, first layer polysilicon layer 301, tunnel layer 203,
Accumulation layer 202 and barrier layer 201 perform etching, until spilling the simultaneously over etching silicon epitaxy layer 140 1 of silicon epitaxy layer (SEG) 140
Depthkeeping degree；
S600：Such as Fig. 4 e, oxidation masking layer 401 is removed, and carry out second layer polysilicon 701 and deposit preceding prerinse；It is described
Oxidation masking layer 401 is removed to carry out using acid standard cleaning (SC2)；Prerinse is adopted before the second layer polysilicon 701 deposits
Carried out with diluted hydrofluoric acid (DHF)；
S700：Such as Fig. 4 f, the deposition of progress second layer polysilicon layer 701.
To sum up, the present embodiment uses the low temperature free-radical oxidation technique oxidation polysilicon layer less than 530 DEG C, forms masking oxygen
Change layer, uniform in shaping is good, also, low-temperature oxidation can prevent polysilicon crystal, compared to conventional atomic layer cvd silicon oxide more
Add densification, without particle and hole.The present invention carries out the prerinse before second layer polysilicon deposition using diluted hydrofluoric acid, can go
The SiO generated except polysilicon surface by low temperature free-radical oxidation2Layer, because diluted hydrofluoric acid is to polysilicon and SiO2With higher
Ratio is selected, can go out SiO2Without damaging polysilicon, compared to traditional alkaline standard cleaning (SC1), it is easier to stable control
The uniformity of polysilicon processed, and prevent the damage of polysilicon；And diluted hydrofluoric acid cleaning can ensure first layer polysilicon layer
Interface cleanness between second layer polysilicon layer, there is no interface SiO2The presence of layer.The 3D NAND that preparation can be greatly improved dodge
The performance deposited.
The foregoing is only a preferred embodiment of the present invention, but protection scope of the present invention be not limited thereto,
Any one skilled in the art the invention discloses technical scope in, the change or replacement that can readily occur in,
It should all be included within the scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of the claim
Enclose and be defined.
Claims (10)
- The preparation method in 1.3D nand flash memory raceway grooves hole, it is characterised in that methods described comprises the following steps：There is provided one has the substrate stacked structure formed with raceway groove hole；Deposited in the raceway groove hole, form barrier layer, accumulation layer and tunnel layer respectively；Carry out the deposition of first layer polysilicon layer；Low temperature free-radical oxidation (Low temperature radical are carried out to the polysilicon layer of first layer deposition Oxidation), to form oxidation masking layer；Oxidation masking layer, first layer polysilicon layer, tunnel layer, accumulation layer and barrier layer to raceway groove bottom hole portion perform etching, directly To spilling silicon epitaxy layer (SEG) and the over etching silicon epitaxy layer certain depth；Oxidation masking layer is removed, and carries out prerinse before second layer polysilicon deposition；Carry out the deposition of second layer polysilicon layer.
- 2. preparation method as claimed in claim 1, it is characterised in that the offer one has the substrate formed with raceway groove hole Stacked structure is with the following method：Substrate is provided, interlayer dielectric layer and sacrificial dielectric layer of the substrate surface formed with multi-layer intercrossed stacking form substrate heap Stack structure, the sacrificial dielectric layer are formed between adjacent interlayer dielectric layer；The interlayer dielectric layer is silicon oxide layer, described Sacrificial dielectric layer is silicon nitride layer；The substrate stacked structure is etched, etches the interlayer dielectric layer and sacrificial dielectric layer to form raceway groove hole, the raceway groove Pass to the substrate and form the silicon groove of certain depth；Silicon epitaxy layer is formed, silicon is carried out at the silicon groove is epitaxially-formed silicon epitaxy layer.
- 3. the method as described in claim 1, it is characterised in that the barrier layer, accumulation layer and tunnel layer are oxide-nitride Thing-oxide structure (ONO).
- 4. method as claimed in claim 3, it is characterised in that the oxidenitride oxide structure (ONO) uses Atomic layer deposition method (ALD) formation.
- 5. method as claimed in claim 4, it is characterised in that the oxidenitride oxide structure (ONO) is institute State oxide-nitride-oxide structure (ONO).
- 6. the method as described in claim 1, it is characterised in that the first layer polysilicon layer uses low-pressure chemical vapor deposition Method (LPCVD) formation.
- 7. method as claimed in claim 6, it is characterised in that the temperature of the low temperature free-radical oxidation is less than 530 DEG C.
- 8. the method as described in claim 1, it is characterised in that the removal oxidation masking layer uses acid standard cleaning (SC2) carry out.
- 9. the method as described in claim 1, it is characterised in that prerinse uses dilute hydrogen fluorine before the second layer polysilicon deposition Sour (DHF) is carried out.
- 10.3D nand flash memories, it is characterised in that the flash memory is prepared as the method described in any one in claim 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710740880.XA CN107731849B (en) | 2017-08-25 | 2017-08-25 | The preparation method and 3D nand flash memory in 3D nand flash memory channel hole |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710740880.XA CN107731849B (en) | 2017-08-25 | 2017-08-25 | The preparation method and 3D nand flash memory in 3D nand flash memory channel hole |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107731849A true CN107731849A (en) | 2018-02-23 |
| CN107731849B CN107731849B (en) | 2019-02-12 |
Family
ID=61204830
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710740880.XA Active CN107731849B (en) | 2017-08-25 | 2017-08-25 | The preparation method and 3D nand flash memory in 3D nand flash memory channel hole |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107731849B (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108538848A (en) * | 2018-06-21 | 2018-09-14 | 长江存储科技有限责任公司 | Semiconductor structure and forming method thereof |
| CN109103190A (en) * | 2018-08-24 | 2018-12-28 | 长江存储科技有限责任公司 | The forming method of semiconductor structure |
| CN109273359A (en) * | 2018-09-26 | 2019-01-25 | 长江存储科技有限责任公司 | A kind of lithographic method |
| CN110034123A (en) * | 2019-04-30 | 2019-07-19 | 长江存储科技有限责任公司 | Form the method and three-dimensional storage of three-dimensional storage |
| CN110600478A (en) * | 2019-08-28 | 2019-12-20 | 长江存储科技有限责任公司 | Preparation method of three-dimensional memory and three-dimensional memory |
| CN111180455A (en) * | 2020-01-02 | 2020-05-19 | 长江存储科技有限责任公司 | 3D memory device and method of manufacturing the same |
| CN111403396A (en) * | 2020-01-14 | 2020-07-10 | 长江存储科技有限责任公司 | Channel structure including tunneling layer with adjusted nitrogen weight percentage and method of forming the same |
| CN112216702A (en) * | 2020-10-09 | 2021-01-12 | 长江存储科技有限责任公司 | Etching process and 3D NAND manufacturing process |
| CN112490140A (en) * | 2020-11-18 | 2021-03-12 | 长江存储科技有限责任公司 | Method for monitoring unsealing of channel through hole |
| CN113437069A (en) * | 2021-06-28 | 2021-09-24 | 芯盟科技有限公司 | Dynamic random access memory and forming method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101335245A (en) * | 2007-06-28 | 2008-12-31 | 海力士半导体有限公司 | Method of fabricating flash memory device |
| US20100308396A1 (en) * | 2009-06-08 | 2010-12-09 | Hynix Semiconductor Inc. | Gate Patterns of Nonvolatile Memory Device and Method of Forming the Same |
| CN102097387A (en) * | 2009-12-15 | 2011-06-15 | 三星电子株式会社 | Methods of forming nonvolatile memory devices |
| CN106206507A (en) * | 2015-04-30 | 2016-12-07 | 旺宏电子股份有限公司 | Semiconductor structure and manufacture method thereof |
-
2017
- 2017-08-25 CN CN201710740880.XA patent/CN107731849B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101335245A (en) * | 2007-06-28 | 2008-12-31 | 海力士半导体有限公司 | Method of fabricating flash memory device |
| US20100308396A1 (en) * | 2009-06-08 | 2010-12-09 | Hynix Semiconductor Inc. | Gate Patterns of Nonvolatile Memory Device and Method of Forming the Same |
| CN102097387A (en) * | 2009-12-15 | 2011-06-15 | 三星电子株式会社 | Methods of forming nonvolatile memory devices |
| CN106206507A (en) * | 2015-04-30 | 2016-12-07 | 旺宏电子股份有限公司 | Semiconductor structure and manufacture method thereof |
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108538848A (en) * | 2018-06-21 | 2018-09-14 | 长江存储科技有限责任公司 | Semiconductor structure and forming method thereof |
| CN108538848B (en) * | 2018-06-21 | 2024-01-16 | 长江存储科技有限责任公司 | Semiconductor structure and forming method thereof |
| CN109103190A (en) * | 2018-08-24 | 2018-12-28 | 长江存储科技有限责任公司 | The forming method of semiconductor structure |
| CN109103190B (en) * | 2018-08-24 | 2020-12-11 | 长江存储科技有限责任公司 | Method for forming semiconductor structure |
| CN109273359B (en) * | 2018-09-26 | 2020-11-20 | 长江存储科技有限责任公司 | Etching method |
| CN109273359A (en) * | 2018-09-26 | 2019-01-25 | 长江存储科技有限责任公司 | A kind of lithographic method |
| CN110034123A (en) * | 2019-04-30 | 2019-07-19 | 长江存储科技有限责任公司 | Form the method and three-dimensional storage of three-dimensional storage |
| CN110034123B (en) * | 2019-04-30 | 2020-07-10 | 长江存储科技有限责任公司 | Method for forming three-dimensional memory and three-dimensional memory |
| CN110600478A (en) * | 2019-08-28 | 2019-12-20 | 长江存储科技有限责任公司 | Preparation method of three-dimensional memory and three-dimensional memory |
| CN110600478B (en) * | 2019-08-28 | 2022-03-18 | 长江存储科技有限责任公司 | Preparation method of three-dimensional memory and three-dimensional memory |
| CN111180455B (en) * | 2020-01-02 | 2022-11-29 | 长江存储科技有限责任公司 | 3D memory device and method of manufacturing the same |
| CN111180455A (en) * | 2020-01-02 | 2020-05-19 | 长江存储科技有限责任公司 | 3D memory device and method of manufacturing the same |
| CN111403396A (en) * | 2020-01-14 | 2020-07-10 | 长江存储科技有限责任公司 | Channel structure including tunneling layer with adjusted nitrogen weight percentage and method of forming the same |
| CN111403396B (en) * | 2020-01-14 | 2021-11-23 | 长江存储科技有限责任公司 | Channel structure including tunneling layer with adjusted nitrogen weight percentage and method of forming the same |
| US11444163B2 (en) | 2020-01-14 | 2022-09-13 | Yangtze Memory Technologies Co., Ltd. | Channel structure having tunneling layer with adjusted nitrogen weight percent and methods for forming the same |
| CN112216702A (en) * | 2020-10-09 | 2021-01-12 | 长江存储科技有限责任公司 | Etching process and 3D NAND manufacturing process |
| CN112490140A (en) * | 2020-11-18 | 2021-03-12 | 长江存储科技有限责任公司 | Method for monitoring unsealing of channel through hole |
| CN112490140B (en) * | 2020-11-18 | 2023-08-01 | 长江存储科技有限责任公司 | Method for monitoring unsealing of trench through hole |
| CN113437069A (en) * | 2021-06-28 | 2021-09-24 | 芯盟科技有限公司 | Dynamic random access memory and forming method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107731849B (en) | 2019-02-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107731849B (en) | The preparation method and 3D nand flash memory in 3D nand flash memory channel hole | |
| CN107464817B (en) | A kind of production method of 3D nand flash memories | |
| CN107591409B (en) | The production method of channel structure in a kind of 3D nand flash memory | |
| CN107706191B (en) | A kind of 3D nand flash memory channel hole polysilicon articulamentum forming method | |
| CN106941103A (en) | The forming method of nand memory | |
| JP6504178B2 (en) | Method of forming tunnel oxide layer in three dimensional NAND memory structure and related device | |
| CN107731741B (en) | A kind of process improving contact hole plug oxide recess | |
| CN106206598B (en) | Gate-division type flash memory device making method | |
| CN104538363B (en) | The structure and manufacture method of SONOS flash memories | |
| CN104241204B (en) | The forming method of 3D nand flash memories | |
| CN107482017A (en) | A kind of preparation technology in 3D nand flash memories raceway groove hole | |
| CN109256384B (en) | Through hole structure, preparation method thereof and three-dimensional memory | |
| CN107994027B (en) | Method for reducing load effect influence in SONO etching | |
| CN107591408B (en) | A kind of 3D NAND flash memory structure and preparation method thereof | |
| CN107658222A (en) | A kind of flatening process in 3D nand flash memories raceway groove hole | |
| CN103811307B (en) | Semiconductor device and forming method thereof | |
| CN107731839A (en) | A kind of 3D NAND flash memory structures and preparation method thereof | |
| CN107994030B (en) | A kind of 3D nand flash memory preparation method stacked based on oxide-graphene film and flash memory | |
| CN107658223B (en) | The preparation process of polysilicon plug in a kind of flash memory structure | |
| CN107731829B (en) | The contact hole forming method and contact structure of 3D nand flash memory | |
| CN107968050B (en) | Method for etching bottom of channel hole | |
| CN101859725B (en) | Method for forming wafer by improving edge of shallow trench isolation structure | |
| CN107731841A (en) | A kind of method of improvement 3D nand flash memory SEG growth qualities | |
| CN111863826A (en) | Manufacturing method of graphical mask and manufacturing method of three-dimensional NAND memory | |
| CN107731831A (en) | A kind of process for improving contact hole plug oxide depression |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |