CN107731849B - The preparation method and 3D nand flash memory in 3D nand flash memory channel hole - Google Patents
The preparation method and 3D nand flash memory in 3D nand flash memory channel hole Download PDFInfo
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- CN107731849B CN107731849B CN201710740880.XA CN201710740880A CN107731849B CN 107731849 B CN107731849 B CN 107731849B CN 201710740880 A CN201710740880 A CN 201710740880A CN 107731849 B CN107731849 B CN 107731849B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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Abstract
The present invention provides the production methods and 3D nand flash memory in 3D nand flash memory channel hole, which comprises deposits in the channel hole of substrate stacked structure, is respectively formed barrier layer, accumulation layer and tunnel layer；Then the deposition of first layer polysilicon layer is carried out；Low temperature free-radical oxidation is carried out to the polysilicon layer of first layer deposition, to form oxidation masking layer；The oxidation masking layer of channel hole bottom, first layer polysilicon layer, tunnel layer, accumulation layer and barrier layer are performed etching, until leaking out silicon epitaxy layer simultaneously over etching silicon epitaxy layer certain depth；Oxidation masking layer is removed, and carries out prerinse before second layer polysilicon deposition；Carry out the deposition of second layer polysilicon layer.Oxidation masking layer is formed and using the prerinse before diluted hydrofluoric acid progress second layer polysilicon deposition due to using low temperature free-radical oxidation technique, it saves polysilicon and returns quarter step, formation uniformity is good, the channel hole polysilicon layer of high quality, and at low cost, high reliablity.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of preparation sides of 3D nand flash memory channel hole polysilicon
Method.
Background technique
In order to improve the density of memory device, industry is dedicated to the memory cell that research and development reduce two-dimensional arrangement extensively
Size method.With the memory cell dimensions continual reductions of two-dimentional (2D) memory device, signal conflict and interference can be shown
It writes and increases, so that being difficult to carry out multi-level-cell (MLC) operation.In order to overcome the limitation of 2D memory device, there is three-dimensional
The research in memory device this year of (3D) structure is gradually warmed up, by by memory cell be three-dimensionally disposed in substrate come
Improve integration density.
In the production of 3D nand flash memory, it is related to the preparation method in channel hole and each functional layer of side wall, specifically, existing skill
The method that channel hole side wall functional layer is made in art please refers to Fig. 1 a-1e:
S1: such as Fig. 1 a, stacked structure is formed in channel hole side wall, the stacked structure is ONO structure (oxide skin(coating) 1-1-
Nitride layer 1-2- oxide skin(coating) 1-3)；The ONO structure generallys use atomic layer deposition method (ALD) preparation, then first layer
Polysilicon deposition 1-4；
S2: such as Fig. 1 b, the wet process of first layer polysilicon, which is returned, is carved；It generallys use alkaline standard cleaning (SC1) and cuts down first layer
Polysilicon 1-4；
S3: such as Fig. 1 c, barrier oxide (CAP Buffer Oxide) 1-5 deposition is sheltered, which generallys use atom
Layer sedimentation (ALD)；Purpose is for the polysilicon structure of subsequent etch protective side wall deposition；
S4: such as Fig. 1 d, the SONO layer etching of channel hole bottom is carried out, and carries out wet removing (wet strip) barrier oxidation
Object 1-5；And carry out prerinse before second layer polysilicon deposition；
S5: such as Fig. 1 e, the deposition of second layer polysilicon, so that the polysilicon layer 1-6 of second layer deposition sinks first layer
Long-pending polysilicon layer 1-4 is connected to silicon epitaxy layer.
1) it still, in the above-mentioned methods, has following defects that and is returned in carving technology in the polysilicon wet process in S2 step, it is difficult
To control the uniformity of polysilicon thickness, as shown in the photo of Fig. 2, the thickness of channel hole periphery polysilicon is in circumference four direction
Thickness be respectively 6.66 (nm), 6.84 (nm), 7.02 (nm) and 7.2 (nm), difference up to 8% or so, and polysilicon vulnerable to
Damage, so that the formation to product impacts.The barrier oxidation of atomic layer deposition method (ALD) preparation used in the S3 step
Nitride layer is not fine and close enough, generates particle and hole the problem of due to technique itself in sedimentary, and at high cost, deposition efficiency is low
Under；The bottom disconnection problem of polysilicon easy to form in subsequent technique is integrated, as best shown in figures 3 a and 3b, it is seen then that the second layer is heavy
The long-pending bottom polysilicon layer 1-6 is there is no being connected to, by figure it can also be seen that the polysilicon of second layer deposition is in different location thickness
It is inconsistent, it is maximum in the thickness of silicon epitaxy layer deposition, in the thickness minimum (T of ONO structure part depositionSi>Ta-Si>TONO)。
Summary of the invention
In view of the above-mentioned drawbacks in the prior art, the purpose of the present invention is to provide a kind of 3D nand flash memory channel holes
Production method, this process simplify process flows in the prior art, and can form that uniformity is good, and the channel hole of high quality is more
The articulamentum of crystal silicon and bottom silicon epitaxy layer.To improve the performance of 3D nand flash memory.
To achieve the goals above, The technical solution adopted by the invention is as follows:
A kind of production method in 3D nand flash memory channel hole, described method includes following steps:
There is provided one has the substrate stacked structure for being formed with channel hole；
It is deposited in the channel hole, is respectively formed barrier layer, accumulation layer and tunnel layer；
Carry out the deposition of first layer polysilicon layer；
Low temperature free-radical oxidation (Low temperature radical is carried out to the polysilicon layer of first layer deposition
Oxidation), to form oxidation masking layer；
The oxidation masking layer of channel hole bottom, first layer polysilicon layer, tunnel layer, accumulation layer and barrier layer are carved
Erosion, until leaking out silicon epitaxy layer (SEG) simultaneously over etching silicon epitaxy layer certain depth；
Oxidation masking layer is removed, and carries out prerinse before second layer polysilicon deposition；
Carry out the deposition of second layer polysilicon layer.
Further, it is described provide one and have be formed with the substrate stacked structure in channel hole with the following method:
Substrate is provided, the substrate surface is formed with the interlayer dielectric layer of multi-layer intercrossed stacking and sacrificial dielectric layer forms lining
Bottom stacked structure, the sacrificial dielectric layer are formed between adjacent interlayer dielectric layer；The interlayer dielectric layer is silicon oxide layer,
The sacrificial dielectric layer is silicon nitride layer；
The substrate stacked structure is etched, etches the interlayer dielectric layer and sacrificial dielectric layer to form channel hole, it is described
Channel hole passes to the substrate and forms the silicon slot of certain depth；
Silicon epitaxy layer is formed, silicon is carried out at the silicon slot is epitaxially-formed silicon epitaxy layer.
Further, the barrier layer, accumulation layer and tunnel layer are oxidenitride oxide structure (ONO)；
Further, the oxidenitride oxide structure (ONO) is formed using atomic layer deposition method (ALD).
Further, the oxidenitride oxide structure (ONO) is the oxide-nitride-oxide knot
Structure (ONO)
Further, the first layer polysilicon layer is formed using Low Pressure Chemical Vapor Deposition (LPCVD).
Further, the temperature of the low temperature free-radical oxidation is less than 530 DEG C.
Further, the removal oxidation masking layer is carried out using acid standard cleaning (SC2).
Further, prerinse is carried out using diluted hydrofluoric acid (DHF) before the second layer polysilicon deposition.
It is a further object to provide a kind of 3D nand flash memories prepared using the above method.
Compared with prior art, the beneficial effects are mainly reflected as follows:
Firstly, the present invention uses the low temperature free-radical oxidation technique lower than 530 DEG C to aoxidize polysilicon layer, masking oxidation is formed
Layer, uniform in shaping is good, also, low-temperature oxidation can prevent polysilicon crystal, more compared to conventional atomic layer cvd silicon oxide
Densification, without particle and hole.
Secondly, the present invention carries out the prerinse before second layer polysilicon deposition using diluted hydrofluoric acid, polysilicon can be removed
The SiO that surface is generated by low temperature free-radical oxidation2Layer, since diluted hydrofluoric acid is to polysilicon and SiO2Selection ratio with higher, can
With the SiO that goes out2Without damaging polysilicon, compared to traditional alkaline standard cleaning (SC1), it is easier to stability contorting polysilicon
Uniformity, and prevent the damage of polysilicon；And diluted hydrofluoric acid cleaning can guarantee that first layer polysilicon layer and the second layer are more
Interface cleanness between crystal silicon layer does not have interface SiO2The presence of layer.
Again, the metal of deposition layer surface can be removed using acid standard cleaning, and can be with to the ONO structure of bottom
The processing for carrying out interface, is conducive to the deposition of second layer polysilicon deposition.
Finally, comprehensive use above-mentioned technology, the present invention can save polysilicon and return quarter step, and formation uniformity is good, high-quality
The channel hole polysilicon layer of amount, and at low cost, high reliablity.
Detailed description of the invention
By reading the following detailed description of the preferred embodiment, various other advantages and benefits are common for this field
Technical staff will become clear.The drawings are only for the purpose of illustrating a preferred embodiment, and is not considered as to the present invention
Limitation.And throughout the drawings, the same reference numbers will be used to refer to the same parts.In the accompanying drawings:
Fig. 1 a-1e is the method for making channel hole side wall functional layer in the prior art；
Fig. 2, the in the prior art microphoto of channel hole periphery polysilicon unevenness.
Fig. 3 a-3b, polysilicon bottom broken string is schemed in the prior art, and wherein 3a is schematic diagram, and 3b is microphoto.
Fig. 4 a-4f is the process flow chart of channel hole preparation method in the embodiment of the present invention 1.
Specific embodiment
The illustrative embodiments of the disclosure are more fully described below with reference to accompanying drawings.Although showing this public affairs in attached drawing
The illustrative embodiments opened, it being understood, however, that may be realized in various forms the disclosure without the reality that should be illustrated here
The mode of applying is limited.It is to be able to thoroughly understand the disclosure on the contrary, providing these embodiments, and can be by this public affairs
The range opened is fully disclosed to those skilled in the art.
For clarity, not describing whole features of practical embodiments.In the following description, it is not described in detail well known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
In hair, it is necessary to make a large amount of implementation details to realize the specific objective of developer, such as according to related system or related business
Limitation, changes into another embodiment by one embodiment.Additionally, it should think that this development may be complicated and expend
Time, but to those skilled in the art it is only routine work.
The present invention is more specifically described by way of example referring to attached drawing in the following passage.It is wanted according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very simplified form and using non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
Fig. 4 a-4f is please referred to, in the present embodiment, proposes a kind of production method in 3D nand flash memory channel hole, the party
Method the following steps are included:
S100: such as Fig. 4 a, providing one has the substrate stacked structure for being formed with channel hole；
In the embodiment, there is the substrate stacked structure for being formed with channel hole following method can be used for the offer one:
S101: providing substrate 100, and 100 surface of substrate is formed with the interlayer dielectric layer 110 of multi-layer intercrossed stacking and sacrificial
Domestic animal dielectric layer 120 forms substrate stacked structure, and the sacrificial dielectric layer 120 is formed between adjacent interlayer dielectric layer 110；And
And interlayer dielectric layer 110 is silicon oxide layer, the sacrificial dielectric layer 120 is silicon nitride layer；
S102: etching the substrate stacked structure, etches the interlayer dielectric layer 110 and sacrificial dielectric layer 120 to be formed
Channel hole 130, the channel hole pass to the substrate 100 and form the silicon slot of certain depth；
S103: forming silicon epitaxy layer 140, and silicon is carried out at the silicon slot is epitaxially-formed silicon epitaxy layer 140；
S200: it such as Fig. 4 a, is deposited in the channel hole 130, is respectively formed barrier layer 201, accumulation layer 202 and tunnel layer
203, the barrier layer 201, accumulation layer 202 and tunnel layer 203 are respectively silicon oxide layer, silicon nitride layer and silicon oxide layer.And
The silicon oxide layer and silicon nitride layer are formed using atomic layer deposition method (ALD)；
S300: such as Fig. 4 b, the deposition of first layer polysilicon layer 301 is carried out；301 layers of the first layer polysilicon use low pressure
Chemical vapour deposition technique (LPCVD) formation；
S400: such as Fig. 4 c, low temperature free-radical oxidation (Low is carried out to the polysilicon layer 301 of first layer deposition
Temperature radical oxidation), to form oxidation masking layer 401；The temperature of the low temperature free-radical oxidation is small
In 530 DEG C；
S500: such as Fig. 4 d, to the oxidation masking layer 401 of channel hole bottom, first layer polysilicon layer 301, tunnel layer 203,
Accumulation layer 202 and barrier layer 201 perform etching, until leaking out silicon epitaxy layer (SEG) 140 simultaneously over etching silicon epitaxy layer 140 1
Depthkeeping degree；
S600: such as Fig. 4 e, oxidation masking layer 401 is removed, and carries out second layer polysilicon 701 and deposits preceding prerinse；It is described
Oxidation masking layer 401 is removed to carry out using acid standard cleaning (SC2)；Prerinse is adopted before the second layer polysilicon 701 deposits
It is carried out with diluted hydrofluoric acid (DHF)；
S700: such as Fig. 4 f, the deposition of second layer polysilicon layer 701 is carried out.
To sum up, the present embodiment uses the low temperature free-radical oxidation technique lower than 530 DEG C to aoxidize polysilicon layer, forms masking oxygen
Change layer, uniform in shaping is good, also, low-temperature oxidation can prevent polysilicon crystal, more compared to conventional atomic layer cvd silicon oxide
Add densification, without particle and hole.The present invention carries out the prerinse before second layer polysilicon deposition using diluted hydrofluoric acid, can go
The SiO generated except polysilicon surface by low temperature free-radical oxidation2Layer, since diluted hydrofluoric acid is to polysilicon and SiO2It is with higher
Ratio is selected, can go out SiO2Without damaging polysilicon, compared to traditional alkaline standard cleaning (SC1), it is easier to stablize control
The uniformity of polysilicon processed, and prevent the damage of polysilicon；And diluted hydrofluoric acid cleaning can guarantee first layer polysilicon layer
Interface cleanness between second layer polysilicon layer does not have interface SiO2The presence of layer.The 3D NAND that preparation can be greatly improved dodges
The performance deposited.
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto,
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by anyone skilled in the art,
It should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of the claim
Subject to enclosing.
Claims (7)
- The production method in 1.3D nand flash memory channel hole, which is characterized in that described method includes following steps:There is provided one has the substrate stacked structure for being formed with channel hole；It is deposited in the channel hole, is respectively formed barrier layer, accumulation layer and tunnel layer；Carry out the deposition of first layer polysilicon layer；Low temperature free-radical oxidation (Low temperature radical is carried out to the polysilicon layer of first layer deposition Oxidation), to form oxidation masking layer；The oxidation masking layer of channel hole bottom, first layer polysilicon layer, tunnel layer, accumulation layer and barrier layer are performed etching, directly To leaking out silicon epitaxy layer and the over etching silicon epitaxy layer certain depth；Oxidation masking layer is removed, the removal oxidation masking layer is carried out using acid standard cleaning；And carry out second layer polysilicon Preceding prerinse is deposited, prerinse is carried out using diluted hydrofluoric acid before the second layer polysilicon deposition；Carry out the deposition of second layer polysilicon layer.
- 2. production method as described in claim 1, which is characterized in that described to provide one with the substrate for being formed with channel hole Stacked structure is with the following method:Substrate is provided, the substrate surface is formed with the interlayer dielectric layer of multi-layer intercrossed stacking and sacrificial dielectric layer forms substrate heap Stack structure, the sacrificial dielectric layer are formed between adjacent interlayer dielectric layer；The interlayer dielectric layer is silicon oxide layer, described Sacrificial dielectric layer is silicon nitride layer；The substrate stacked structure is etched, etches the interlayer dielectric layer and sacrificial dielectric layer to form channel hole, the channel Hole passes to the substrate and forms the silicon slot of certain depth；Silicon epitaxy layer is formed, silicon is carried out at the silicon slot is epitaxially-formed silicon epitaxy layer.
- 3. the method as described in claim 1, which is characterized in that the barrier layer, accumulation layer and tunnel layer are oxide-nitride Object-oxide structure.
- 4. method as claimed in claim 3, which is characterized in that the oxidenitride oxide structure uses atomic layer Sedimentation is formed.
- 5. method as claimed in claim 4, which is characterized in that the oxidenitride oxide structure is the oxidation Silicon-silicon nitride-silicon oxide silicon structure.
- 6. the method as described in claim 1, which is characterized in that the first layer polysilicon layer uses low-pressure chemical vapor deposition Method is formed.
- 7. method as claimed in claim 6, which is characterized in that the temperature of the low temperature free-radical oxidation is less than 530 DEG C.
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| CN108538848B (en) * | 2018-06-21 | 2024-01-16 | 长江存储科技有限责任公司 | Semiconductor structure and forming method thereof |
| CN109103190B (en) * | 2018-08-24 | 2020-12-11 | 长江存储科技有限责任公司 | Method for forming semiconductor structure |
| CN109273359B (en) * | 2018-09-26 | 2020-11-20 | 长江存储科技有限责任公司 | Etching method |
| CN110034123B (en) * | 2019-04-30 | 2020-07-10 | 长江存储科技有限责任公司 | Method for forming three-dimensional memory and three-dimensional memory |
| CN110600478B (en) * | 2019-08-28 | 2022-03-18 | 长江存储科技有限责任公司 | Preparation method of three-dimensional memory and three-dimensional memory |
| CN111180455B (en) * | 2020-01-02 | 2022-11-29 | 长江存储科技有限责任公司 | 3D memory device and method of manufacturing the same |
| WO2021142602A1 (en) * | 2020-01-14 | 2021-07-22 | Yangtze Memory Technologies Co., Ltd. | Channel structure having tunneling layer with adjusted nitrogen weight percent and methods for forming the same |
| CN112216702B (en) * | 2020-10-09 | 2022-03-29 | 长江存储科技有限责任公司 | Etching process and 3D NAND manufacturing process |
| CN112490140B (en) * | 2020-11-18 | 2023-08-01 | 长江存储科技有限责任公司 | Method for monitoring unsealing of trench through hole |
| CN113437069B (en) * | 2021-06-28 | 2022-07-12 | 芯盟科技有限公司 | Dynamic random access memory and forming method thereof |
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| KR101194876B1 (en) * | 2009-06-08 | 2012-10-25 | 에스케이하이닉스 주식회사 | Gate pattern for nonvolatile memory device and manufacturing method of the same |
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| CN101335245A (en) * | 2007-06-28 | 2008-12-31 | 海力士半导体有限公司 | Method of fabricating flash memory device |
| CN102097387A (en) * | 2009-12-15 | 2011-06-15 | 三星电子株式会社 | Methods of forming nonvolatile memory devices |
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