CN107658316B - The 3D nand flash memory of the 3D NAND preparation method and acquisition that prevent SEG from damaging - Google Patents
The 3D nand flash memory of the 3D NAND preparation method and acquisition that prevent SEG from damaging Download PDFInfo
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- CN107658316B CN107658316B CN201710726144.9A CN201710726144A CN107658316B CN 107658316 B CN107658316 B CN 107658316B CN 201710726144 A CN201710726144 A CN 201710726144A CN 107658316 B CN107658316 B CN 107658316B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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Abstract
The present invention provides the 3D NAND preparation method for preventing SEG from damaging and the 3D nand flash memories of acquisition, the method includes, in the preparation process of the neighboring area device, HF and/or HNO used by carrying out strong clean to substrate back is replaced using acid standard cleaning (SC2)3；To not remove the SiO of substrate back2Film and polysilicon layer；The oxide of substrate back is remained, so that etching (dry method) technique in subsequent channel hole preparation process does not generate charge；And then the generation of electrochemical reaction during subsequent phosphoric acid etch is avoided to damage to prevent from electrochemical reaction occurs in phosphoric acid etching process to SEG.And then the avalanche of 3D structure can be prevented, and reduce BSG crash rate；Obtain higher product recovery rate.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of 3D NAND preparation method for preventing SEG from damaging and obtain
The 3D nand flash memory obtained.
Background technique
In order to improve the density of memory device, industry is dedicated to the memory cell that research and development reduce two-dimensional arrangement extensively
Size method.With the memory cell dimensions continual reductions of two-dimentional (2D) memory device, signal conflict and interference can be shown
It writes and increases, so that being difficult to carry out multi-level-cell (MLC) operation.In order to overcome the limitation of 2D memory device, there is three-dimensional
The research in memory device this year of (3D) structure is gradually warmed up, by by memory cell be three-dimensionally disposed in substrate come
Improve integration density.
3D nand flash memory, as shown in Figure 1-3, include peripheral devices region 1-1 and core step stack region 1-2, core
Step stack region 1-2 includes channel hole 2-1 and grid wire casing 3-1；Above structure generally includes following preparation process:
S1: the preparation of peripheral devices；
S2: the preparation of nucleus step stacked structure；
S3: the preparation in nucleus channel hole；
S4: the preparation of nucleus grid wire casing；
S5: pass through phosphoric acid (H using grid wire casing3PO4) etch the sacrificial dielectric layer nitride removed in stacked structure.
Wherein in S5 step, silicon will not be etched by phosphoric acid by chemical reaction, but in the presence of electrochemical reaction condition, silicon
It can be etched, chemical reaction process, electrochemical reaction process and etching process principle are as shown in Fig. 4, and 4-1 is chemistry in figure
Oxidation process, 4-2 are electrochemical oxidation process, and 4-3 is etching reaction process, and reaction equation is as follows:
≡Si-H+H2O→Si-OH+2H++2e- (1)
(≡Si)3Si-OH+3H2O→3(≡Si-H)+Si(OH)4 (2)
Wherein, formula (1) is the reaction process in the presence of electrochemical oxidation reactions condition, and formula (2) is etching process.
At this point, substrate molecule is to enliven state, it can directly be reacted with free electron, lead to the random thermal decomposition of Si-H, it should be with
The reaction of substrate molecule causes to generate two electronics in conduction band (conduction band, CB)；The anode that additional power supply applies
Current potential and opposite electrode will drive first free electron to leave surface to enter in conduction band, this process is in hydrone
(H2O it is prone under) attacking, and is accelerated in wet etch process, since this decomposition leaves filling of reacting with water
Sufficient space --- it is related to a molecule with reacting for water at this time, rather than two under the conditions of chemical oxidation --- and the reaction
Can occur in any position, therefore, electrochemical oxidation process is suitable non-selectivity, i.e., isotropic (although due to
Bielectron injection needs higher activation energy).Therefore, the degree of anisotropic depend on chemistry and electrochemical oxidation generation into
It row ratio and changes with additional current potential.
In the prior art, the film of substrate back is formed and removal process such as Fig. 5 a-e in the preparation process of neighboring area device
It is shown, specifically:
S1: Fig. 5 a is referred to, in one layer of SiO of substrate 5-1 Surface Creation2Then film 5-2 is carried out active area (AA) and high
The deposition of pressure area (HV) protective layer silicon nitride forms silicon nitride film 5-3 in substrate back；
S2: referring to Fig. 5 b, carries out the removal of protective layer silicon nitride 5-3, and deposits neighboring area grid polycrystalline silicon；In substrate
The back side forms polysilicon film 5-4, is cleaned with HF or HNO3 to substrate back and the wet etching of gate blocks layer is gone
It removes, so that being removed when deposition neighboring area grid polycrystalline silicon in the polysilicon film 5-4 that substrate back generates；
S3: referring to Fig. 5 c, then carries out the deposition of peripheral devices barrier oxide layers, and carries out etching barrier layer (ESL)
The deposition of silicon nitride, to form membranous layer of silicon oxide 5-5 and silicon nitride film layer 5-6 at the back side substrate 5-1；
S4: referring to Fig. 5 d, then carries out wet etching to substrate back, removes etching barrier layer (ESL) silicon nitride film 5-
6；
S5: referring to Fig. 5 e, executes multistep wet etching to barrier oxide layers, and to subsequent buffer oxide nitride layer
It learns mechanical lapping (CMP), so that the membranous layer of silicon oxide 5-5 that the back side substrate 5-1 is formed is removed.
When substrate has carried out the process cycles of neighboring area grid and entered the process cycles in channel hole, if substrate is carried on the back
Face does not have oxide or protecting nitride, in the forming process of neighboring area grid and during channel hole etches, will produce
Raw charge.The charge of this generation will lead to the generation of the wet etching electrochemical reaction of Si described above.So that in phosphorus
During acid etch removes the sacrificial dielectric layer nitride in stacked structure, channel hole SEG is damaged.
The microphoto damaged after phosphoric acid etching to SEG in the prior art is as shown in Figure 6；And in subsequent BSG
Fracture and the avalanche of 3D structure or the failure of BSG in oxidation；Yield loss is greater than 90%.
Summary of the invention
In view of the above-mentioned drawbacks in the prior art, the purpose of the present invention is to provide the 3D NAND for preventing SEG from damaging preparations
Method and the 3D nand flash memory of acquisition, this method can prevent the damage to SEG in the process with phosphoric acid etches sacrificial nitride layer,
To improve the performance of 3D nand flash memory.
To achieve the goals above, The technical solution adopted by the invention is as follows:
The 3D NAND preparation method for preventing SEG from damaging, the method includes following preparation steps:
One Si substrate is provided；
The preparation of neighboring area device is carried out on substrate；In the preparation process of the neighboring area device, it is retained in
The SiO of substrate back2Polysilicon film is formed in substrate back when film and deposition neighboring area grid polycrystalline silicon；
The preparation of nucleus step stacked structure；The nucleus step stacked structure includes multi-layer intercrossed stacking
Interlayer dielectric layer and sacrificial dielectric layer form substrate stacked structure, the sacrificial dielectric layer be formed in adjacent interlayer dielectric layer it
Between；
The preparation in nucleus channel hole；The channel hole includes silicon epitaxial layer (SEG), and raw in the silicon epitaxy
Stacked structure on payzone；
The preparation of nucleus grid wire casing；
Pass through phosphoric acid (H using grid wire casing3PO4) etch the sacrificial dielectric layer removed in stacked structure.
Further, the preparation of the neighboring area device includes:
One layer of SiO of substrate 5-1 Surface Creation2Then film carries out active area (AA) and the nitridation of higher-pressure region (HV) protective layer
The deposition of silicon forms silicon nitride film in substrate back, carries out the removal of protective layer silicon nitride, and deposit neighboring area gate polycrystalline
Silicon；Polysilicon film is formed in substrate back.
Further, the preparation of the neighboring area device further include:
The SiO that weak wet-cleaning is retained in substrate back is carried out to the polysilicon film that substrate back is formed2Film and deposition
Polysilicon film is formed in substrate back when the grid polycrystalline silicon of neighboring area；
Wet process removal is carried out to neighboring area gate blocks layer；
The SiO that weak wet-cleaning is retained in substrate back is carried out again to the polysilicon film that substrate back is formed2Film and
Polysilicon film is formed in substrate back when depositing neighboring area grid polycrystalline silicon.
Further, the weak wet-cleaning is acid system standard cleaning (SC2).
Further, the preparation of the neighboring area device further include:
The deposition of silica barrier layer,
The deposition on silicon nitride etch barrier layer (ESL),
To form substrate, SiO in substrate back2Film, neighboring area gate polysilicon layer, silica barrier layer and nitrogen
The film layer structure of SiClx etching barrier layer (ESL).
Further, the preparation of the neighboring area device further include:
The removal of high-concentration dopant N-type (N+) area's wet process；
The removal of high-concentration dopant p-type (P+) area's wet process；
Nucleus barrier layer silicon nitride (SiN) wet etching；
By above-mentioned technique, the silicon nitride etch barrier layer (ESL) of the substrate back deposition is removed, and silica
Layer is removed
Further, the preparation method further include:
The first barrier layer of core space oxide wet etch；
0 interlayer insulating film nucleus the second oxide first time wet etching；
0 interlayer insulating film nucleus second of wet etching of the second oxide；
The second barrier layer of core space silicon nitride wet etching；
The chemical mechanical grinding removal of buffer oxide behind second barrier layer；
Cleaning；
By above-mentioned technique, the barrier oxide layers of the substrate back deposition are removed；And it is formed in channel hole and is formed
Before technique, there is SiO in substrate back2Polysilicon is formed in substrate back when film and deposition neighboring area grid polycrystalline silicon
Film.
Further, the interlayer dielectric layer is silicon oxide layer, and the sacrificial dielectric layer is silicon nitride layer.
It is a further object to provide a kind of 3D nand flash memories prepared using the above method.
Compared with prior art, the beneficial effects are mainly reflected as follows:
Firstly, charge will be generated in the preparation of neighboring area device and the etching process in channel hole, and the charge is once
Into subsequent phosphoric acid etches sacrificial dielectric layer process, it will lead to and electrochemical reaction occurs to the damage to SEG.And work as substrate
When there is oxide membranous layer to protect at the back side, charge will not be generated.Therefore, the present invention is by using weak cleaning, to prevent SEG's
Damage.
Secondly as preventing the damage of SEG, and then the avalanche of 3D structure can be prevented, and reduce BSG crash rate.
Again, the present invention can expand the window of phosphoric acid etch nitride, so that operation is more convenient.
Finally, the present invention can obtain higher product recovery rate using above-mentioned technology.
Detailed description of the invention
By reading the following detailed description of the preferred embodiment, various other advantages and benefits are common for this field
Technical staff will become clear.The drawings are only for the purpose of illustrating a preferred embodiment, and is not considered as to the present invention
Limitation.And throughout the drawings, the same reference numbers will be used to refer to the same parts.In the accompanying drawings:
The neighboring area of Fig. 1,3D NAND and the schematic diagram of nucleus step structure；
Fig. 2 is formed with the schematic diagram of channel pore structure in nucleus step structure；
Fig. 3, the structural schematic diagram after grid wire casing and etching sacrificial layer are formed in nucleus step structure；
The schematic illustration of chemical reaction, electrochemical reaction and etching process occurs for Fig. 4, silicon；
Fig. 5 a-e, the prior art carry out the variation of the film layer structure of substrate back when neighboring area device preparation technology circulation
Schematic diagram；
Fig. 6, the microphoto that SEG is damaged after phosphoric acid etching in the prior art；
Fig. 7 a-e, the variation of the film layer structure of substrate back is shown when the present invention carries out neighboring area device preparation technology circulation
It is intended to.
Specific embodiment
The illustrative embodiments of the disclosure are more fully described below with reference to accompanying drawings.Although showing this public affairs in attached drawing
The illustrative embodiments opened, it being understood, however, that may be realized in various forms the disclosure without the reality that should be illustrated here
The mode of applying is limited.It is to be able to thoroughly understand the disclosure on the contrary, providing these embodiments, and can be by this public affairs
The range opened is fully disclosed to those skilled in the art.
For clarity, not describing whole features of practical embodiments.In the following description, it is not described in detail well known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
In hair, it is necessary to make a large amount of implementation details to realize the specific objective of developer, such as according to related system or related business
Limitation, changes into another embodiment by one embodiment.Additionally, it should think that this development may be complicated and expend
Time, but to those skilled in the art it is only routine work.
The present invention is more specifically described by way of example referring to attached drawing in the following passage.It is wanted according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very simplified form and using non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
The present embodiment provides a kind of 3D NAND preparation methods for preventing SEG from damaging, and the method includes preparing step as follows
It is rapid:
S100 provides a Si substrate；
S200 carries out the preparation of neighboring area device on substrate；In the preparation process of the neighboring area device, protect
Stay in the SiO of substrate back2Polysilicon film is formed in substrate back when film and deposition neighboring area grid polycrystalline silicon；
S300, the preparation of nucleus step stacked structure；The nucleus step stacked structure includes multi-layer intercrossed
The interlayer dielectric layer and sacrificial dielectric layer of stacking form substrate stacked structure, and the sacrificial dielectric layer is formed in adjacent interlayer and is situated between
Between matter layer；The interlayer dielectric layer is silicon oxide layer, and the sacrificial dielectric layer is silicon nitride layer.
S400, the preparation in nucleus channel hole；The channel hole includes silicon epitaxial layer (SEG), and in the silicon
Stacked structure on epitaxial growth layer；
S500, the preparation of nucleus grid wire casing；
S600 passes through phosphoric acid (H using grid wire casing3PO4) etch the sacrificial dielectric layer removed in stacked structure.
Further, include: with reference to Fig. 7 a-d, the preparation S200 of the neighboring area device
S210: 700 Surface Creation of substrate, one layer of SiO2Then film 701 carries out active area (AA) and higher-pressure region (HV) and protects
The deposition of sheath silicon nitride forms silicon nitride film 702 in substrate back, as shown in Figure 7a；The removal of protective layer silicon nitride is carried out,
And deposit neighboring area grid polycrystalline silicon；Polysilicon film 703 is formed in substrate back, as shown in Figure 7b.
S220: sour standard cleaning (SC2) is carried out to the polysilicon film that substrate back is formed and is cleaned, substrate back is retained in
SiO2Polysilicon film 703 is formed in substrate back when film 701 and deposition neighboring area grid polycrystalline silicon；
S230: wet process removal is carried out to neighboring area gate blocks layer；
S240: acid system standard cleaning (SC2) is carried out to the polysilicon film that substrate back is formed again and is retained, in substrate back
SiO2Polysilicon film 703 is formed in substrate back when film 701 and deposition neighboring area grid polycrystalline silicon；As shown in Figure 7b；
S250: the deposition of silica barrier layer,
S260: the deposition of silicon nitride etch barrier layer (ESL), to form substrate 700, SiO in substrate back2Film
701, neighboring area gate polysilicon layer 703, silica barrier layer 704 and silicon nitride etch barrier layer (ESL) 705 film layer knot
Structure；As shown in Figure 7 c；
S270: the removal of high-concentration dopant N-type (N+) area's wet process, the removal of high-concentration dopant p-type (P+) area's wet process, nucleus
Barrier layer silicon nitride (SiN) wet etching；By above-mentioned technique, the silicon nitride etch barrier layer of the substrate back deposition
(ESL) it 705 is removed, and silica barrier layer 704 is removedAs shown in figure 7d；
S280: the first barrier layer of core space oxide wet etch；0 the second oxide of interlayer insulating film nucleus first
Secondary wet etching；0 interlayer insulating film nucleus second of wet etching of the second oxide；The second barrier layer of core space silicon nitride
Wet etching；The chemical mechanical grinding removal of buffer oxide behind second barrier layer；Cleaning；By above-mentioned technique, the substrate
The barrier oxide layers 704 of backside deposition are removed；And before being formed in channel hole formation process, there is SiO in substrate back2It is thin
Polysilicon film 703 is formed in substrate back when film 701 and deposition neighboring area grid polycrystalline silicon, as shown in figure 7e.
To sum up, using the above method, the oxide of substrate back is remained, so that in subsequent channel hole preparation process
Etching (dry method) technique do not generate charge；The generation for avoiding electrochemical reaction during subsequent phosphoric acid etch, to prevent
The damage of SEG.And in turn due to preventing the damage of SEG, and then the avalanche of 3D structure can be prevented, and reduce BSG mistake
Efficiency.The present invention can expand the window of phosphoric acid etch nitride, so that operation is more convenient.Using above-mentioned technology, the present invention can
To obtain higher product recovery rate.
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto,
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by anyone skilled in the art,
It should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of the claim
Subject to enclosing.
Claims (9)
1. the 3D NAND preparation method for preventing SEG from damaging, which is characterized in that the method includes following preparation steps:
One Si substrate is provided；
The preparation of neighboring area device is carried out on substrate；In the preparation process of the neighboring area device, it is retained in substrate
The SiO at the back side2Polysilicon film is formed in substrate back when film and deposition neighboring area grid polycrystalline silicon；
The preparation of nucleus step stacked structure；The nucleus step stacked structure includes the interlayer of multi-layer intercrossed stacking
Dielectric layer and sacrificial dielectric layer form substrate stacked structure, and the sacrificial dielectric layer is formed between adjacent interlayer dielectric layer；
The preparation in nucleus channel hole；The channel hole includes silicon epitaxial layer, and on the silicon epitaxial layer
Stacked structure；
The preparation of nucleus grid wire casing；
Pass through phosphoric acid (H using grid wire casing3PO4) etch the sacrificial dielectric layer removed in stacked structure.
2. the 3D NAND preparation method for preventing SEG from damaging as described in claim 1, which is characterized in that the neighboring area device
The preparation of part includes:
Substrate surface generates one layer of SiO2Then film carries out the deposition of active area and higher-pressure region protective layer silicon nitride, carry on the back in substrate
Face forms silicon nitride film, carries out the removal of protective layer silicon nitride, and deposits neighboring area grid polycrystalline silicon；It is formed in substrate back
Polysilicon film.
3. the 3D NAND preparation method for preventing SEG from damaging as claimed in claim 2, which is characterized in that the neighboring area device
The preparation of part further include:
The SiO that weak wet-cleaning is retained in substrate back is carried out to the polysilicon film that substrate back is formed2Film and deposition peripheral region
Polysilicon film is formed in substrate back when the grid polycrystalline silicon of domain；
Wet process removal is carried out to neighboring area gate blocks layer；
The SiO that weak wet-cleaning is retained in substrate back is carried out again to the polysilicon film that substrate back is formed2Film and deposition week
Polysilicon film is formed in substrate back when border region grid polycrystalline silicon.
4. the 3D NAND preparation method for preventing SEG from damaging as claimed in claim 3, which is characterized in that the weak cleaning is acid
Method standard cleaning.
5. the 3D NAND preparation method for preventing SEG from damaging as claimed in claim 4, which is characterized in that the neighboring area device
The preparation of part further include:
The deposition of silica barrier layer,
The deposition on silicon nitride etch barrier layer,
To form substrate, SiO in substrate back2Film, neighboring area gate polysilicon layer, silica barrier layer and silicon nitride
The film layer structure of etching barrier layer.
6. the 3D NAND preparation method for preventing SEG from damaging as claimed in claim 5, which is characterized in that the neighboring area device
The preparation of part further include:
The removal of high-concentration dopant N-type (N+) area's wet process；
The removal of high-concentration dopant p-type (P+) area's wet process；
Nucleus barrier layer silicon nitride wet etching；
By above-mentioned technique, the silicon nitride etch barrier layer of the substrate back deposition is removed, and silicon oxide layer is removed
7. the 3D NAND preparation method for preventing SEG from damaging as claimed in claim 5, which is characterized in that the preparation method is also
Include:
The first barrier layer of core space oxide wet etch；
0 interlayer insulating film nucleus the second oxide first time wet etching；
0 interlayer insulating film nucleus second of wet etching of the second oxide；
The second barrier layer of core space silicon nitride wet etching；
The chemical mechanical grinding removal of buffer oxide behind second barrier layer；
Cleaning；
By above-mentioned technique, the barrier oxide layers of the substrate back deposition are removed；And it is formed in channel hole formation process
Before, there is SiO in substrate back2Polysilicon film is formed in substrate back when film and deposition neighboring area grid polycrystalline silicon.
8. the 3D NAND preparation method for preventing SEG from damaging as described in claim 1-7 any one, which is characterized in that described
Interlayer dielectric layer is silicon oxide layer, and the sacrificial dielectric layer is silicon nitride layer.
9.3D nand flash memory, which is characterized in that 3D nand flash memory method as described in claim 1-8 any one obtains
?.
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