CN107658222A - A kind of flatening process in 3D nand flash memories raceway groove hole - Google Patents
A kind of flatening process in 3D nand flash memories raceway groove hole Download PDFInfo
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- CN107658222A CN107658222A CN201710728043.5A CN201710728043A CN107658222A CN 107658222 A CN107658222 A CN 107658222A CN 201710728043 A CN201710728043 A CN 201710728043A CN 107658222 A CN107658222 A CN 107658222A
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- raceway groove
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
Abstract
The invention provides a kind of flatening process in 3D nand flash memories raceway groove hole, it is included in deposit polycrystalline silicon connector in the raceway groove hole of O/N substrate stacked structures；And planarization process at least once is carried out, to remove the nitride layer of the O/N substrates stacked structure the superiors.Realize cmp (CMP) technique for different materials with visibly different removal rate by using the lapping liquid (Slurry) with high selectivity, so as to accurately control cmp planarizationization processing to rest at the tunic for wanting stop, and the silicon nitride etch step before can removing from common process, so as to avoid the destruction of the ONO stacked structures caused by over etching for trench sidewalls, and only need to carry out in a processing chamber housing, and simplify technique and equipment, cost is saved, improves effect.By present invention process, polysilicon plug height and the uniformity of pattern can be effectively improved, so as to enhance product performance, so as to improve the overall performance of 3D nand flash memories.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of 3D NAND flash memory structures and preparation method thereof, especially
It is a kind of flatening process in the raceway groove hole that can simplify raceway groove hole (Channel Hole) preparation method.
Background technology
With the development of plane flash memories, the production technology of semiconductor achieves huge progress.But recently
Several years, the development of plane flash memory encountered various challenges：Physics limit, the existing developing technique limit and storage electron density
Limit etc..In this context, to solve the difficulty and most ask being produced into for lower unit storage unit that planar flash memory runs into
This, a variety of three-dimensional (3D) flash memories structures are arisen at the historic moment, such as 3D NOR (3D or non-) flash memories and 3D NAND
(3D with non-) flash memory.
Wherein, in the 3D flash memories of NOR-type structure, memory cell is arranged in parallel between bit line and ground wire, and in NAND
In the 3D flash memories of type structure, memory cell tandem between bit line and ground wire arranges.NAND-type flash memory tool with cascaded structure
There is relatively low reading speed, but there is higher writing speed, so as to which NAND-type flash memory is suitable for data storage, its is excellent
Point is that small volume, capacity are big.Flush memory device can be divided into stacked grid type and separate gate type according to the structure of memory cell, and
And floating gate device and silicon-oxide-nitride-oxide (SONO) device are divided into according to the shape of charge storage layer.Its
In, SONO types flush memory device has the reliability more excellent than floating grid polar form flush memory device, and can be performed with relatively low voltage
Programming and erasing operation, and ONOS types flush memory device has very thin unit, and be easy to manufacture.
At present, in the conventional fabrication process in 3D NAND structure raceway grooves hole, comprise the following steps (such as Fig. 1 a~1d institutes
Show)：
S1：Deposit polycrystalline silicon connector, as shown in Figure 1a, connector oxide return carve spatial deposition polysilicon it is more to be formed
Crystal silicon connector 1；
S2：Planarization process, as shown in Figure 1 b, the polycrystalline is planarized using cmp (CMP) technique
The surface of silicon connector 1 is to expose the hard silicon nitride layer 2 of the superiors；
S3：Etch nitride silicon layer, as illustrated in figure 1 c, using wet-etching technology, etch the hard nitridation of the superiors
Silicon layer 2；
S4：Deposited oxide layer is (not shown) to carry out oxide deposition to form oxide skin(coating)；
S5：Secondary planarization process, as shown in Figure 1 d, using the planarization connector oxidation of cmp (CMP) technique
The surface of nitride layer to expose the silicon nitride layer in polysilicon plug and ONO stacked structures, and accurately control polysilicon plug and
The decrement of oxide skin(coating) 3 beside polysilicon plug.
But in above-mentioned common process, in the planarization process step of cmp (CMP), often produce
It is recessed (Dishing) and abrades (Scratch), and caused depression (Dishing) can also enters one in a planarization process
Step aggravates depression (Dishing) problem caused by secondary planarization process, and depression can cause caused by planarization process twice
The height of polysilicon plug and the uniformity deterioration of pattern, so as to influence threshold voltage (Vt), ion implanting (Ion) effect, also
The processing steps such as photoetching and the etching of the via of subsequent back end processing procedure (Back End of Line, abbreviation BEOL) can be influenceed.No
Only in this way, during etch nitride silicon layer, it will usually be applicable certain over etching rate (about 70%), with compensate etch-rate and
The inhomogeneities of thickness, ensure fully to etch, and the destruction of this ONO stacked structure that can cause trench sidewalls.It is in addition, above-mentioned
+ wet etching of cmp planarization+multiple wet-cleaning removes polymer beads twice in common process, and processing step is more
It is various, the overall time that control also increases processing procedure is neither easy, increases cost.Above mentioned problem can all have a strong impact on final production
The yield and performance of product.
Therefore, how to avoid the depression in cmp planarization and simplify above-mentioned manufacturing process as far as possible, be always art technology
Personnel endeavour the direction of research.
The content of the invention
It is an object of the invention to provide a kind of preparation method of 3D nand flash memories, raceway groove hole (Channel can be simplified
Hole manufacturing process), and the depression in planarization process (Dishing) problem is reduced, so as to improve the property of 3D nand flash memories
Energy.
To achieve these goals, the present invention proposes the flatening process in 3D nand flash memory raceway grooves hole, and it includes following
Step：
The deposit polycrystalline silicon connector in the raceway groove hole of O/N substrate stacked structures；
Planarization process at least once is carried out, to remove the nitride layer of the O/N substrates stacked structure the superiors, and essence
Really control the decrement of the oxide beside polysilicon plug and polysilicon plug.
Further, the planarization process uses cmp (CMP) technique.
Further, the number of the planarization process is once.
Further, when the number of the planarization process is one time, the lapping liquid of cmp (CMP) use
(Slurry) removal is selectively polysilicon removal rate ＞ nitride removal speed ＞ oxide removal speed.Preferably
The SiO that particle diameter is 10-200nm, mass percent is 2-5%2Lapping liquid.
Further, the number of the planarization process is secondary.
Further, when the number of the planarization process is secondary, the cmp of each planarization process
(CMP) technique uses different lapping liquids (Slurry), the lapping liquid (Slurry) that wherein first time planarization process uses
It is polysilicon removal rate ＞ nitride removal speed, to remove unnecessary polysilicon plug, and accurately to end to remove selectivity
In the nitride layer of the O/N substrates stacked structure the superiors, preferably particle diameter be 25-500nm, mass percent 3-
8% SiO2Lapping liquid；And then the removal of the lapping liquid (Slurry) used due to second of planarization process selectively for：
Polysilicon removal rate ＞ oxide removal speed, and nitride removal speed ＞ oxide removal speed, to remove nitridation
Nitride layer and polysilicon plug, and accurately end in the oxide skin(coating) of the O/N substrates stacked structure the superiors, preferably quality hundred
Point than for 5%-30%, more have the hydrogen peroxide lapping liquid for electing 10% as.
Further, the O/N substrates stacked structure is silica/silicon nitride stacked structure.
Further, the side wall in the raceway groove hole has ONOP stacked structures.
Further, the decrement of the oxide is, relative to O/N substrate stacked structures the superiors oxide layer thicknesses
Decrement be less than
The present invention also provides a kind of 3D NAND flash memory structures, and it is by the planarization in foregoing 3D nand flash memory raceway grooves hole
Technique is prepared.
Compared with prior art, the beneficial effects are mainly as follows：
First, realize cmp (CMP) work by using the lapping liquid (Slurry) with high selectivity
Skill has visibly different removal rate for different materials, thinks so as to accurately control cmp planarizationization processing to rest on
At the tunic to be stopped；
Second, by a step or multi-step chemical mechanical lapping (CMP) technique, the nitrogen before can removing from common process
SiClx etch step, so as to avoid the destruction of the ONO stacked structures caused by over etching for trench sidewalls；
3rd, due to eliminating etching technics and multiple wet clean process, above-mentioned processing procedure can be caused either to use
One step CMP or multistep CMP, all only need to carry out in a processing chamber housing, and simplify technique and equipment, save into
This, improves effect.
4th, by above-mentioned technique, polysilicon plug height and the uniformity of pattern can be effectively improved, so as to improve production
Moral character energy.
Brief description of the drawings
By reading the detailed description of hereafter preferred embodiment, it is various other the advantages of and benefit it is common for this area
Technical staff will be clear understanding.Accompanying drawing is only used for showing the purpose of preferred embodiment, and is not considered as to the present invention
Limitation.And in whole accompanying drawing, identical part is denoted by the same reference numerals.In the accompanying drawings：
Fig. 1 a-d are the flatening process flow chart in 3D nand flash memories raceway groove hole in the prior art；
Fig. 2 a-b are the flatening process flow chart in 3D nand flash memory raceway grooves hole in the embodiment of the present invention 1；
Fig. 3 a-c are the flatening process flow chart in 3D nand flash memory raceway grooves hole in the embodiment of the present invention 1.
Embodiment
The illustrative embodiments of the disclosure are more fully described below with reference to accompanying drawings.Although this public affairs is shown in accompanying drawing
The illustrative embodiments opened, it being understood, however, that may be realized in various forms the disclosure without the reality that should be illustrated here
The mode of applying is limited.Conversely, there is provided these embodiments are to be able to be best understood from the disclosure, and can be by this public affairs
The scope opened completely is communicated to those skilled in the art.
For clarity, whole features of practical embodiments are not described.In the following description, it is not described in detail known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
In hair, it is necessary to a large amount of implementation details are made to realize the specific objective of developer, such as according to relevant system or relevant business
Limitation, another embodiment is changed into by one embodiment.Additionally, it should think that this development is probably complicated and expended
Time, but it is only to those skilled in the art routine work.
More specifically description is of the invention by way of example referring to the drawings in the following passage.Will according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that accompanying drawing is using very simplified form and using non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
Fig. 2 is refer to, is the first embodiment of the present invention, in the present embodiment, it is proposed that a kind of 3D nand flash memories raceway groove
The flatening process in hole, comprises the following steps：
S100：The deposit polycrystalline silicon connector in the raceway groove hole of O/N substrate stacked structures；
S110：A planarization process is carried out, to remove the silicon nitride layer of the O/N substrates stacked structure the superiors.
Specifically, in the step s 100, refer to Fig. 2 a, first, step S101 is carried out, there is provided one has O/N substrates
The substrate 100 of stacked structure, the O/N substrates stacked structure be interlayer dielectric layer be silicon oxide layer 110 and sacrificial dielectric layer i.e.
The stacked structure that silicon nitride layer 120 forms；Then, step S102 is carried out, the O/N substrates stacked structure is performed etching with shape
Into raceway groove hole, and growing epitaxial silicon is carried out to obtain silicon epitaxy layer；Then, step S103 is carried out, side wall is formed in trench sidewalls
ONOP stacked structures (oxide-nitride-oxide-primary depositing polysilicon)；Then, step S104 is carried out, vertically downward
Etch the side wall ONOP stacked structures bottom and pass to silicon epitaxy layer；Then, step S105 is carried out, secondary polysilicon is carried out and sinks
Product；Then, step S106 is carried out, connector oxide is deposited and returns and carve；Finally, step S107, deposit polycrystalline silicon connector are carried out
130。
In step s 110, Fig. 2 b are refer to, a planarization process are carried out, to remove the O/N substrates stacked structure
The silicon nitride layer 120 of the superiors, obtains smooth surface.The planarization process uses cmp (CMP) work
Skill, and the removal of lapping liquid (Slurry) that the cmp (CMP) uses is selectively for polysilicon removal rate
＞ silicon nitride removal rate ＞ silica removal rates, so as to ensure effectively to remove polysilicon plug 130 and silicon nitride layer 120,
And silicon oxide layer 110 is accurately ended in, while ensure silicon oxide layer 110 relative to original O/N substrates stacked structure the superiors oxygen
The decrement of the thickness of SiClx layer 110 is less thanPreferably particle diameter be 10-200nm, mass percent be 2-5%'s
SiO2Lapping liquid.
Fig. 3 is refer to, is the second embodiment of the present invention, in the present embodiment, it is proposed that a kind of 3D nand flash memories raceway groove
The flatening process in hole, comprises the following steps：
S200：The deposit polycrystalline silicon connector in the raceway groove hole of O/N substrate stacked structures；
S210：First time planarization process is carried out, it is most upper that the planarization process ends in the O/N substrates stacked structure
The silicon nitride layer of layer；
S220：Second of planarization process is carried out, the planarization process removes the O/N substrates stacked structure the superiors
Silicon oxide layer.
Specifically, in step s 200, refer to Fig. 3 a, first, step S201 is carried out, there is provided one has O/N substrates
The substrate 200 of stacked structure, the O/N substrates stacked structure be interlayer dielectric layer be silicon oxide layer 210 and sacrificial dielectric layer i.e.
The stacked structure that silicon nitride layer 220 forms；Then, step S202 is carried out, the O/N substrates stacked structure is performed etching with shape
Into raceway groove hole, and growing epitaxial silicon is carried out to obtain silicon epitaxy layer；Then, step S203 is carried out, side wall is formed in trench sidewalls
ONOP stacked structures (oxide-nitride-oxide-primary depositing polysilicon)；Then, step S204 is carried out, vertically downward
Etch the side wall ONOP stacked structures bottom and pass to silicon epitaxy layer；Then, step S205 is carried out, secondary polysilicon is carried out and sinks
Product；Then, step S206 is carried out, connector oxide is deposited and returns and carve；Finally, step S207, deposit polycrystalline silicon connector are carried out
230。
In step S210, Fig. 3 b are refer to, first time planarization process are carried out, to remove a part of polysilicon plug
230, and planarization process is accurately ended at the silicon nitride layer 220 of the O/N substrates stacked structure the superiors.Described
Secondary planarization process uses cmp (CMP) technique, and the removal selectivity of the lapping liquid (Slurry) used
For polysilicon removal rate ＞ silicon nitride removal rates are accurate to cut so as to ensure that planarization process effectively removes polysilicon
Terminate at the silicon nitride layer 220 of the O/N substrates stacked structure the superiors.Preferably particle diameter is 25-500nm, quality hundred
Divide than the SiO for 6-10%2Lapping liquid.
In step S220, Fig. 3 c are refer to, carry out second of planarization process, knot is stacked to remove the O/N substrates
The silicon nitride layer 220 of the structure the superiors, obtains smooth surface.Second of planarization process is also ground using chemical machinery
(CMP) technique is ground, and the removal of the lapping liquid (Slurry) used is selectively for polysilicon removal rate ＞ silica removes
Speed, and silicon nitride removal rate ＞ silica removal rates.So as to ensure that planarization process effectively removes silicon nitride
Layer 220, and the silicon oxide layer 210 accurately ended in below the silicon nitride layers of the O/N substrates stacked structure the superiors, are protected simultaneously
The decrement for demonstrate,proving silicon oxide layer 110 is small relative to the decrement of the thickness of original O/N substrates stacked structure the superiors silicon oxide layer 110
InPreferably mass percent be 5%-30% hydrogen peroxide lapping liquid, most preferably 10% hydrogen peroxide lapping liquid.
To sum up, cmp (CMP) work is realized by using the lapping liquid (Slurry) with high selectivity
Skill has visibly different removal rate for different materials, thinks so as to accurately control cmp planarizationization processing to rest on
At the tunic to be stopped；By a step or multi-step chemical mechanical lapping (CMP) technique, before can removing from common process
Silicon nitride etch step, so as to avoid the destruction of the ONO stacked structures caused by over etching for trench sidewalls；By
In eliminating etching technics, above-mentioned processing procedure can be caused either to use a step CMP or multistep CMP, all only needed at one
Carried out in processing chamber housing, and simplify technique and equipment, save cost, improve effect.Pass through present invention process, Neng Gouyou
Effect improves polysilicon plug height and the uniformity of pattern, so as to enhance product performance, so as to improve the entirety of 3D nand flash memories
Performance.
The foregoing is only a preferred embodiment of the present invention, but protection scope of the present invention be not limited thereto,
Any one skilled in the art the invention discloses technical scope in, the change or replacement that can readily occur in,
It should all be included within the scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of the claim
Enclose and be defined.
Claims (10)
1. a kind of flatening process in 3D nand flash memories raceway groove hole, it is characterised in that it comprises the following steps：
The deposit polycrystalline silicon connector in the raceway groove hole of O/N substrate stacked structures；
Planarization process at least once is carried out, to remove the unnecessary polysilicon in the O/N substrates stacked structure top and the superiors
Nitride layer, and accurately control the decrement of the oxide beside polysilicon plug and polysilicon plug.
A kind of 2. flatening process in 3D nand flash memories raceway groove hole according to claim 1, it is characterised in that：
The planarization process uses cmp (CMP) technique.
A kind of 3. flatening process in 3D nand flash memories raceway groove hole according to claim 2, it is characterised in that：
The number of the planarization process is once.
A kind of 4. flatening process in 3D nand flash memories raceway groove hole according to claim 3, it is characterised in that：
When the number of the planarization process is one time, the lapping liquid (Slurry) of cmp (CMP) use
It is polysilicon removal rate ＞ nitride removal speed ＞ oxide removal speed to remove selectivity；Preferably particle diameter is
10-200nm, the SiO that mass percent is 2-5%2Lapping liquid.
A kind of 5. flatening process in 3D nand flash memories raceway groove hole according to claim 2, it is characterised in that：
The number of the planarization process is secondary.
A kind of 6. flatening process in 3D nand flash memories raceway groove hole according to claim 5, it is characterised in that：
When the number of the planarization process is secondary, cmp (CMP) technique of each planarization process is not using
Same lapping liquid (Slurry), the removal for the lapping liquid (Slurry) that wherein first time planarization process uses is selectively to be more
Crystal silicon removal rate ＞ nitride removal speed, to remove unnecessary polysilicon plug, and accurately ends in the O/N substrates heap
The SiO that the nitride layer of the stack structure the superiors, preferably particle diameter are 25-500nm, mass percent is 6-10%2Grinding
Liquid；And then the removal of the lapping liquid (Slurry) used due to second of planarization process selectively for：Polysilicon removes speed
Rate ＞ oxide removal speed, and nitride removal speed ＞ oxide removal speed, to remove nitride layer and polysilicon
Connector, and the oxide skin(coating) of the O/N substrates stacked structure the superiors is accurately ended in, preferably mass percent is 5%-
30% hydrogen peroxide solution.
A kind of 7. flatening process in 3D nand flash memories raceway groove hole according to claim 1, it is characterised in that：
The O/N substrates stacked structure is silica/silicon nitride stacked structure.
A kind of 8. flatening process in 3D nand flash memories raceway groove hole according to claim 1, it is characterised in that：
The side wall in the raceway groove hole has ONOP stacked structures.
9. a kind of flatening process in 3D nand flash memories raceway groove hole according to claim 1-8 any one, its feature exist
In：
The decrement of the oxide is that the decrement relative to O/N substrate stacked structures the superiors oxide layer thicknesses is less than
A kind of 10. 3D NAND flash memory structures, it is characterised in that：It is dodged as the 3D NAND described in claim 1-9 any one
The flatening process for depositing raceway groove hole is prepared.
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| US11943928B2 (en) | 2018-04-18 | 2024-03-26 | Yangtze Memory Technologies Co., Ltd. | Method for forming channel hole plug of three-dimensional memory device |
| CN109817571A (en) * | 2019-01-02 | 2019-05-28 | 长江存储科技有限责任公司 | A kind of preparation method of planarization process method and three-dimensional storage |
| CN111276413A (en) * | 2020-01-02 | 2020-06-12 | 长江存储科技有限责任公司 | Semiconductor structure, preparation method thereof and related detection method |
| CN112582422A (en) * | 2020-11-30 | 2021-03-30 | 长江存储科技有限责任公司 | Preparation method of three-dimensional memory and three-dimensional memory |
| CN112582422B (en) * | 2020-11-30 | 2022-02-11 | 长江存储科技有限责任公司 | Preparation method of three-dimensional memory and three-dimensional memory |
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