CN108054167B - The production method of embedded flash memory - Google Patents
The production method of embedded flash memory Download PDFInfo
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- CN108054167B CN108054167B CN201711297481.7A CN201711297481A CN108054167B CN 108054167 B CN108054167 B CN 108054167B CN 201711297481 A CN201711297481 A CN 201711297481A CN 108054167 B CN108054167 B CN 108054167B
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The present invention relates to the production methods of embedded flash memory, memory block in substrate is formed with gate structure, by forming conductive layer in logic area and memory block and covering the step difference that photoresist eliminates logic area and memory block, it is returned and is carved by photoresist, expose partial electroconductive layer, the partial electroconductive layer covers top and the part side wall of the gate structure, by remaining photoresist as photoetching compound protective layer, etch the partial electroconductive layer, to expose top and the part side wall of gate structure, certain thickness conductive layer is formd around gate structure, after removing photoetching compound protective layer, the conductive layer for covering the substrate is all formd in logic area and memory block, compared in prior art by depositing thicker polysilicon layer and making the method for the step difference that planarization process eliminates logic area and memory block, reduce process flow and can Save the cost.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to Embedded production methods.
Background technique
In recent years, with the rapid development in smart electronics product market, all kinds of microcontroller (micro controller
Unit, MCU) and SoC chip use be deep into each of the daily lifes such as automotive electronics, Industry Control and medical product
Aspect.And high performance MCU or SoC product is all be unable to do without in high-performance embedded flash memory (embedded flash, E-flash)
The support of core.Either from chip area, system performance and power consumption, or consider from manufacturing yield and on the design cycle, it is embedding
Enter formula memory to be all continuously increased the leading role of SoC design.Embedded flash memory is to patrol existing flash memory with existing
It collects module to be combined from physics or electricity, more diverse performance is provided.
Flash memory (flash) is small in size with its, capacity is big, at low cost, power down number as a kind of safety, quick memory bank
According to the series of advantages such as not losing, become data and the most important carrier of program in embedded system.Wherein, each unit by
The 2T embedded flash memory of two transistor-storage tubes and selecting pipe (or erasing pipe) composition by selecting pipe due to that (or can be wiped
Except pipe) external disturbance (programming interference, or even erasing crosstalk) is reduced and even forgoes and be widely used.
In existing embedded flash memory manufacturing process, storage unit (storage is often carried out simultaneously on the same base
Area), the technique of logic transistor (logic area) and high voltage transistor, however, prior art passes through deposit polysilicon layer (two twice
Normally also include logic area among secondary deposit and deposit an oxide layer) and chemical mechanical grinding polysilicon layer eliminate and logic area and deposit
The step difference of storage area, etches polycrystalline silicon layer in logic area and memory block forms grid layer again later, subsequent to etch the grid layer again
To form the selection grid and/or erasing grid of logic area grid and memory block.Entire process time is long and with high costs.
Summary of the invention
The technical problem to be solved by the present invention is to prior arts in the selection grid for forming logic area grid and memory block and/or
Process flow cumbersome and at high cost problem when wiping grid.
To solve the above problems, including the following steps: the present invention provides a kind of production method of embedded flash memory
One substrate is provided, includes logic area and memory block in the substrate, the memory block is formed with gate structure, described
Gate structure includes the hard mask layer at the top of it and the side wall positioned at its side wall；Form conductive layer, the conductive layer covering
The memory block and the logic area；Photoresist layer is formed, the photoresist layer covers the conductive layer, and the photoresist
The surface of layer is parallel to the substrate surface；The part photoresist layer is removed, the part conductive layer, the part are exposed
Conductive layer covers the hard mask layer and the part side wall；Using the remaining photoresist layer as photoetching compound protective layer, carve
The conductive layer is lost, the hard mask layer and the part side wall are exposed；And the removal photoetching compound protective layer.
Optionally, the gate structure further include the floating gate sequentially formed along the substrate surface, contrasted between solid dielectric layer and
Control gate.
Optionally, grid oxic horizon, gate structure position are also formed between the substrate and the gate structure
Height above the grid oxic horizon is 200nm~250nm.
Optionally, the conductive layer includes polysilicon, and the thickness of the conductive layer is 40~60nm.
Optionally, the photoresist layer is formed using spin-coating method, the photoresist layer includes positive photoresist.
Optionally, the removal part photoresist layer utilizes anisotropic dry etch process.
Optionally, the removal part photoresist layer utilizes oxygen ashing process.
Optionally, it etches the conductive layer and utilizes anisotropic dry etch process.
Optionally, using the remaining photoresist layer as photoetching compound protective layer, the step of etching the conductive layer, includes:
So that the remaining conductive layer is flushed in the logic area with the memory block.
Optionally, the production method of the embedded flash memory further include: after removing the photoetching compound protective layer, etch institute
Conductive layer is stated, the grid of logic area and the selection grid of memory block and/or erasing grid are formed.
Using the production method of embedded flash memory provided by the invention, logic area and memory block are eliminated using photoresist
Step difference is returned by photoresist and is carved, exposes partial electroconductive layer, which covers the top and portion of the gate structure
Point side wall etches the conductive layer by remaining photoresist as photoetching compound protective layer, expose the stacking gate top and
Part side wall still retains the certain thickness conductive layer that is, in the substrate of the gate structure side, removes photoresist
After protective layer, the certain thickness conductive layer for covering the substrate, the remaining conduction are all formd in logic area and memory block
Layer can be used for being subsequently formed to be passed through in the grid of logic area and the selection grid of memory block and/or erasing grid, with prior art
It deposits thicker polysilicon layer and chemical mechanical grinding eliminates the side of the step difference of logic area and memory block etches polycrystalline silicon layer again
Method is compared, and process flow and cost-saved is reduced.
Detailed description of the invention
Fig. 1 is the flow diagram of the production method of the embedded flash memory of the embodiment of the present invention.
Fig. 2 a to Fig. 2 f is the diagrammatic cross-section of each step of production method of the embedded flash memory of the embodiment of the present invention.
Description of symbols:
100- substrate；110- logic area；The memory block 120-；130- gate structure；131- hard mask layer；133- side wall；
101- grid oxic horizon；102- fleet plough groove isolation structure；135- floating gate；137- contrasted between solid dielectric layer；139- control gate；140- is conductive
Layer；150- photoresist layer.
Specific embodiment
Make further specifically below in conjunction with production method of the drawings and specific embodiments to embedded flash memory of the invention
It is bright.According to following explanation, advantages and features of the invention will be become apparent from.It should be noted that attached drawing is all made of very simplification
Form and use non-accurate ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
Fig. 1 is the flow diagram of the production method of the embedded flash memory of the embodiment of the present invention.As shown in Figure 1, this implementation
The production method of the embedded flash memory of example includes the following steps:
S1: providing a substrate, include logic area and memory block in the substrate, and the memory block is formed with gate structure,
The gate structure includes the hard mask layer at the top of it and the side wall positioned at its side wall；
S2: forming conductive layer, and the conductive layer covers the memory block and the logic area；
S3: photoresist layer is formed, the photoresist layer covers the conductive layer, and the surface of the photoresist layer is parallel
In the substrate surface；
S4: the removal part photoresist layer exposes the part conductive layer, and the partial electroconductive layer covering is described hard
Mask layer and the part side wall；
S5: using the remaining photoresist layer as photoetching compound protective layer, etching the conductive layer, exposes and described covers firmly
Mold layer and the part side wall；And
S6: the photoetching compound protective layer is removed.
Fig. 2 a to Fig. 2 f is the diagrammatic cross-section of each step of production method of the embedded flash memory of the embodiment of the present invention.Below
It is described in more detail in conjunction with Fig. 1 to Fig. 2 a to production method of Fig. 2 f to the embedded flash memory of the present embodiment.
In conjunction with Fig. 1 and Fig. 2 a, step S1 is executed, a substrate 100 is provided, includes logic area 110 and memory block in substrate 100
120, wherein memory block 120 is formed with gate structure 130, and gate structure 130 includes 131 He of hard mask layer at the top of it
Positioned at the side wall 133 of its side wall.
Specifically, the material of substrate 100 can be silicon, germanium, SiGe or silicon carbide etc., it is also possible to cover silicon on insulator
(SOI) perhaps germanium on insulator (geoi) (GOI) or can also be III, V compounds of group such as other materials, such as GaAs.
Substrate 100 can also inject certain doping particle according to design requirement to change electrical parameter.
It include logic area 110 and memory block 120 in substrate 100, wherein and logic area 110 is used to form logic transistor,
Gate structure 130 is formd in memory block 120, the gate structure 130 of memory block 110 can be one or more, subsequent
It is used to form storage unit (cell).
It should be noted that the present embodiment emphasis, which describes to introduce, forms subsequent use in memory block 110 and logic area 120
The method for forming the grid and selecting pipe and the grid layer of the grid of erasing pipe of logic transistor, therefore, the base of step S1
On bottom 100, gate structure 130 is formd, and it is possible to think to have been completed but be not limited in substrate 100 following
Processing step: being formed with isolation channel in substrate 100, and has carried out in substrate 100 trap injection (such as deep N-well note
Enter), other ion implantings (such as ion implanting of adjustment threshold voltage) and annealing, still, those skilled in the art
It should be appreciated that being only to illustrate and patrol in schematic form in figure so that diagram can clearly express the core concept of the application
Area 110 and memory block 120 are collected, but this production method for not representing embedded flash memory of the present invention only includes these parts
Or step, well known flash memory structure and processing step can also reside in wherein.
In the present embodiment, fleet plough groove isolation structure 102 (STI) is formed in substrate 100, for logic area 110 with deposit
Isolation is formed between storage area 120 and between storage unit.Fleet plough groove isolation structure 102 includes spacer medium such as silica
Equal materials.
In this step, it is formed with grid oxic horizon 101 on 100 surface of substrate, gate structure 130 is located at grid oxic horizon
101 tops.Grid oxic horizon 101 is used to that charge to be avoided to pass through the floating gate in gate structure 130 to enter substrate 100, and then influences
The voltage status of substrate 100 adversely affects flash memory formation.The material of grid oxic horizon 101 can be silica or mix
The silica of nitrogen.Thickness for example existsExtremely
Gate structure 130 includes floating gate 135, contrasted between solid dielectric layer 137 and the control formed on 101 surface of grid oxic horizon
Grid 139, also, in the present embodiment, the top of gate structure 130 includes the hard mask layer 131 for covering control gate, gate structure
130 side include cover floating gate 135, contrasted between solid dielectric layer 137, control gate 139, hard mask layer 131 all side walls side wall
133。
Wherein, floating gate 135 is embedded between grid oxic horizon 101 and contrasted between solid dielectric layer 137, due to external circuit not
Have connection, be it is at floating state, to store charge, on floating gate 135, control gate 139 is used for for the position of control gate 139
The input and output of data are controlled, it is usually connected with external electrode such as wordline (word line).In general, floating gate 135
It may include the conductive materials such as polysilicon with control gate 139, polysilicon can be formed using chemical vapour deposition technique, floating gate 135 and control
Grid 139 processed also may include Doped ions, and the method for DOPOS doped polycrystalline silicon is, for example, that chemical vapour deposition technique is utilized to form one layer not
After doped polysilicon layer, ion implanting step is carried out to be formed, and is also possible to form doped polycrystalline using chemical vapour deposition technique
Silicon layer is simultaneously doped when participating in the cintest.
The effect of contrasted between solid dielectric layer 137 is that isolation floating gate 135 and control gate 139, its composition can be silica-nitridation
Silicon-silica (Oxide-Nitride-Oxide, ONO), the forming method of ONO are, for example, first to form one layer of oxygen with thermal oxidation method
After SiClx, using chemical vapour deposition technique in forming silicon nitride layer on silicon oxide layer, wet hydrogen and dioxygen oxidation portion are then used again
Divide silicon nitride layer and forms another layer of silicon oxide layer.Contrasted between solid dielectric layer 137 is also possible to the insulating materials such as silica.
The effect of hard mask layer 131 and side wall 133 includes protection floating gate 135 and control gate 139, can pass through chemical gas
Mutually the semiconductor technologies such as deposition and photoetching, dry etching are formed, and material can be silicon nitride or silica, in another embodiment
In, the material of side wall 133 can also be the multilayered structure such as ONO.
In the present embodiment, after step S1, height of the gate structure 130 above grid oxic horizon 101 is aboutExtremely
In conjunction with Fig. 1 and Fig. 2 b, step S2 is executed, forms conductive layer 140, conductive layer 140 covers memory block 120 and logic area
110, thus conductive layer 140 also covers gate structure 130.
Conductive layer 140 includes being subsequently used for forming the grid of logic area 110 and the selection grid and control of memory block 120
Grid, therefore comprising conductive material, in the present embodiment, conductive layer is, for example, polysilicon layer, and polysilicon layer can utilize chemical gaseous phase
Sedimentation is formed, and conductive layer 140 also may include Doped ions, and the method for DOPOS doped polycrystalline silicon is, for example, to utilize chemical vapor deposition
After method forms one layer of undoped polysilicon layer, ion implanting step is carried out to be formed, and is also possible to utilize chemical vapour deposition technique
It forms doped polysilicon layer and is doped when participating in the cintest.
Conductive layer 140 its be covered on logic area 110 and memory block 120 in substrate 100, wherein also cover grid knot
The top and side of structure 130, since the top of gate structure 130 and side are hard mask layer 131 and side wall 133 respectively, thus
Conductive layer 140 is covered on hard mask layer 131 and side wall 133 and surface.
In the present embodiment, conductive layer 140 does not need the very thick of deposition, and thickness is aboutExtremelyIt sinks in prior art
Long-pending polysilicon layer is thicker (typically larger than) be for the ease of flatening process (such as chemical mechanical milling tech,
CMP), but process time is long and at high cost.It is obviated in the present embodiment in order to eliminate logic area 110 and memory block
120 step difference and the CMP process used, conductive layer 140 do not need it is whole be thinned, thus its thickness can be mainly according to logic area
The thickness of 110 grid, the selection grid of memory block 120 and/or erasing grid is set.
In conjunction with Fig. 1 and Fig. 2 c, step S3 is executed, forms photoresist layer 150, photoresist layer 150 covers conductive layer 140, and
And the surface of photoresist layer 150 is parallel to 100 surface of substrate.
Specifically, photoresist layer 150 can use photoresist (or photoresist, class photoresist) material commonly used in the art, this reality
It applies in example, photoresist layer 150 is preferably flowable i.e. liquid form, so as to be coated in substrate 100 using spin coating proceeding,
Coating photoresist in substrate 100 using spin coating proceeding is the highly developed technique in this field, thus this step is easily achieved, and
And generally for the flat photoresist surface of formation and photoresist is made to have the effect of that enough etch stoppers, photoresist cover
Whole coating surfaces are covered, such as in the present embodiment, photoresist layer 150 is covered on 140 surface of conductive layer, and is easier to realize
Logic area 110 and the photoresist layer of memory block 120 150 flush, that is, pass through step S3, the surface of photoresist layer 150 is parallel
In 100 surface of substrate.
In the present embodiment, be conducive to by executing step S3 so that logic area 110 and memory block 120 overcome step difference
Synchronous etching technics is executed with memory block 120 in logic area 110.
In conjunction with Fig. 1 and Fig. 2 d, step S4 is executed, part photoresist layer 150 is removed, exposes partial electroconductive layer 140, it is described
Partial electroconductive layer 140 covers hard mask layer 131 and part side wall 133.
In this step, partial etching is carried out to photoresist layer 150, such as etch partially, it is preferred that photoresist layer 150 wraps
Include positive photoresist, positive photoresist described herein is referred in the feelings for not needing exposure machine commonly used in the art and being exposed
Under condition, Other substrate materials itself can protect a kind of photoresist of subsurface material in etching process.It, can using positive photoresist
After spin coating photoresist layer 150 in step s3 and such as baking-curing, directly progress step S4 can save exposure work
Sequence.But it will be understood by those skilled in the art that the present embodiment is not intended to limit the selection of photoresist 150, in certain embodiments, according to
Composite factor is considered, and photoresist 150 is also possible to negative photoresist, alternatively, photoresist layer 150 also may include certain chemistry
Reagent, such as bottom anti-reflective (BARC) material, top anti-reflective material (DARC), hmds (HMDS) etc., photoetching
Glue-line 150 may include exposure commonly used in the art/etch stopper material, and details are not described herein.
In the present embodiment, part photoresist layer 150 is removed to expose the hardmask layer of covering gate structure 130
131 and part side wall 133 conductive layer 140, can use the oxygen (O of dry etching2) cineration technics completes, etch period is big
About 10s to 15s, but not limited to this, cineration technics can be according to the height and etching used of gate structure 130, photoresist layer 150
The difference of equipment selects different partial etching methods.
By step S4, since the photoresist layer 150 of 130 top of gate structure is relatively thin, at the top of conductive layer 140 revealed
Out, also, by the adjustment of etching condition, the conductive layer 140 for covering a part of side wall 133 at close top can be exposed.I.e.
In memory block 120, in addition to 130 top of gate structure and 133 region of part side wall, conductive layer 140 is still by remaining photoresist layer
Covering, and in logic area 110, conductive layer 140 is still all covered by remaining photoresist layer.Remaining photoresist layer is by photoetching
Glue-line 150 etches, and in order to embody the connection of the two, remaining photoresist layer is still indicated with label 150.
In conjunction with Fig. 1 and Fig. 2 e, step S5 is executed, using remaining photoresist layer 150 as photoetching compound protective layer, etching conductive
Layer 140, exposes hard mask layer 131 and part side wall 133.
The method for etching other regions using photoresist overlay partial region is technique commonly used in the art, therefore this reality
It applies example step S5 is not unfolded to illustrate.In the present embodiment, the material of conductive layer 140 is, for example, polysilicon, to the quarter of conductive layer 140
Preferably anisotropic dry etching is lost, etching gas is preferably using selected from HBr, Cl2、SF6、O2、N2、NF3, Ar, He and CF4Group
At one of group or a variety of be used as etching gas.
By step S5, the conductive layer 140 that previous step exposes is removed, so that remaining conductive layer only covers
Around the gate structure 130 of memory block 120 and the whole region of logic area 110.Remaining conductive layer is by 140 quarter of conductive layer
Erosion is formed, and in order to embody the connection of the two, remaining conductive layer is still indicated with label 140.In preferred embodiment, quarter can be passed through
The adjustment of erosion condition so that the remaining conductive layer 140 being covered on around the gate structure 130 of memory block 120 be still photo-etched
140 thickness of conductive layer that glue-line 150 covers is same or similar, or flushes.However, the present invention is not limited thereto, according to logic area 110
Grid, memory block 120 selection grid and/or wipe grid gate type it is different, by step S5, the conduction of logic area 110
Layer 140 and the thickness of remaining conductive layer 140 around the gate structure 130 of memory block 120 can also be different.
In conjunction with Fig. 1 and Fig. 2 f, step S6 is executed, removes photoetching compound protective layer.The step is needed to remove and be patrolled in the present embodiment
Collect the remaining photoresist layer 150 in area 110 and memory block 120.Specifically part photoresist layer 150 can be removed using with step S4
The same or similar technique of method, removal (etching) photoresist is technique customary in the art, and details are not described herein again.
By above-mentioned steps S1 to step S6, the present embodiment forms conductive layer 140 in logic area 110 and memory block 120,
In memory block 120, conductive layer 140 is formed in around gate structure 130.It is subsequent to pass through patterning process etching conductive layer
140 (conductive layer 140 is remaining 140 material of partial electroconductive layer after step S1~S6), to form the grid of logic area 110
The selection grid and/or erasing grid of pole (being used to form logic transistor) and memory block 120.
In conclusion the production method of the embedded flash memory of the present embodiment, is forming the grid and use for being used for logic area 110
In memory block 120 selection grid and/or wipe grid conductive layer 140 when, do not need to deposit very thick conductive layer to cover grid
Structure utilizes the part of photoresist to carve to carry out the step difference that flatening process eliminates logic area 110 and memory block 120
Etching technique only forms the conduction of thickness described in the grid in actual logic area 110 or the selection grid of memory block 120 and/or erasing grid
Layer, it is possible to reduce process flow simultaneously saves the process cost.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of interest field of the present invention,
Anyone skilled in the art without departing from the spirit and scope of the present invention, may be by the methods and techniques of the disclosure above
Content makes possible variation and modification to technical solution of the present invention, therefore, anything that does not depart from the technical scheme of the invention,
Any simple modifications, equivalents, and modifications to the above embodiments according to the technical essence of the invention, belong to this hair
The protection scope of bright technical solution.
Claims (10)
1. a kind of production method of embedded flash memory characterized by comprising
One substrate is provided, includes logic area and memory block in the substrate, the memory block is formed with gate structure, the grid
Structure includes the hard mask layer at the top of it and the side wall positioned at its side wall；
Conductive layer is formed, the conductive layer covers the memory block and the logic area；
Photoresist layer is formed, the photoresist layer directly covers the conductive layer, and the surface of the photoresist layer is parallel to
The substrate surface；
Removal covers the photoresist layer of the segment thickness of the memory block and the logic area, exposes the part conduction
Layer, the partial electroconductive layer cover the hard mask layer and the part side wall；
Using the photoresist layer of residual thickness as photoetching compound protective layer, the conductive layer is etched, exposes the hard mask
Layer and the part side wall；And
Remove the photoetching compound protective layer.
2. the production method of embedded flash memory as described in claim 1, which is characterized in that the gate structure further includes along institute
State floating gate, contrasted between solid dielectric layer and control gate that substrate surface sequentially forms.
3. the production method of embedded flash memory as described in claim 1, which is characterized in that in the substrate and the grid knot
Be also formed with grid oxic horizon between structure, the gate structure be located at the height above the grid oxic horizon be 200~
250nm。
4. the production method of embedded flash memory as described in claim 1, which is characterized in that the conductive layer includes polysilicon,
The thickness of the conductive layer is 40~60nm.
5. the production method of embedded flash memory as described in claim 1, which is characterized in that form the photoetching using spin-coating method
Glue-line, the photoresist layer include positive photoresist.
6. the production method of embedded flash memory as described in claim 1, which is characterized in that the removal part photoresist layer benefit
Use anisotropic dry etch process.
7. the production method of embedded flash memory as described in claim 1, which is characterized in that the removal part photoresist layer benefit
Use oxygen ashing process.
8. the production method of embedded flash memory as described in claim 1, which is characterized in that etch the conductive layer using it is each to
Anisotropic dry etch process.
9. the production method of embedded flash memory as claimed in any one of claims 1 to 8, which is characterized in that with remaining described
For photoresist layer as photoetching compound protective layer, the step of etching the conductive layer includes: so that the remaining conductive layer is described
Logic area and the memory block flush.
10. the production method of embedded flash memory as claimed in any one of claims 1 to 8, which is characterized in that the embedded sudden strain of a muscle
The production method deposited further include: after removing the photoetching compound protective layer, etch the conductive layer, formed the grid of logic area with
And the selection grid and/or erasing grid of memory block.
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Address after: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee after: Wuhan Xinxin Integrated Circuit Co.,Ltd. Country or region after: China Address before: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee before: Wuhan Xinxin Semiconductor Manufacturing Co.,Ltd. Country or region before: China |