TWI353640B - Method of forming semiconductor structure - Google Patents

Description

1353640 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semi-conductive >§# gentleman 1«-diameter dry-forging structure, and more particularly to a memory device having at least three spacer thicknesses . [Previous technique #f] According to the design of the transistor and its intrinsic characteristics, the length of the channel region can be defined by the length of the lower channel between the source of the transistor and the # & or by the spacer around the gate. The effect of the transistor is affected by changing the resistance of the channel region. For example, the source/no-polar region can be defined by an ion implantation process by using a spacer and a spacer as a mask. Therefore, the visibility of the gap around the closed pole directly affects the size and position of the source/no-polar region. The thinner the gap wall, the closer the source/drain regions under the gate will be, and the shorter channel length will increase the operating speed of the transistor. For example, in memory applications, the gap between the gates of the array region is as thin as possible to increase the operating speed of the transistor, thereby increasing the efficiency of memory writing or output. A transistor located in the peripheral region that requires a higher operating voltage requires a thicker spacer to increase the length of its channel region to have a lower breakdown voltage, and more than one spacer thickness is required for individual The transistor of use defines the length of the channel region that is suitable. Therefore, there is a need in the industry to form spacers of different thicknesses in different regions of an integrated circuit to define a suitable length of the channel region to meet the operational requirements of individual components, and to avoid gaps in different thicknesses.

Clienfs Docket No.: 96-040 TT5s Docket No:0492-A41402-TW/f/JYChen 6 1353640 Affects the yield of subsequent processes. SUMMARY OF THE INVENTION The present invention provides a method of forming a semiconductor structure, including: a column region and a peripheral region 'and includes a plurality of layers in the array region, and the second gate stack including the low voltage component in the peripheral region隹^^β and the second gate stack g' of the voltage component form a first dielectric layer overlying the first gate gate stack, and above the third gate stack and sidewalls, depositing a second brother-dielectric On the layer, removing the second dielectric layer on the first gate stack and the second gate stack, leaving a second dielectric layer on the third gate stack, and then = two dielectric layers on the first An inter-electrode stack, a second gate stack, and a third gate I^back_second dielectric layer to expose the first dielectric layer, and remove the second dielectric layer in the array region to expose the first dielectric a layer, and etching back the first dielectric layer to expose the first gate stack, the second gate stack, and the upper surface of the third gate stack, and the first gate stack, the second gate stack, and the first gate stack The sidewalls of the three gate stacks respectively form a first spacer wall, a second spacer wall, and a third spacer wall, wherein the third spacer wall is thick A gap larger than the second wall, and the wall thickness of the second gap is larger than the first spacer. The above and other objects, features, and advantages of the present invention will become more apparent from the aspects of the invention. The spacer structure and its preparation method are applicable to many kinds of

Client's Docket No. :96-040 TT's Docket No:0492-A4I402-TW/f/JYChen 7 1353640 Conductor structure, especially suitable for the aspect ratio (aSpect ratio) of the opening (or gap) between components in a part of the structure High and regional components require thinner spacers and components in other regions require thicker spacers. For example, in the application of nonvolatile memory cells, the hidden ribs can be divided into, for example, an array region and a peripheral region. FIG. 1 to FIG. 10 are a series of processes. A cross-sectional view for explaining a manufacturing process for forming three different thickness spacers in an embodiment of the present invention. Referring now to Figure 1, the substrate 1 is first provided. The substrate 1 〇 includes an array region 12 and a peripheral region 14. Substrate 10 can be a semiconductor substrate such as a germanium substrate, a germanium substrate, other semiconductor compound substrates, or an insulating layer overlying germanium (SOI) or the like. The array region 12 includes a plurality of first gate stacks 16 having a plurality of openings (or gaps) of varying widths, at least one of which has an aspect ratio of greater than 2.6. In the peripheral region 14, a second gate stack 18 of low voltage components and a third gate stack 20 of high voltage components are included. The substrate between the second gate stack 18 and the third gate stack 2 may include shallow trenches, germanium & edge regions 11. The above-described gate stack can be fabricated by a conventional method in which the first gate stack 16, the second gate stack 18, and the third electrode stack 20 respectively include, for example, a gate electrode and a gate dielectric layer. And/or other material layers·#' is not shown in the figure for the simplified illustration. In addition, the first gate stack 16, the second gate stack 18, and the second, the visible stack 20 is a mask layer, and the substrate 1G is lightly doped and implanted on the substrate on both sides of the gate stack. Forming a first light-changing king pole region 16a, a second lightly doped source/drain region 18a, a two-source/汲汉卑 three lightly doped source

Client's Docket No.: 96-040 TT's Docket N〇: 0492-A41402-TW/f/JYChen 8 1353640 Polar/bungee area 20a. Lightly doped source/drain region or low energy and doping amount implanted in the substrate iq: = ion The formation of the pole/drain region can effectively avoid the hot electron effect. Lightly doped source In order to increase the operating speed and density of the component, the gate stack 16 will be formed with a thinner spacer, while the second gate stack 18 of the first-voltage component is required to be: The last time between the thick and the _, respectively, is shaped to avoid the premise of a breakdown (the τ stay: the ability of the pressure. ...therefore, having a faster operating speed, as shown in Fig. 1, the first dielectric layer 22 can be formed by, for example, a method or an oxidation method, and the square 22 of the substrate can be compliantly covered. On the first - gate stack 16 . Above and to the sidewalls of the first dielectric layer and the third gate stack 20. Wherein, the thickness of the /pole 18 will determine the thickness of the first gate stack 16 in the following::: the thickness of the interlayer of the electrical layer 22, the first dielectric layer can be adjusted as needed, and the operation requirements of the formed components are . Due to the first stack of electrodes; it is required to be thin so that the first dielectric layer 22 "

For example, the LV I meter process is an example, about 100 Α to about 200 Α. The material of the Weisheng 90 奈 electrical layer 22 includes yttrium oxide, tantalum nitride, ', 1 about l6 〇 A' first-intermediate material. . H-cut, or other suitable Next, in order to form a thick spacer in the high-voltage element, the array region 12 is formed with defects, and the present invention deposits the VIII:t of the thick spacer particularly at the stage. The deposition of the first stage of the second dielectric layer, that is, the first layer of the second dielectric layer, please refer to the second layer of the second dielectric layer with reference to Figure 2-4.

Clients Docket N〇.: 96-040 TT5s Docket No:0492-A41402-TW/f/JYChen 9 1353640. The row is selectively removed leaving only the second dielectric layer 24a of the third gate stack 20. Referring to FIG. 2, after the first dielectric layer 22 is formed, the second dielectric layer 24a may be deposited on the first dielectric layer 22 by a method such as chemical vapor deposition. The second dielectric layer 24a will form a spacer wall of the third gate stack 20 together with the first dielectric layer 22 and the second dielectric layer 24b to be deposited again. The thickness of the second dielectric layer 24a can be tolerated by the desired thickness of the spacer of the third gate stack 20, the thickness of the second dielectric layer 24b to be deposited again, and the high aspect ratio opening in the array region 12. The thickness and the like are adjusted. The thickness of the second dielectric layer 24a is exemplified by a 90 nm process, about 600 A to about 1000 A, preferably about 800 A. The second dielectric layer 24a needs to be different from the material of the first dielectric layer 22 to facilitate selective removal of the second dielectric layer 24a in subsequent processes. The material of the second dielectric layer 24a may be removed prior to being different from the first dielectric layer 22, and may include tantalum nitride, hafnium oxide, hafnium oxynitride, or other suitable materials. All combinations of materials that can be selectively removed can be used as the first dielectric layer and the second dielectric layer without affecting the operation of the device. As shown in Fig. 3, after the second electrical layer 24a is formed, a protective material such as the first photoresist layer 26 may be formed on the third gate stack 20. The first photoresist layer 26 can be used to protect the second gate stack 20 on the second dielectric layer 24a on the first gate stack 16 and the second gate stack 18, for example, by etching. Dielectric layer 24a is protected from etching removal. The formation of the first photoresist layer 26 may include coating a photoresist layer on the substrate 10, and then exposing and developing the photoresist layer to form only the third gate stack 20

Client's Docket N〇.: 96-040 TT5s Docket No: 0492-A41402-TW/f/JYChen 10 1353640. The first photoresist layer 26. However, other mask layers may be used in place of the first photoresist layer 26. Next, referring to FIG. 4, the first dielectric layer 24 on the first gate stack 16 and the second gate stack U is exposed by removing the first dielectric layer 24a not protected by the first photoresist layer 26. . The removal of the second dielectric layer 24a may be performed using a dry etching method or a wet etching method. Since the material of the second dielectric layer 24a is different from that of the second layer 22, the second dielectric layer 24a can be selectively removed by a suitable removal process. For example, when the material of the first dielectric layer 22 is oxidized stone and the material of the second dielectric layer 24a is nitrided, a suitable dry etching is preferably by anisotropic reactive ion etching (anis〇tr). 〇pic • RIE) ' Suitable etchants include chf4/o2, CF4/H2, c2F6, c3F8, ΝΙ?3, combinations of the foregoing, and the like. A suitable wet-money engraving method involves etching the second dielectric layer 24a (tantalum nitride layer) using a hot liquid acid solution (about 15 Å. 〇 about 200X: between). Next, the protective material on the third gate stack 20 is removed, such as the first photoresist layer 26 of FIG. The removal of the first photoresist layer 26 can be carried out by wet stripping or dry stripping. The wet stripping method involves the use of an organic solvent such as an internal and an aromatic solvent or an inorganic solution such as sulfuric acid or hydrogen peroxide to remove the photoresist. The dry stripping method includes using a milk electric device to ash a photoresist, and reacting the photoresist material into gaseous CO, C〇2, and H2〇 to remove. A second stage of deposition of the second dielectric layer (i.e., second dielectric layer 24b) is then performed. As shown in FIG. 5, after removing a portion of the second dielectric layer 24a and the first photoresist layer 26, a second dielectric layer may be formed on the substrate 10 by, for example, chemical vapor deposition (ie, Two dielectric layers 24b). The second dielectric layer 24b formed again and the first dielectric layer 22 will be combined in a subsequent process.

Client's Docket No.: 96-040 TT's Docket No: 0492-A41402-TW/f/JYChen 1353640 The gap between the two gate stacks 18. The thickness of the second dielectric layer 24b can be adjusted according to the requirement of the low voltage component to which the second gate stack 18 belongs, but it is still not too thick to avoid defects in the high aspect ratio opening in the array region 12, the second The thickness of the electrical layer 24b is exemplified by a 90 nm process, from about 200 A to about -600 A, preferably about 400 A. Next, as shown in FIG. 6, the second dielectric layer 24b and the second dielectric layer 24a are formed again by etch back to expose the first gate stack 16, the second gate stack 18, and the first The first dielectric layer 22 of the top portion of the three gate stack 20. Similar to the removal of the second dielectric layer 24a in FIG. 4, since the material of the second dielectric layer 24b is different from that of the first dielectric layer 22, it can be selectively removed by a suitable etch back process. Two dielectric layers 24b. Preferably, the second dielectric layer 24b is etched back and forth using an anisotropic etch, such as by reactive ion etching (RIE), and the etchant used may be selected from the material of the second dielectric layer 24b. In addition, since the third gate stack 20 was previously protected by the first photoresist layer 26 and the second dielectric layers 24a and 24b were deposited twice, the second dielectric layer around the third gate stack 20 ( The thicknesses of 24a and 24b) are greater than the second dielectric layer (24b) around the second gate stack 18. The total thickness of the second dielectric layers 24a and 24b around the third gate stack 20 is exemplified by a 90 nm process, about 1000 A to about 1400 A, preferably about 1200 A. Referring next to FIG. 7, a protective material such as a second photoresist layer 28 may be formed on the substrate 10 to protect the second dielectric layer 24 in the peripheral region 14. The second photoresist layer 28 can be formed similar to the method of the first photoresist layer 26. As shown in Fig. 8, the protective material forming the peripheral region 14 (for example, the seventh

Client's Docket No.: 96-040 TT's Docket No: 0492-A41402-TW/f/JYChen 12 1353640. After the second photoresist layer 28), it can be removed by, for example, dry etching or wet etching. The second dielectric layer 24b in the array region 12. Similar to the removal of the first two dielectric layers 24a or 24b, since the material of the second dielectric layer 24b is different from the first dielectric layer 22, the first of the array regions 12 can be selectively removed. Two dielectric layers 24b. Referring to FIG. 9, after the second photoresist layer 28 is removed, the first dielectric layer 22 is etched back to expose the first gate stack 16, the second gate stack 18, and the third gate. The upper surface of the stack 20 and the sidewalls of the first gate stack 16, the second gate stack 18, and the third gate stack 20 respectively form a first spacer, a second spacer, and a third spacer. Preferably, the first dielectric layer 22 is etched back and forth using an anisotropic etch, such as by reactive ion etching (RIE), and the etchant used may be selected from the material of the first dielectric layer 22. Wherein, the thickness of the first spacer is largely determined by the thickness of the first dielectric layer 22, and the second spacer and the third spacer are respectively formed by the first dielectric layer 22 and the second dielectric layer (24b or 24a and 24b) )Composed together. In an embodiment of the invention, the second spacer and the third spacer are composite spacers composed of the first dielectric layer 22 and the second dielectric layer (24b or 24a and 24b). And wherein the first dielectric layer 22 is of the "L" type (as shown in FIG. 9). The substrate 10 can then be subjected to an ion implantation process to form a source/drain region. As shown in FIG. 10, the substrate 10 is subjected to an ion implantation process by using the formed first spacer, the second spacer, and the third spacer as masks, respectively, in the first gate stack 16, and the second The gate stack 18 and the substrate 10 on both sides of the spacer of the third gate stack 20 respectively form a first source/drain region

Client's Docket No.: 96-040 TT^ Docket No: 0492-A41402-TW/f/JYChen 13 / primary pole/; and pole region 18a, and third source/drain region 20a. For example, the present invention has many advantages, such as different components (4) of the implementation of the present invention, forming a channel of different lengths between the gaps of the thicknesses of the gaps (sources: seeking曰1 distance) or lightly doped source/drain regions to meet the requirements of different components, and by combining thinner dielectric layers to form thicker gaps to avoid thicker dielectric layers The resulting defects, for example, due to the order [cavity or overhang (GVei " hang) and other unfavorable follow-up. Moreover, in the present invention-embodiment, only two mask processes can be used to form a spacer of two thicknesses, which can save costs. It will be appreciated by those skilled in the art that there are many components in a semiconductor structure: however, the optimum spacer thicknesses are different from each other, the embodiment of the present invention, and the spacers of the three thicknesses that optimize the overall performance of the component. Those skilled in the art will be able to form three gaps of thickness = thickness to meet the needs of individual semiconductor structures without departing from the spirit of the invention. Three or more thickness spacers may also be formed to form three or more channel regions or lightly doped source regions to optimize the operation of the semiconductor structure. The present invention has been disclosed in the above preferred embodiments, and is not intended to limit the invention. Any of the embodiments of the present invention can be used in any way without departing from the spirit and scope of the present invention. The scope of protection of the present invention is subject to the scope of application of the invention; [Simple description of the map]

Clienfs Docket No.: 96-040 TT, s Docket No: 0492-A41402-TW/f/JYChen 1353640 FIGS. 1 to 10 are a series of process cross-sectional views for explaining three different forms in an embodiment of the present invention. The manufacturing process of the thickness spacer. [Main component symbol description] 10~substrate; 12~array area; 14~peripheral area; 16~first gate stack; 18~second gate stack; 20~third gate stack; 11~ shallow trench insulation 16a~first lightly doped source/nopole region; 18a~second lightly doped source/drain region; 20a~third lightly doped source/drain region; 22~first dielectric Layer; 24a~ (first deposited) second dielectric layer; 26~ first photoresist layer; 24b~ (second deposited) second dielectric layer; 28~ second photoresist layer; 16b~ The first source/drain region, 181) to the second source/> and the polar region, 20b to the second source/pole region.

Client's Docket No.: 96-040 TT's Docket No:0492-A41402-TW/f/JYChen 15

Claims (1)

1353640 No. 96146066 Application Patent Revision Amendment 100 years June 14 a repair i replacement page month, f day revision ten, patent application scope: 1. A method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a An array region and a peripheral region, and the array region includes a plurality of first gate stacks, wherein the peripheral region includes a second gate stack of a low voltage component and a third gate stack of a high voltage component; forming a a first dielectric layer covering the first gate stack, the second gate stack, and the third gate stack and sidewalls; depositing a second dielectric layer on the first dielectric layer; Removing the second dielectric layer on the first gate stack and the second gate stack, leaving the second dielectric layer on the third gate stack; depositing the second dielectric again An electric layer is disposed on the first gate stack, the second gate stack, and the third gate stack; the second dielectric layer is etched back to expose the first gate stacks, the second a gate stack, and the first dielectric on the third gate stack a layer; removing the second dielectric layer in the array region to expose the first dielectric layer; and returning the first dielectric layer to expose the first gate stack, the second gate And stacking the upper surface of the third gate stack, and forming a first spacer and a second sidewall respectively on the sidewalls of the first gate stack, the second gate stack, and the third gate stack a spacer, and a third spacer; wherein the thickness of the third spacer is greater than the second spacer, and the Client^ Docket No.: 96-040 TT's Docket No: 0492-A41402TWFl/JYChen 16 ^53640 f96146066 Please refer to the patent fine revision section - the thickness of the spacer is larger than the first spacer. 2. The method of claim 2, wherein the first dielectric layer is formed of the following different materials, including a oxidized stone material selected from the group consisting of: =导=". The method further includes encapsulating a second open layer to protect the third gate stack prior to removing the second dielectric layer on the stack. 4帛~ photoresist (such as the method described in the patent application (4)!] wherein the second dielectric is removed in the array region; = before forming: the dielectric layer is further formed first - second light "= a gate stack and a third gate stack. Hai. 5. The half of the method described in the scope of the patent: [the method] wherein the second dielectric layer is backed by the second and third gaps The first dielectric layer in the wall is etched into an L-shape. The method for forming a semiconductor structure according to the above-mentioned patent scope includes the first spacer, the second spacer, or The three spacers are masks and the substrate is subjected to an ion implantation process to = at least one source/drain region. / Client's Docket ΤΜ〇.: 96-040 TT^ Docket Νο:0492-Α4 1402TWF1 /JYChen 17